1/* $FreeBSD: releng/11.0/sys/dev/usb/controller/at91dci.c 298932 2016-05-02 17:44:03Z pfg $ */ 2/*- 3 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * This file contains the driver for the AT91 series USB Device 29 * Controller 30 */ 31 32/* 33 * Thanks to "David Brownell" for helping out regarding the hardware 34 * endpoint profiles. 35 */ 36 37/* 38 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 39 * reset. 40 * 41 * NOTE: When the chip detects BUS-reset it will also reset the 42 * endpoints, Function-address and more. 43 */ 44 45#ifdef USB_GLOBAL_INCLUDE_FILE 46#include USB_GLOBAL_INCLUDE_FILE 47#else 48#include <sys/stdint.h> 49#include <sys/stddef.h> 50#include <sys/param.h> 51#include <sys/queue.h> 52#include <sys/types.h> 53#include <sys/systm.h> 54#include <sys/kernel.h> 55#include <sys/bus.h> 56#include <sys/module.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/condvar.h> 60#include <sys/sysctl.h> 61#include <sys/sx.h> 62#include <sys/unistd.h> 63#include <sys/callout.h> 64#include <sys/malloc.h> 65#include <sys/priv.h> 66 67#include <dev/usb/usb.h> 68#include <dev/usb/usbdi.h> 69 70#define USB_DEBUG_VAR at91dcidebug 71 72#include <dev/usb/usb_core.h> 73#include <dev/usb/usb_debug.h> 74#include <dev/usb/usb_busdma.h> 75#include <dev/usb/usb_process.h> 76#include <dev/usb/usb_transfer.h> 77#include <dev/usb/usb_device.h> 78#include <dev/usb/usb_hub.h> 79#include <dev/usb/usb_util.h> 80 81#include <dev/usb/usb_controller.h> 82#include <dev/usb/usb_bus.h> 83#endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85#include <dev/usb/controller/at91dci.h> 86 87#define AT9100_DCI_BUS2SC(bus) \ 88 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 89 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 90 91#define AT9100_DCI_PC2SC(pc) \ 92 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 93 94#define AT9100_DCI_THREAD_IRQ \ 95 (AT91_UDP_INT_BUS | AT91_UDP_INT_END_BR | AT91_UDP_INT_RXRSM | AT91_UDP_INT_RXSUSP) 96 97#ifdef USB_DEBUG 98static int at91dcidebug = 0; 99 100static SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 101SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &at91dcidebug, 0, "at91dci debug level"); 103#endif 104 105#define AT9100_DCI_INTR_ENDPT 1 106 107/* prototypes */ 108 109static const struct usb_bus_methods at91dci_bus_methods; 110static const struct usb_pipe_methods at91dci_device_bulk_methods; 111static const struct usb_pipe_methods at91dci_device_ctrl_methods; 112static const struct usb_pipe_methods at91dci_device_intr_methods; 113static const struct usb_pipe_methods at91dci_device_isoc_fs_methods; 114 115static at91dci_cmd_t at91dci_setup_rx; 116static at91dci_cmd_t at91dci_data_rx; 117static at91dci_cmd_t at91dci_data_tx; 118static at91dci_cmd_t at91dci_data_tx_sync; 119static void at91dci_device_done(struct usb_xfer *, usb_error_t); 120static void at91dci_do_poll(struct usb_bus *); 121static void at91dci_standard_done(struct usb_xfer *); 122static void at91dci_root_intr(struct at91dci_softc *sc); 123 124/* 125 * NOTE: Some of the bits in the CSR register have inverse meaning so 126 * we need a helper macro when acknowledging events: 127 */ 128#define AT91_CSR_ACK(csr, what) do { \ 129 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 130 AT91_UDP_CSR_TXPKTRDY| \ 131 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 132 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 133 AT91_UDP_CSR_RX_DATA_BK1| \ 134 AT91_UDP_CSR_TXCOMP| \ 135 AT91_UDP_CSR_RXSETUP| \ 136 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 137} while (0) 138 139/* 140 * Here is a list of what the chip supports. 141 * Probably it supports more than listed here! 142 */ 143static const struct usb_hw_ep_profile 144 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 145 146 [0] = { 147 .max_in_frame_size = 8, 148 .max_out_frame_size = 8, 149 .is_simplex = 1, 150 .support_control = 1, 151 }, 152 [1] = { 153 .max_in_frame_size = 64, 154 .max_out_frame_size = 64, 155 .is_simplex = 1, 156 .support_multi_buffer = 1, 157 .support_bulk = 1, 158 .support_interrupt = 1, 159 .support_isochronous = 1, 160 .support_in = 1, 161 .support_out = 1, 162 }, 163 [2] = { 164 .max_in_frame_size = 64, 165 .max_out_frame_size = 64, 166 .is_simplex = 1, 167 .support_multi_buffer = 1, 168 .support_bulk = 1, 169 .support_interrupt = 1, 170 .support_isochronous = 1, 171 .support_in = 1, 172 .support_out = 1, 173 }, 174 [3] = { 175 /* can also do BULK */ 176 .max_in_frame_size = 8, 177 .max_out_frame_size = 8, 178 .is_simplex = 1, 179 .support_interrupt = 1, 180 .support_in = 1, 181 .support_out = 1, 182 }, 183 [4] = { 184 .max_in_frame_size = 256, 185 .max_out_frame_size = 256, 186 .is_simplex = 1, 187 .support_multi_buffer = 1, 188 .support_bulk = 1, 189 .support_interrupt = 1, 190 .support_isochronous = 1, 191 .support_in = 1, 192 .support_out = 1, 193 }, 194 [5] = { 195 .max_in_frame_size = 256, 196 .max_out_frame_size = 256, 197 .is_simplex = 1, 198 .support_multi_buffer = 1, 199 .support_bulk = 1, 200 .support_interrupt = 1, 201 .support_isochronous = 1, 202 .support_in = 1, 203 .support_out = 1, 204 }, 205}; 206 207static void 208at91dci_get_hw_ep_profile(struct usb_device *udev, 209 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 210{ 211 if (ep_addr < AT91_UDP_EP_MAX) { 212 *ppf = (at91dci_ep_profile + ep_addr); 213 } else { 214 *ppf = NULL; 215 } 216} 217 218static void 219at91dci_clocks_on(struct at91dci_softc *sc) 220{ 221 if (sc->sc_flags.clocks_off && 222 sc->sc_flags.port_powered) { 223 224 DPRINTFN(5, "\n"); 225 226 if (sc->sc_clocks_on) { 227 (sc->sc_clocks_on) (sc->sc_clocks_arg); 228 } 229 sc->sc_flags.clocks_off = 0; 230 231 /* enable Transceiver */ 232 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 233 } 234} 235 236static void 237at91dci_clocks_off(struct at91dci_softc *sc) 238{ 239 if (!sc->sc_flags.clocks_off) { 240 241 DPRINTFN(5, "\n"); 242 243 /* disable Transceiver */ 244 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 245 246 if (sc->sc_clocks_off) { 247 (sc->sc_clocks_off) (sc->sc_clocks_arg); 248 } 249 sc->sc_flags.clocks_off = 1; 250 } 251} 252 253static void 254at91dci_pull_up(struct at91dci_softc *sc) 255{ 256 /* pullup D+, if possible */ 257 258 if (!sc->sc_flags.d_pulled_up && 259 sc->sc_flags.port_powered) { 260 sc->sc_flags.d_pulled_up = 1; 261 (sc->sc_pull_up) (sc->sc_pull_arg); 262 } 263} 264 265static void 266at91dci_pull_down(struct at91dci_softc *sc) 267{ 268 /* pulldown D+, if possible */ 269 270 if (sc->sc_flags.d_pulled_up) { 271 sc->sc_flags.d_pulled_up = 0; 272 (sc->sc_pull_down) (sc->sc_pull_arg); 273 } 274} 275 276static void 277at91dci_wakeup_peer(struct at91dci_softc *sc) 278{ 279 if (!(sc->sc_flags.status_suspend)) { 280 return; 281 } 282 283 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 284 285 /* wait 8 milliseconds */ 286 /* Wait for reset to complete. */ 287 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 288 289 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 290} 291 292static void 293at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 294{ 295 DPRINTFN(5, "addr=%d\n", addr); 296 297 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 298 AT91_UDP_FADDR_EN); 299} 300 301static uint8_t 302at91dci_setup_rx(struct at91dci_softc *sc, struct at91dci_td *td) 303{ 304 struct usb_device_request req; 305 uint32_t csr; 306 uint32_t temp; 307 uint16_t count; 308 309 /* read out FIFO status */ 310 csr = AT91_UDP_READ_4(sc, td->status_reg); 311 312 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 313 314 temp = csr; 315 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 316 AT91_UDP_CSR_RX_DATA_BK1 | 317 AT91_UDP_CSR_STALLSENT | 318 AT91_UDP_CSR_RXSETUP | 319 AT91_UDP_CSR_TXCOMP); 320 321 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 322 goto not_complete; 323 } 324 /* clear did stall */ 325 td->did_stall = 0; 326 327 /* get the packet byte count */ 328 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 329 330 /* verify data length */ 331 if (count != td->remainder) { 332 DPRINTFN(0, "Invalid SETUP packet " 333 "length, %d bytes\n", count); 334 goto not_complete; 335 } 336 if (count != sizeof(req)) { 337 DPRINTFN(0, "Unsupported SETUP packet " 338 "length, %d bytes\n", count); 339 goto not_complete; 340 } 341 /* receive data */ 342 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 343 td->fifo_reg, (void *)&req, sizeof(req)); 344 345 /* copy data into real buffer */ 346 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 347 348 td->offset = sizeof(req); 349 td->remainder = 0; 350 351 /* sneak peek the set address */ 352 if ((req.bmRequestType == UT_WRITE_DEVICE) && 353 (req.bRequest == UR_SET_ADDRESS)) { 354 sc->sc_dv_addr = req.wValue[0] & 0x7F; 355 } else { 356 sc->sc_dv_addr = 0xFF; 357 } 358 359 /* sneak peek the endpoint direction */ 360 if (req.bmRequestType & UE_DIR_IN) { 361 csr |= AT91_UDP_CSR_DIR; 362 } else { 363 csr &= ~AT91_UDP_CSR_DIR; 364 } 365 366 /* write the direction of the control transfer */ 367 AT91_CSR_ACK(csr, temp); 368 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 369 return (0); /* complete */ 370 371not_complete: 372 /* abort any ongoing transfer */ 373 if (!td->did_stall) { 374 DPRINTFN(5, "stalling\n"); 375 temp |= AT91_UDP_CSR_FORCESTALL; 376 td->did_stall = 1; 377 } 378 379 /* clear interrupts, if any */ 380 if (temp) { 381 DPRINTFN(5, "clearing 0x%08x\n", temp); 382 AT91_CSR_ACK(csr, temp); 383 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 384 } 385 return (1); /* not complete */ 386} 387 388static uint8_t 389at91dci_data_rx(struct at91dci_softc *sc, struct at91dci_td *td) 390{ 391 struct usb_page_search buf_res; 392 uint32_t csr; 393 uint32_t temp; 394 uint16_t count; 395 uint8_t to; 396 uint8_t got_short; 397 398 to = 2; /* don't loop forever! */ 399 got_short = 0; 400 401 /* check if any of the FIFO banks have data */ 402repeat: 403 /* read out FIFO status */ 404 csr = AT91_UDP_READ_4(sc, td->status_reg); 405 406 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 407 408 if (csr & AT91_UDP_CSR_RXSETUP) { 409 if (td->remainder == 0) { 410 /* 411 * We are actually complete and have 412 * received the next SETUP 413 */ 414 DPRINTFN(5, "faking complete\n"); 415 return (0); /* complete */ 416 } 417 /* 418 * USB Host Aborted the transfer. 419 */ 420 td->error = 1; 421 return (0); /* complete */ 422 } 423 /* Make sure that "STALLSENT" gets cleared */ 424 temp = csr; 425 temp &= AT91_UDP_CSR_STALLSENT; 426 427 /* check status */ 428 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 429 AT91_UDP_CSR_RX_DATA_BK1))) { 430 if (temp) { 431 /* write command */ 432 AT91_CSR_ACK(csr, temp); 433 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 434 } 435 return (1); /* not complete */ 436 } 437 /* get the packet byte count */ 438 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 439 440 /* verify the packet byte count */ 441 if (count != td->max_packet_size) { 442 if (count < td->max_packet_size) { 443 /* we have a short packet */ 444 td->short_pkt = 1; 445 got_short = 1; 446 } else { 447 /* invalid USB packet */ 448 td->error = 1; 449 return (0); /* we are complete */ 450 } 451 } 452 /* verify the packet byte count */ 453 if (count > td->remainder) { 454 /* invalid USB packet */ 455 td->error = 1; 456 return (0); /* we are complete */ 457 } 458 while (count > 0) { 459 usbd_get_page(td->pc, td->offset, &buf_res); 460 461 /* get correct length */ 462 if (buf_res.length > count) { 463 buf_res.length = count; 464 } 465 /* receive data */ 466 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 467 td->fifo_reg, buf_res.buffer, buf_res.length); 468 469 /* update counters */ 470 count -= buf_res.length; 471 td->offset += buf_res.length; 472 td->remainder -= buf_res.length; 473 } 474 475 /* clear status bits */ 476 if (td->support_multi_buffer) { 477 if (td->fifo_bank) { 478 td->fifo_bank = 0; 479 temp |= AT91_UDP_CSR_RX_DATA_BK1; 480 } else { 481 td->fifo_bank = 1; 482 temp |= AT91_UDP_CSR_RX_DATA_BK0; 483 } 484 } else { 485 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 486 AT91_UDP_CSR_RX_DATA_BK1); 487 } 488 489 /* write command */ 490 AT91_CSR_ACK(csr, temp); 491 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 492 493 /* 494 * NOTE: We may have to delay a little bit before 495 * proceeding after clearing the DATA_BK bits. 496 */ 497 498 /* check if we are complete */ 499 if ((td->remainder == 0) || got_short) { 500 if (td->short_pkt) { 501 /* we are complete */ 502 return (0); 503 } 504 /* else need to receive a zero length packet */ 505 } 506 if (--to) { 507 goto repeat; 508 } 509 return (1); /* not complete */ 510} 511 512static uint8_t 513at91dci_data_tx(struct at91dci_softc *sc, struct at91dci_td *td) 514{ 515 struct usb_page_search buf_res; 516 uint32_t csr; 517 uint32_t temp; 518 uint16_t count; 519 uint8_t to; 520 521 to = 2; /* don't loop forever! */ 522 523repeat: 524 525 /* read out FIFO status */ 526 csr = AT91_UDP_READ_4(sc, td->status_reg); 527 528 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 529 530 if (csr & AT91_UDP_CSR_RXSETUP) { 531 /* 532 * The current transfer was aborted 533 * by the USB Host 534 */ 535 td->error = 1; 536 return (0); /* complete */ 537 } 538 /* Make sure that "STALLSENT" gets cleared */ 539 temp = csr; 540 temp &= AT91_UDP_CSR_STALLSENT; 541 542 if (csr & AT91_UDP_CSR_TXPKTRDY) { 543 if (temp) { 544 /* write command */ 545 AT91_CSR_ACK(csr, temp); 546 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 547 } 548 return (1); /* not complete */ 549 } else { 550 /* clear TXCOMP and set TXPKTRDY */ 551 temp |= (AT91_UDP_CSR_TXCOMP | 552 AT91_UDP_CSR_TXPKTRDY); 553 } 554 555 count = td->max_packet_size; 556 if (td->remainder < count) { 557 /* we have a short packet */ 558 td->short_pkt = 1; 559 count = td->remainder; 560 } 561 while (count > 0) { 562 usbd_get_page(td->pc, td->offset, &buf_res); 563 564 /* get correct length */ 565 if (buf_res.length > count) { 566 buf_res.length = count; 567 } 568 /* transmit data */ 569 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 570 td->fifo_reg, buf_res.buffer, buf_res.length); 571 572 /* update counters */ 573 count -= buf_res.length; 574 td->offset += buf_res.length; 575 td->remainder -= buf_res.length; 576 } 577 578 /* write command */ 579 AT91_CSR_ACK(csr, temp); 580 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 581 582 /* check remainder */ 583 if (td->remainder == 0) { 584 if (td->short_pkt) { 585 return (0); /* complete */ 586 } 587 /* else we need to transmit a short packet */ 588 } 589 if (--to) { 590 goto repeat; 591 } 592 return (1); /* not complete */ 593} 594 595static uint8_t 596at91dci_data_tx_sync(struct at91dci_softc *sc, struct at91dci_td *td) 597{ 598 uint32_t csr; 599 uint32_t temp; 600 601 /* read out FIFO status */ 602 csr = AT91_UDP_READ_4(sc, td->status_reg); 603 604 DPRINTFN(5, "csr=0x%08x\n", csr); 605 606 if (csr & AT91_UDP_CSR_RXSETUP) { 607 DPRINTFN(5, "faking complete\n"); 608 /* Race condition */ 609 return (0); /* complete */ 610 } 611 temp = csr; 612 temp &= (AT91_UDP_CSR_STALLSENT | 613 AT91_UDP_CSR_TXCOMP); 614 615 /* check status */ 616 if (csr & AT91_UDP_CSR_TXPKTRDY) { 617 goto not_complete; 618 } 619 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 620 goto not_complete; 621 } 622 if (td->status_reg == AT91_UDP_CSR(0) && sc->sc_dv_addr != 0xFF) { 623 /* 624 * The AT91 has a special requirement with regard to 625 * setting the address and that is to write the new 626 * address before clearing TXCOMP: 627 */ 628 at91dci_set_address(sc, sc->sc_dv_addr); 629 } 630 /* write command */ 631 AT91_CSR_ACK(csr, temp); 632 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 633 634 return (0); /* complete */ 635 636not_complete: 637 if (temp) { 638 /* write command */ 639 AT91_CSR_ACK(csr, temp); 640 AT91_UDP_WRITE_4(sc, td->status_reg, csr); 641 } 642 return (1); /* not complete */ 643} 644 645static void 646at91dci_xfer_do_fifo(struct usb_xfer *xfer) 647{ 648 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 649 struct at91dci_td *td; 650 uint8_t temp; 651 652 DPRINTFN(9, "\n"); 653 654 td = xfer->td_transfer_cache; 655 if (td == NULL) 656 return; 657 658 while (1) { 659 if ((td->func) (sc, td)) { 660 /* operation in progress */ 661 break; 662 } 663 if (((void *)td) == xfer->td_transfer_last) { 664 goto done; 665 } 666 if (td->error) { 667 goto done; 668 } else if (td->remainder > 0) { 669 /* 670 * We had a short transfer. If there is no alternate 671 * next, stop processing ! 672 */ 673 if (!td->alt_next) { 674 goto done; 675 } 676 } 677 /* 678 * Fetch the next transfer descriptor and transfer 679 * some flags to the next transfer descriptor 680 */ 681 temp = 0; 682 if (td->fifo_bank) 683 temp |= 1; 684 td = td->obj_next; 685 xfer->td_transfer_cache = td; 686 if (temp & 1) 687 td->fifo_bank = 1; 688 } 689 return; 690 691done: 692 temp = (xfer->endpointno & UE_ADDR); 693 694 /* update FIFO bank flag and multi buffer */ 695 if (td->fifo_bank) { 696 sc->sc_ep_flags[temp].fifo_bank = 1; 697 } else { 698 sc->sc_ep_flags[temp].fifo_bank = 0; 699 } 700 701 /* compute all actual lengths */ 702 xfer->td_transfer_cache = NULL; 703 sc->sc_xfer_complete = 1; 704} 705 706static uint8_t 707at91dci_xfer_do_complete(struct usb_xfer *xfer) 708{ 709 struct at91dci_td *td; 710 711 DPRINTFN(9, "\n"); 712 td = xfer->td_transfer_cache; 713 if (td == NULL) { 714 /* compute all actual lengths */ 715 at91dci_standard_done(xfer); 716 return(1); 717 } 718 return (0); 719} 720 721static void 722at91dci_interrupt_poll_locked(struct at91dci_softc *sc) 723{ 724 struct usb_xfer *xfer; 725 726 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 727 at91dci_xfer_do_fifo(xfer); 728} 729 730static void 731at91dci_interrupt_complete_locked(struct at91dci_softc *sc) 732{ 733 struct usb_xfer *xfer; 734repeat: 735 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 736 if (at91dci_xfer_do_complete(xfer)) 737 goto repeat; 738 } 739} 740 741void 742at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 743{ 744 DPRINTFN(5, "vbus = %u\n", is_on); 745 746 if (is_on) { 747 if (!sc->sc_flags.status_vbus) { 748 sc->sc_flags.status_vbus = 1; 749 750 /* complete root HUB interrupt endpoint */ 751 at91dci_root_intr(sc); 752 } 753 } else { 754 if (sc->sc_flags.status_vbus) { 755 sc->sc_flags.status_vbus = 0; 756 sc->sc_flags.status_bus_reset = 0; 757 sc->sc_flags.status_suspend = 0; 758 sc->sc_flags.change_suspend = 0; 759 sc->sc_flags.change_connect = 1; 760 761 /* complete root HUB interrupt endpoint */ 762 at91dci_root_intr(sc); 763 } 764 } 765} 766 767int 768at91dci_filter_interrupt(void *arg) 769{ 770 struct at91dci_softc *sc = arg; 771 int retval = FILTER_HANDLED; 772 uint32_t status; 773 774 USB_BUS_SPIN_LOCK(&sc->sc_bus); 775 776 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 777 status &= AT91_UDP_INT_DEFAULT; 778 779 if (status & AT9100_DCI_THREAD_IRQ) 780 retval = FILTER_SCHEDULE_THREAD; 781 782 /* acknowledge interrupts */ 783 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status & ~AT9100_DCI_THREAD_IRQ); 784 785 /* poll FIFOs, if any */ 786 at91dci_interrupt_poll_locked(sc); 787 788 if (sc->sc_xfer_complete != 0) 789 retval = FILTER_SCHEDULE_THREAD; 790 791 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 792 793 return (retval); 794} 795 796void 797at91dci_interrupt(void *arg) 798{ 799 struct at91dci_softc *sc = arg; 800 uint32_t status; 801 802 USB_BUS_LOCK(&sc->sc_bus); 803 USB_BUS_SPIN_LOCK(&sc->sc_bus); 804 805 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 806 status &= AT9100_DCI_THREAD_IRQ; 807 808 /* acknowledge interrupts */ 809 810 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 811 812 /* check for any bus state change interrupts */ 813 814 if (status & AT91_UDP_INT_BUS) { 815 816 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 817 818 if (status & AT91_UDP_INT_END_BR) { 819 820 /* set correct state */ 821 sc->sc_flags.status_bus_reset = 1; 822 sc->sc_flags.status_suspend = 0; 823 sc->sc_flags.change_suspend = 0; 824 sc->sc_flags.change_connect = 1; 825 826 /* disable resume interrupt */ 827 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 828 AT91_UDP_INT_RXRSM); 829 /* enable suspend interrupt */ 830 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 831 AT91_UDP_INT_RXSUSP); 832 } 833 /* 834 * If RXRSM and RXSUSP is set at the same time we interpret 835 * that like RESUME. Resume is set when there is at least 3 836 * milliseconds of inactivity on the USB BUS. 837 */ 838 if (status & AT91_UDP_INT_RXRSM) { 839 if (sc->sc_flags.status_suspend) { 840 sc->sc_flags.status_suspend = 0; 841 sc->sc_flags.change_suspend = 1; 842 843 /* disable resume interrupt */ 844 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 845 AT91_UDP_INT_RXRSM); 846 /* enable suspend interrupt */ 847 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 848 AT91_UDP_INT_RXSUSP); 849 } 850 } else if (status & AT91_UDP_INT_RXSUSP) { 851 if (!sc->sc_flags.status_suspend) { 852 sc->sc_flags.status_suspend = 1; 853 sc->sc_flags.change_suspend = 1; 854 855 /* disable suspend interrupt */ 856 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 857 AT91_UDP_INT_RXSUSP); 858 859 /* enable resume interrupt */ 860 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 861 AT91_UDP_INT_RXRSM); 862 } 863 } 864 /* complete root HUB interrupt endpoint */ 865 at91dci_root_intr(sc); 866 } 867 868 if (sc->sc_xfer_complete != 0) { 869 sc->sc_xfer_complete = 0; 870 at91dci_interrupt_complete_locked(sc); 871 } 872 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 873 USB_BUS_UNLOCK(&sc->sc_bus); 874} 875 876static void 877at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 878{ 879 struct at91dci_td *td; 880 881 /* get current Transfer Descriptor */ 882 td = temp->td_next; 883 temp->td = td; 884 885 /* prepare for next TD */ 886 temp->td_next = td->obj_next; 887 888 /* fill out the Transfer Descriptor */ 889 td->func = temp->func; 890 td->pc = temp->pc; 891 td->offset = temp->offset; 892 td->remainder = temp->len; 893 td->fifo_bank = 0; 894 td->error = 0; 895 td->did_stall = temp->did_stall; 896 td->short_pkt = temp->short_pkt; 897 td->alt_next = temp->setup_alt_next; 898} 899 900static void 901at91dci_setup_standard_chain(struct usb_xfer *xfer) 902{ 903 struct at91dci_std_temp temp; 904 struct at91dci_softc *sc; 905 struct at91dci_td *td; 906 uint32_t x; 907 uint8_t ep_no; 908 uint8_t need_sync; 909 910 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 911 xfer->address, UE_GET_ADDR(xfer->endpointno), 912 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 913 914 temp.max_frame_size = xfer->max_frame_size; 915 916 td = xfer->td_start[0]; 917 xfer->td_transfer_first = td; 918 xfer->td_transfer_cache = td; 919 920 /* setup temp */ 921 922 temp.pc = NULL; 923 temp.td = NULL; 924 temp.td_next = xfer->td_start[0]; 925 temp.offset = 0; 926 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 927 xfer->flags_int.isochronous_xfr; 928 temp.did_stall = !xfer->flags_int.control_stall; 929 930 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 931 ep_no = (xfer->endpointno & UE_ADDR); 932 933 /* check if we should prepend a setup message */ 934 935 if (xfer->flags_int.control_xfr) { 936 if (xfer->flags_int.control_hdr) { 937 938 temp.func = &at91dci_setup_rx; 939 temp.len = xfer->frlengths[0]; 940 temp.pc = xfer->frbuffers + 0; 941 temp.short_pkt = temp.len ? 1 : 0; 942 /* check for last frame */ 943 if (xfer->nframes == 1) { 944 /* no STATUS stage yet, SETUP is last */ 945 if (xfer->flags_int.control_act) 946 temp.setup_alt_next = 0; 947 } 948 949 at91dci_setup_standard_chain_sub(&temp); 950 } 951 x = 1; 952 } else { 953 x = 0; 954 } 955 956 if (x != xfer->nframes) { 957 if (xfer->endpointno & UE_DIR_IN) { 958 temp.func = &at91dci_data_tx; 959 need_sync = 1; 960 } else { 961 temp.func = &at91dci_data_rx; 962 need_sync = 0; 963 } 964 965 /* setup "pc" pointer */ 966 temp.pc = xfer->frbuffers + x; 967 } else { 968 need_sync = 0; 969 } 970 while (x != xfer->nframes) { 971 972 /* DATA0 / DATA1 message */ 973 974 temp.len = xfer->frlengths[x]; 975 976 x++; 977 978 if (x == xfer->nframes) { 979 if (xfer->flags_int.control_xfr) { 980 if (xfer->flags_int.control_act) { 981 temp.setup_alt_next = 0; 982 } 983 } else { 984 temp.setup_alt_next = 0; 985 } 986 } 987 if (temp.len == 0) { 988 989 /* make sure that we send an USB packet */ 990 991 temp.short_pkt = 0; 992 993 } else { 994 995 /* regular data transfer */ 996 997 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 998 } 999 1000 at91dci_setup_standard_chain_sub(&temp); 1001 1002 if (xfer->flags_int.isochronous_xfr) { 1003 temp.offset += temp.len; 1004 } else { 1005 /* get next Page Cache pointer */ 1006 temp.pc = xfer->frbuffers + x; 1007 } 1008 } 1009 1010 /* check for control transfer */ 1011 if (xfer->flags_int.control_xfr) { 1012 1013 /* always setup a valid "pc" pointer for status and sync */ 1014 temp.pc = xfer->frbuffers + 0; 1015 temp.len = 0; 1016 temp.short_pkt = 0; 1017 temp.setup_alt_next = 0; 1018 1019 /* check if we need to sync */ 1020 if (need_sync) { 1021 /* we need a SYNC point after TX */ 1022 temp.func = &at91dci_data_tx_sync; 1023 at91dci_setup_standard_chain_sub(&temp); 1024 } 1025 1026 /* check if we should append a status stage */ 1027 if (!xfer->flags_int.control_act) { 1028 1029 /* 1030 * Send a DATA1 message and invert the current 1031 * endpoint direction. 1032 */ 1033 if (xfer->endpointno & UE_DIR_IN) { 1034 temp.func = &at91dci_data_rx; 1035 need_sync = 0; 1036 } else { 1037 temp.func = &at91dci_data_tx; 1038 need_sync = 1; 1039 } 1040 1041 at91dci_setup_standard_chain_sub(&temp); 1042 if (need_sync) { 1043 /* we need a SYNC point after TX */ 1044 temp.func = &at91dci_data_tx_sync; 1045 at91dci_setup_standard_chain_sub(&temp); 1046 } 1047 } 1048 } 1049 1050 /* must have at least one frame! */ 1051 td = temp.td; 1052 xfer->td_transfer_last = td; 1053 1054 /* setup the correct fifo bank */ 1055 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1056 td = xfer->td_transfer_first; 1057 td->fifo_bank = 1; 1058 } 1059} 1060 1061static void 1062at91dci_timeout(void *arg) 1063{ 1064 struct usb_xfer *xfer = arg; 1065 1066 DPRINTF("xfer=%p\n", xfer); 1067 1068 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1069 1070 /* transfer is transferred */ 1071 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1072} 1073 1074static void 1075at91dci_start_standard_chain(struct usb_xfer *xfer) 1076{ 1077 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1078 1079 DPRINTFN(9, "\n"); 1080 1081 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1082 1083 /* poll one time */ 1084 at91dci_xfer_do_fifo(xfer); 1085 1086 if (at91dci_xfer_do_complete(xfer) == 0) { 1087 1088 uint8_t ep_no = xfer->endpointno & UE_ADDR; 1089 1090 /* 1091 * Only enable the endpoint interrupt when we are actually 1092 * waiting for data, hence we are dealing with level 1093 * triggered interrupts ! 1094 */ 1095 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1096 1097 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1098 1099 /* put transfer on interrupt queue */ 1100 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1101 1102 /* start timeout, if any */ 1103 if (xfer->timeout != 0) { 1104 usbd_transfer_timeout_ms(xfer, 1105 &at91dci_timeout, xfer->timeout); 1106 } 1107 } 1108 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1109} 1110 1111static void 1112at91dci_root_intr(struct at91dci_softc *sc) 1113{ 1114 DPRINTFN(9, "\n"); 1115 1116 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1117 1118 /* set port bit */ 1119 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1120 1121 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1122 sizeof(sc->sc_hub_idata)); 1123} 1124 1125static usb_error_t 1126at91dci_standard_done_sub(struct usb_xfer *xfer) 1127{ 1128 struct at91dci_td *td; 1129 uint32_t len; 1130 uint8_t error; 1131 1132 DPRINTFN(9, "\n"); 1133 1134 td = xfer->td_transfer_cache; 1135 1136 do { 1137 len = td->remainder; 1138 1139 if (xfer->aframes != xfer->nframes) { 1140 /* 1141 * Verify the length and subtract 1142 * the remainder from "frlengths[]": 1143 */ 1144 if (len > xfer->frlengths[xfer->aframes]) { 1145 td->error = 1; 1146 } else { 1147 xfer->frlengths[xfer->aframes] -= len; 1148 } 1149 } 1150 /* Check for transfer error */ 1151 if (td->error) { 1152 /* the transfer is finished */ 1153 error = 1; 1154 td = NULL; 1155 break; 1156 } 1157 /* Check for short transfer */ 1158 if (len > 0) { 1159 if (xfer->flags_int.short_frames_ok || 1160 xfer->flags_int.isochronous_xfr) { 1161 /* follow alt next */ 1162 if (td->alt_next) { 1163 td = td->obj_next; 1164 } else { 1165 td = NULL; 1166 } 1167 } else { 1168 /* the transfer is finished */ 1169 td = NULL; 1170 } 1171 error = 0; 1172 break; 1173 } 1174 td = td->obj_next; 1175 1176 /* this USB frame is complete */ 1177 error = 0; 1178 break; 1179 1180 } while (0); 1181 1182 /* update transfer cache */ 1183 1184 xfer->td_transfer_cache = td; 1185 1186 return (error ? 1187 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1188} 1189 1190static void 1191at91dci_standard_done(struct usb_xfer *xfer) 1192{ 1193 usb_error_t err = 0; 1194 1195 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1196 xfer, xfer->endpoint); 1197 1198 /* reset scanner */ 1199 1200 xfer->td_transfer_cache = xfer->td_transfer_first; 1201 1202 if (xfer->flags_int.control_xfr) { 1203 1204 if (xfer->flags_int.control_hdr) { 1205 1206 err = at91dci_standard_done_sub(xfer); 1207 } 1208 xfer->aframes = 1; 1209 1210 if (xfer->td_transfer_cache == NULL) { 1211 goto done; 1212 } 1213 } 1214 while (xfer->aframes != xfer->nframes) { 1215 1216 err = at91dci_standard_done_sub(xfer); 1217 xfer->aframes++; 1218 1219 if (xfer->td_transfer_cache == NULL) { 1220 goto done; 1221 } 1222 } 1223 1224 if (xfer->flags_int.control_xfr && 1225 !xfer->flags_int.control_act) { 1226 1227 err = at91dci_standard_done_sub(xfer); 1228 } 1229done: 1230 at91dci_device_done(xfer, err); 1231} 1232 1233/*------------------------------------------------------------------------* 1234 * at91dci_device_done 1235 * 1236 * NOTE: this function can be called more than one time on the 1237 * same USB transfer! 1238 *------------------------------------------------------------------------*/ 1239static void 1240at91dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1241{ 1242 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1243 uint8_t ep_no; 1244 1245 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1246 1247 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1248 xfer, xfer->endpoint, error); 1249 1250 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1251 1252 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1253 ep_no = (xfer->endpointno & UE_ADDR); 1254 1255 /* disable endpoint interrupt */ 1256 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1257 1258 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1259 } 1260 1261 /* dequeue transfer and start next transfer */ 1262 usbd_transfer_done(xfer, error); 1263 1264 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1265} 1266 1267static void 1268at91dci_xfer_stall(struct usb_xfer *xfer) 1269{ 1270 at91dci_device_done(xfer, USB_ERR_STALLED); 1271} 1272 1273static void 1274at91dci_set_stall(struct usb_device *udev, 1275 struct usb_endpoint *ep, uint8_t *did_stall) 1276{ 1277 struct at91dci_softc *sc; 1278 uint32_t csr_val; 1279 uint8_t csr_reg; 1280 1281 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1282 1283 DPRINTFN(5, "endpoint=%p\n", ep); 1284 1285 /* set FORCESTALL */ 1286 sc = AT9100_DCI_BUS2SC(udev->bus); 1287 1288 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1289 csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR); 1290 csr_reg = AT91_UDP_CSR(csr_reg); 1291 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1292 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1293 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1294 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1295} 1296 1297static void 1298at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1299 uint8_t ep_type, uint8_t ep_dir) 1300{ 1301 const struct usb_hw_ep_profile *pf; 1302 uint32_t csr_val; 1303 uint32_t temp; 1304 uint8_t csr_reg; 1305 uint8_t to; 1306 1307 if (ep_type == UE_CONTROL) { 1308 /* clearing stall is not needed */ 1309 return; 1310 } 1311 1312 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1313 1314 /* compute CSR register offset */ 1315 csr_reg = AT91_UDP_CSR(ep_no); 1316 1317 /* compute default CSR value */ 1318 csr_val = 0; 1319 AT91_CSR_ACK(csr_val, 0); 1320 1321 /* disable endpoint */ 1322 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1323 1324 /* get endpoint profile */ 1325 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1326 1327 /* reset FIFO */ 1328 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1329 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1330 1331 /* 1332 * NOTE: One would assume that a FIFO reset would release the 1333 * FIFO banks as well, but it doesn't! We have to do this 1334 * manually! 1335 */ 1336 1337 /* release FIFO banks, if any */ 1338 for (to = 0; to != 2; to++) { 1339 1340 /* get csr value */ 1341 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1342 1343 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1344 AT91_UDP_CSR_RX_DATA_BK1)) { 1345 /* clear status bits */ 1346 if (pf->support_multi_buffer) { 1347 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1348 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1349 temp = AT91_UDP_CSR_RX_DATA_BK1; 1350 } else { 1351 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1352 temp = AT91_UDP_CSR_RX_DATA_BK0; 1353 } 1354 } else { 1355 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1356 AT91_UDP_CSR_RX_DATA_BK1); 1357 } 1358 } else { 1359 temp = 0; 1360 } 1361 1362 /* clear FORCESTALL */ 1363 temp |= AT91_UDP_CSR_STALLSENT; 1364 1365 AT91_CSR_ACK(csr_val, temp); 1366 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1367 } 1368 1369 /* compute default CSR value */ 1370 csr_val = 0; 1371 AT91_CSR_ACK(csr_val, 0); 1372 1373 /* enable endpoint */ 1374 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1375 csr_val |= AT91_UDP_CSR_EPEDS; 1376 1377 if (ep_type == UE_CONTROL) { 1378 csr_val |= AT91_UDP_CSR_ET_CTRL; 1379 } else { 1380 if (ep_type == UE_BULK) { 1381 csr_val |= AT91_UDP_CSR_ET_BULK; 1382 } else if (ep_type == UE_INTERRUPT) { 1383 csr_val |= AT91_UDP_CSR_ET_INT; 1384 } else { 1385 csr_val |= AT91_UDP_CSR_ET_ISO; 1386 } 1387 if (ep_dir & UE_DIR_IN) { 1388 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1389 } 1390 } 1391 1392 /* enable endpoint */ 1393 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1394 1395 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1396} 1397 1398static void 1399at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1400{ 1401 struct at91dci_softc *sc; 1402 struct usb_endpoint_descriptor *ed; 1403 1404 DPRINTFN(5, "endpoint=%p\n", ep); 1405 1406 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1407 1408 /* check mode */ 1409 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1410 /* not supported */ 1411 return; 1412 } 1413 /* get softc */ 1414 sc = AT9100_DCI_BUS2SC(udev->bus); 1415 1416 /* get endpoint descriptor */ 1417 ed = ep->edesc; 1418 1419 /* reset endpoint */ 1420 at91dci_clear_stall_sub(sc, 1421 (ed->bEndpointAddress & UE_ADDR), 1422 (ed->bmAttributes & UE_XFERTYPE), 1423 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1424} 1425 1426usb_error_t 1427at91dci_init(struct at91dci_softc *sc) 1428{ 1429 uint32_t csr_val; 1430 uint8_t n; 1431 1432 DPRINTF("start\n"); 1433 1434 /* set up the bus structure */ 1435 sc->sc_bus.usbrev = USB_REV_1_1; 1436 sc->sc_bus.methods = &at91dci_bus_methods; 1437 1438 USB_BUS_LOCK(&sc->sc_bus); 1439 1440 /* turn on clocks */ 1441 1442 if (sc->sc_clocks_on) { 1443 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1444 } 1445 /* wait a little for things to stabilise */ 1446 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1447 1448 /* disable and clear all interrupts */ 1449 1450 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1451 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1452 1453 /* compute default CSR value */ 1454 1455 csr_val = 0; 1456 AT91_CSR_ACK(csr_val, 0); 1457 1458 /* disable all endpoints */ 1459 1460 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1461 1462 /* disable endpoint */ 1463 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1464 } 1465 1466 /* enable the control endpoint */ 1467 1468 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1469 AT91_UDP_CSR_EPEDS); 1470 1471 /* write to FIFO control register */ 1472 1473 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1474 1475 /* enable the interrupts we want */ 1476 1477 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1478 1479 /* turn off clocks */ 1480 1481 at91dci_clocks_off(sc); 1482 1483 USB_BUS_UNLOCK(&sc->sc_bus); 1484 1485 /* catch any lost interrupts */ 1486 1487 at91dci_do_poll(&sc->sc_bus); 1488 1489 return (0); /* success */ 1490} 1491 1492void 1493at91dci_uninit(struct at91dci_softc *sc) 1494{ 1495 USB_BUS_LOCK(&sc->sc_bus); 1496 1497 /* disable and clear all interrupts */ 1498 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1499 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1500 1501 sc->sc_flags.port_powered = 0; 1502 sc->sc_flags.status_vbus = 0; 1503 sc->sc_flags.status_bus_reset = 0; 1504 sc->sc_flags.status_suspend = 0; 1505 sc->sc_flags.change_suspend = 0; 1506 sc->sc_flags.change_connect = 1; 1507 1508 at91dci_pull_down(sc); 1509 at91dci_clocks_off(sc); 1510 USB_BUS_UNLOCK(&sc->sc_bus); 1511} 1512 1513static void 1514at91dci_suspend(struct at91dci_softc *sc) 1515{ 1516 /* TODO */ 1517} 1518 1519static void 1520at91dci_resume(struct at91dci_softc *sc) 1521{ 1522 /* TODO */ 1523} 1524 1525static void 1526at91dci_do_poll(struct usb_bus *bus) 1527{ 1528 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1529 1530 USB_BUS_LOCK(&sc->sc_bus); 1531 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1532 at91dci_interrupt_poll_locked(sc); 1533 at91dci_interrupt_complete_locked(sc); 1534 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1535 USB_BUS_UNLOCK(&sc->sc_bus); 1536} 1537 1538/*------------------------------------------------------------------------* 1539 * at91dci bulk support 1540 *------------------------------------------------------------------------*/ 1541static void 1542at91dci_device_bulk_open(struct usb_xfer *xfer) 1543{ 1544 return; 1545} 1546 1547static void 1548at91dci_device_bulk_close(struct usb_xfer *xfer) 1549{ 1550 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1551} 1552 1553static void 1554at91dci_device_bulk_enter(struct usb_xfer *xfer) 1555{ 1556 return; 1557} 1558 1559static void 1560at91dci_device_bulk_start(struct usb_xfer *xfer) 1561{ 1562 /* setup TDs */ 1563 at91dci_setup_standard_chain(xfer); 1564 at91dci_start_standard_chain(xfer); 1565} 1566 1567static const struct usb_pipe_methods at91dci_device_bulk_methods = 1568{ 1569 .open = at91dci_device_bulk_open, 1570 .close = at91dci_device_bulk_close, 1571 .enter = at91dci_device_bulk_enter, 1572 .start = at91dci_device_bulk_start, 1573}; 1574 1575/*------------------------------------------------------------------------* 1576 * at91dci control support 1577 *------------------------------------------------------------------------*/ 1578static void 1579at91dci_device_ctrl_open(struct usb_xfer *xfer) 1580{ 1581 return; 1582} 1583 1584static void 1585at91dci_device_ctrl_close(struct usb_xfer *xfer) 1586{ 1587 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1588} 1589 1590static void 1591at91dci_device_ctrl_enter(struct usb_xfer *xfer) 1592{ 1593 return; 1594} 1595 1596static void 1597at91dci_device_ctrl_start(struct usb_xfer *xfer) 1598{ 1599 /* setup TDs */ 1600 at91dci_setup_standard_chain(xfer); 1601 at91dci_start_standard_chain(xfer); 1602} 1603 1604static const struct usb_pipe_methods at91dci_device_ctrl_methods = 1605{ 1606 .open = at91dci_device_ctrl_open, 1607 .close = at91dci_device_ctrl_close, 1608 .enter = at91dci_device_ctrl_enter, 1609 .start = at91dci_device_ctrl_start, 1610}; 1611 1612/*------------------------------------------------------------------------* 1613 * at91dci interrupt support 1614 *------------------------------------------------------------------------*/ 1615static void 1616at91dci_device_intr_open(struct usb_xfer *xfer) 1617{ 1618 return; 1619} 1620 1621static void 1622at91dci_device_intr_close(struct usb_xfer *xfer) 1623{ 1624 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1625} 1626 1627static void 1628at91dci_device_intr_enter(struct usb_xfer *xfer) 1629{ 1630 return; 1631} 1632 1633static void 1634at91dci_device_intr_start(struct usb_xfer *xfer) 1635{ 1636 /* setup TDs */ 1637 at91dci_setup_standard_chain(xfer); 1638 at91dci_start_standard_chain(xfer); 1639} 1640 1641static const struct usb_pipe_methods at91dci_device_intr_methods = 1642{ 1643 .open = at91dci_device_intr_open, 1644 .close = at91dci_device_intr_close, 1645 .enter = at91dci_device_intr_enter, 1646 .start = at91dci_device_intr_start, 1647}; 1648 1649/*------------------------------------------------------------------------* 1650 * at91dci full speed isochronous support 1651 *------------------------------------------------------------------------*/ 1652static void 1653at91dci_device_isoc_fs_open(struct usb_xfer *xfer) 1654{ 1655 return; 1656} 1657 1658static void 1659at91dci_device_isoc_fs_close(struct usb_xfer *xfer) 1660{ 1661 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1662} 1663 1664static void 1665at91dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1666{ 1667 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1668 uint32_t temp; 1669 uint32_t nframes; 1670 1671 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1672 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1673 1674 /* get the current frame index */ 1675 1676 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1677 1678 /* 1679 * check if the frame index is within the window where the frames 1680 * will be inserted 1681 */ 1682 temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK; 1683 1684 if ((xfer->endpoint->is_synced == 0) || 1685 (temp < xfer->nframes)) { 1686 /* 1687 * If there is data underflow or the endpoint queue is 1688 * empty we schedule the transfer a few frames ahead 1689 * of the current frame position. Else two isochronous 1690 * transfers might overlap. 1691 */ 1692 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1693 xfer->endpoint->is_synced = 1; 1694 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1695 } 1696 /* 1697 * compute how many milliseconds the insertion is ahead of the 1698 * current frame position: 1699 */ 1700 temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1701 1702 /* 1703 * pre-compute when the isochronous transfer will be finished: 1704 */ 1705 xfer->isoc_time_complete = 1706 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1707 xfer->nframes; 1708 1709 /* compute frame number for next insertion */ 1710 xfer->endpoint->isoc_next += xfer->nframes; 1711 1712 /* setup TDs */ 1713 at91dci_setup_standard_chain(xfer); 1714} 1715 1716static void 1717at91dci_device_isoc_fs_start(struct usb_xfer *xfer) 1718{ 1719 /* start TD chain */ 1720 at91dci_start_standard_chain(xfer); 1721} 1722 1723static const struct usb_pipe_methods at91dci_device_isoc_fs_methods = 1724{ 1725 .open = at91dci_device_isoc_fs_open, 1726 .close = at91dci_device_isoc_fs_close, 1727 .enter = at91dci_device_isoc_fs_enter, 1728 .start = at91dci_device_isoc_fs_start, 1729}; 1730 1731/*------------------------------------------------------------------------* 1732 * at91dci root control support 1733 *------------------------------------------------------------------------* 1734 * Simulate a hardware HUB by handling all the necessary requests. 1735 *------------------------------------------------------------------------*/ 1736 1737static const struct usb_device_descriptor at91dci_devd = { 1738 .bLength = sizeof(struct usb_device_descriptor), 1739 .bDescriptorType = UDESC_DEVICE, 1740 .bcdUSB = {0x00, 0x02}, 1741 .bDeviceClass = UDCLASS_HUB, 1742 .bDeviceSubClass = UDSUBCLASS_HUB, 1743 .bDeviceProtocol = UDPROTO_FSHUB, 1744 .bMaxPacketSize = 64, 1745 .bcdDevice = {0x00, 0x01}, 1746 .iManufacturer = 1, 1747 .iProduct = 2, 1748 .bNumConfigurations = 1, 1749}; 1750 1751static const struct at91dci_config_desc at91dci_confd = { 1752 .confd = { 1753 .bLength = sizeof(struct usb_config_descriptor), 1754 .bDescriptorType = UDESC_CONFIG, 1755 .wTotalLength[0] = sizeof(at91dci_confd), 1756 .bNumInterface = 1, 1757 .bConfigurationValue = 1, 1758 .iConfiguration = 0, 1759 .bmAttributes = UC_SELF_POWERED, 1760 .bMaxPower = 0, 1761 }, 1762 .ifcd = { 1763 .bLength = sizeof(struct usb_interface_descriptor), 1764 .bDescriptorType = UDESC_INTERFACE, 1765 .bNumEndpoints = 1, 1766 .bInterfaceClass = UICLASS_HUB, 1767 .bInterfaceSubClass = UISUBCLASS_HUB, 1768 .bInterfaceProtocol = 0, 1769 }, 1770 .endpd = { 1771 .bLength = sizeof(struct usb_endpoint_descriptor), 1772 .bDescriptorType = UDESC_ENDPOINT, 1773 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1774 .bmAttributes = UE_INTERRUPT, 1775 .wMaxPacketSize[0] = 8, 1776 .bInterval = 255, 1777 }, 1778}; 1779 1780#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1781 1782static const struct usb_hub_descriptor_min at91dci_hubd = { 1783 .bDescLength = sizeof(at91dci_hubd), 1784 .bDescriptorType = UDESC_HUB, 1785 .bNbrPorts = 1, 1786 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1787 .bPwrOn2PwrGood = 50, 1788 .bHubContrCurrent = 0, 1789 .DeviceRemovable = {0}, /* port is removable */ 1790}; 1791 1792#define STRING_VENDOR \ 1793 "A\0T\0M\0E\0L" 1794 1795#define STRING_PRODUCT \ 1796 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1797 1798USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1799USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1800 1801static usb_error_t 1802at91dci_roothub_exec(struct usb_device *udev, 1803 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1804{ 1805 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 1806 const void *ptr; 1807 uint16_t len; 1808 uint16_t value; 1809 uint16_t index; 1810 usb_error_t err; 1811 1812 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1813 1814 /* buffer reset */ 1815 ptr = (const void *)&sc->sc_hub_temp; 1816 len = 0; 1817 err = 0; 1818 1819 value = UGETW(req->wValue); 1820 index = UGETW(req->wIndex); 1821 1822 /* demultiplex the control request */ 1823 1824 switch (req->bmRequestType) { 1825 case UT_READ_DEVICE: 1826 switch (req->bRequest) { 1827 case UR_GET_DESCRIPTOR: 1828 goto tr_handle_get_descriptor; 1829 case UR_GET_CONFIG: 1830 goto tr_handle_get_config; 1831 case UR_GET_STATUS: 1832 goto tr_handle_get_status; 1833 default: 1834 goto tr_stalled; 1835 } 1836 break; 1837 1838 case UT_WRITE_DEVICE: 1839 switch (req->bRequest) { 1840 case UR_SET_ADDRESS: 1841 goto tr_handle_set_address; 1842 case UR_SET_CONFIG: 1843 goto tr_handle_set_config; 1844 case UR_CLEAR_FEATURE: 1845 goto tr_valid; /* nop */ 1846 case UR_SET_DESCRIPTOR: 1847 goto tr_valid; /* nop */ 1848 case UR_SET_FEATURE: 1849 default: 1850 goto tr_stalled; 1851 } 1852 break; 1853 1854 case UT_WRITE_ENDPOINT: 1855 switch (req->bRequest) { 1856 case UR_CLEAR_FEATURE: 1857 switch (UGETW(req->wValue)) { 1858 case UF_ENDPOINT_HALT: 1859 goto tr_handle_clear_halt; 1860 case UF_DEVICE_REMOTE_WAKEUP: 1861 goto tr_handle_clear_wakeup; 1862 default: 1863 goto tr_stalled; 1864 } 1865 break; 1866 case UR_SET_FEATURE: 1867 switch (UGETW(req->wValue)) { 1868 case UF_ENDPOINT_HALT: 1869 goto tr_handle_set_halt; 1870 case UF_DEVICE_REMOTE_WAKEUP: 1871 goto tr_handle_set_wakeup; 1872 default: 1873 goto tr_stalled; 1874 } 1875 break; 1876 case UR_SYNCH_FRAME: 1877 goto tr_valid; /* nop */ 1878 default: 1879 goto tr_stalled; 1880 } 1881 break; 1882 1883 case UT_READ_ENDPOINT: 1884 switch (req->bRequest) { 1885 case UR_GET_STATUS: 1886 goto tr_handle_get_ep_status; 1887 default: 1888 goto tr_stalled; 1889 } 1890 break; 1891 1892 case UT_WRITE_INTERFACE: 1893 switch (req->bRequest) { 1894 case UR_SET_INTERFACE: 1895 goto tr_handle_set_interface; 1896 case UR_CLEAR_FEATURE: 1897 goto tr_valid; /* nop */ 1898 case UR_SET_FEATURE: 1899 default: 1900 goto tr_stalled; 1901 } 1902 break; 1903 1904 case UT_READ_INTERFACE: 1905 switch (req->bRequest) { 1906 case UR_GET_INTERFACE: 1907 goto tr_handle_get_interface; 1908 case UR_GET_STATUS: 1909 goto tr_handle_get_iface_status; 1910 default: 1911 goto tr_stalled; 1912 } 1913 break; 1914 1915 case UT_WRITE_CLASS_INTERFACE: 1916 case UT_WRITE_VENDOR_INTERFACE: 1917 /* XXX forward */ 1918 break; 1919 1920 case UT_READ_CLASS_INTERFACE: 1921 case UT_READ_VENDOR_INTERFACE: 1922 /* XXX forward */ 1923 break; 1924 1925 case UT_WRITE_CLASS_DEVICE: 1926 switch (req->bRequest) { 1927 case UR_CLEAR_FEATURE: 1928 goto tr_valid; 1929 case UR_SET_DESCRIPTOR: 1930 case UR_SET_FEATURE: 1931 break; 1932 default: 1933 goto tr_stalled; 1934 } 1935 break; 1936 1937 case UT_WRITE_CLASS_OTHER: 1938 switch (req->bRequest) { 1939 case UR_CLEAR_FEATURE: 1940 goto tr_handle_clear_port_feature; 1941 case UR_SET_FEATURE: 1942 goto tr_handle_set_port_feature; 1943 case UR_CLEAR_TT_BUFFER: 1944 case UR_RESET_TT: 1945 case UR_STOP_TT: 1946 goto tr_valid; 1947 1948 default: 1949 goto tr_stalled; 1950 } 1951 break; 1952 1953 case UT_READ_CLASS_OTHER: 1954 switch (req->bRequest) { 1955 case UR_GET_TT_STATE: 1956 goto tr_handle_get_tt_state; 1957 case UR_GET_STATUS: 1958 goto tr_handle_get_port_status; 1959 default: 1960 goto tr_stalled; 1961 } 1962 break; 1963 1964 case UT_READ_CLASS_DEVICE: 1965 switch (req->bRequest) { 1966 case UR_GET_DESCRIPTOR: 1967 goto tr_handle_get_class_descriptor; 1968 case UR_GET_STATUS: 1969 goto tr_handle_get_class_status; 1970 1971 default: 1972 goto tr_stalled; 1973 } 1974 break; 1975 default: 1976 goto tr_stalled; 1977 } 1978 goto tr_valid; 1979 1980tr_handle_get_descriptor: 1981 switch (value >> 8) { 1982 case UDESC_DEVICE: 1983 if (value & 0xff) { 1984 goto tr_stalled; 1985 } 1986 len = sizeof(at91dci_devd); 1987 ptr = (const void *)&at91dci_devd; 1988 goto tr_valid; 1989 case UDESC_CONFIG: 1990 if (value & 0xff) { 1991 goto tr_stalled; 1992 } 1993 len = sizeof(at91dci_confd); 1994 ptr = (const void *)&at91dci_confd; 1995 goto tr_valid; 1996 case UDESC_STRING: 1997 switch (value & 0xff) { 1998 case 0: /* Language table */ 1999 len = sizeof(usb_string_lang_en); 2000 ptr = (const void *)&usb_string_lang_en; 2001 goto tr_valid; 2002 2003 case 1: /* Vendor */ 2004 len = sizeof(at91dci_vendor); 2005 ptr = (const void *)&at91dci_vendor; 2006 goto tr_valid; 2007 2008 case 2: /* Product */ 2009 len = sizeof(at91dci_product); 2010 ptr = (const void *)&at91dci_product; 2011 goto tr_valid; 2012 default: 2013 break; 2014 } 2015 break; 2016 default: 2017 goto tr_stalled; 2018 } 2019 goto tr_stalled; 2020 2021tr_handle_get_config: 2022 len = 1; 2023 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2024 goto tr_valid; 2025 2026tr_handle_get_status: 2027 len = 2; 2028 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2029 goto tr_valid; 2030 2031tr_handle_set_address: 2032 if (value & 0xFF00) { 2033 goto tr_stalled; 2034 } 2035 sc->sc_rt_addr = value; 2036 goto tr_valid; 2037 2038tr_handle_set_config: 2039 if (value >= 2) { 2040 goto tr_stalled; 2041 } 2042 sc->sc_conf = value; 2043 goto tr_valid; 2044 2045tr_handle_get_interface: 2046 len = 1; 2047 sc->sc_hub_temp.wValue[0] = 0; 2048 goto tr_valid; 2049 2050tr_handle_get_tt_state: 2051tr_handle_get_class_status: 2052tr_handle_get_iface_status: 2053tr_handle_get_ep_status: 2054 len = 2; 2055 USETW(sc->sc_hub_temp.wValue, 0); 2056 goto tr_valid; 2057 2058tr_handle_set_halt: 2059tr_handle_set_interface: 2060tr_handle_set_wakeup: 2061tr_handle_clear_wakeup: 2062tr_handle_clear_halt: 2063 goto tr_valid; 2064 2065tr_handle_clear_port_feature: 2066 if (index != 1) { 2067 goto tr_stalled; 2068 } 2069 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2070 2071 switch (value) { 2072 case UHF_PORT_SUSPEND: 2073 at91dci_wakeup_peer(sc); 2074 break; 2075 2076 case UHF_PORT_ENABLE: 2077 sc->sc_flags.port_enabled = 0; 2078 break; 2079 2080 case UHF_PORT_TEST: 2081 case UHF_PORT_INDICATOR: 2082 case UHF_C_PORT_ENABLE: 2083 case UHF_C_PORT_OVER_CURRENT: 2084 case UHF_C_PORT_RESET: 2085 /* nops */ 2086 break; 2087 case UHF_PORT_POWER: 2088 sc->sc_flags.port_powered = 0; 2089 at91dci_pull_down(sc); 2090 at91dci_clocks_off(sc); 2091 break; 2092 case UHF_C_PORT_CONNECTION: 2093 sc->sc_flags.change_connect = 0; 2094 break; 2095 case UHF_C_PORT_SUSPEND: 2096 sc->sc_flags.change_suspend = 0; 2097 break; 2098 default: 2099 err = USB_ERR_IOERROR; 2100 goto done; 2101 } 2102 goto tr_valid; 2103 2104tr_handle_set_port_feature: 2105 if (index != 1) { 2106 goto tr_stalled; 2107 } 2108 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2109 2110 switch (value) { 2111 case UHF_PORT_ENABLE: 2112 sc->sc_flags.port_enabled = 1; 2113 break; 2114 case UHF_PORT_SUSPEND: 2115 case UHF_PORT_RESET: 2116 case UHF_PORT_TEST: 2117 case UHF_PORT_INDICATOR: 2118 /* nops */ 2119 break; 2120 case UHF_PORT_POWER: 2121 sc->sc_flags.port_powered = 1; 2122 break; 2123 default: 2124 err = USB_ERR_IOERROR; 2125 goto done; 2126 } 2127 goto tr_valid; 2128 2129tr_handle_get_port_status: 2130 2131 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2132 2133 if (index != 1) { 2134 goto tr_stalled; 2135 } 2136 if (sc->sc_flags.status_vbus) { 2137 at91dci_clocks_on(sc); 2138 at91dci_pull_up(sc); 2139 } else { 2140 at91dci_pull_down(sc); 2141 at91dci_clocks_off(sc); 2142 } 2143 2144 /* Select FULL-speed and Device Side Mode */ 2145 2146 value = UPS_PORT_MODE_DEVICE; 2147 2148 if (sc->sc_flags.port_powered) { 2149 value |= UPS_PORT_POWER; 2150 } 2151 if (sc->sc_flags.port_enabled) { 2152 value |= UPS_PORT_ENABLED; 2153 } 2154 if (sc->sc_flags.status_vbus && 2155 sc->sc_flags.status_bus_reset) { 2156 value |= UPS_CURRENT_CONNECT_STATUS; 2157 } 2158 if (sc->sc_flags.status_suspend) { 2159 value |= UPS_SUSPEND; 2160 } 2161 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2162 2163 value = 0; 2164 2165 if (sc->sc_flags.change_connect) { 2166 value |= UPS_C_CONNECT_STATUS; 2167 2168 if (sc->sc_flags.status_vbus && 2169 sc->sc_flags.status_bus_reset) { 2170 /* reset endpoint flags */ 2171 memset(sc->sc_ep_flags, 0, sizeof(sc->sc_ep_flags)); 2172 } 2173 } 2174 if (sc->sc_flags.change_suspend) { 2175 value |= UPS_C_SUSPEND; 2176 } 2177 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2178 len = sizeof(sc->sc_hub_temp.ps); 2179 goto tr_valid; 2180 2181tr_handle_get_class_descriptor: 2182 if (value & 0xFF) { 2183 goto tr_stalled; 2184 } 2185 ptr = (const void *)&at91dci_hubd; 2186 len = sizeof(at91dci_hubd); 2187 goto tr_valid; 2188 2189tr_stalled: 2190 err = USB_ERR_STALLED; 2191tr_valid: 2192done: 2193 *plength = len; 2194 *pptr = ptr; 2195 return (err); 2196} 2197 2198static void 2199at91dci_xfer_setup(struct usb_setup_params *parm) 2200{ 2201 const struct usb_hw_ep_profile *pf; 2202 struct at91dci_softc *sc; 2203 struct usb_xfer *xfer; 2204 void *last_obj; 2205 uint32_t ntd; 2206 uint32_t n; 2207 uint8_t ep_no; 2208 2209 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2210 xfer = parm->curr_xfer; 2211 2212 /* 2213 * NOTE: This driver does not use any of the parameters that 2214 * are computed from the following values. Just set some 2215 * reasonable dummies: 2216 */ 2217 parm->hc_max_packet_size = 0x500; 2218 parm->hc_max_packet_count = 1; 2219 parm->hc_max_frame_size = 0x500; 2220 2221 usbd_transfer_setup_sub(parm); 2222 2223 /* 2224 * compute maximum number of TDs 2225 */ 2226 if (parm->methods == &at91dci_device_ctrl_methods) { 2227 2228 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2229 + 1 /* SYNC 2 */ ; 2230 2231 } else if (parm->methods == &at91dci_device_bulk_methods) { 2232 2233 ntd = xfer->nframes + 1 /* SYNC */ ; 2234 2235 } else if (parm->methods == &at91dci_device_intr_methods) { 2236 2237 ntd = xfer->nframes + 1 /* SYNC */ ; 2238 2239 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2240 2241 ntd = xfer->nframes + 1 /* SYNC */ ; 2242 2243 } else { 2244 2245 ntd = 0; 2246 } 2247 2248 /* 2249 * check if "usbd_transfer_setup_sub" set an error 2250 */ 2251 if (parm->err) { 2252 return; 2253 } 2254 /* 2255 * allocate transfer descriptors 2256 */ 2257 last_obj = NULL; 2258 2259 /* 2260 * get profile stuff 2261 */ 2262 if (ntd) { 2263 2264 ep_no = xfer->endpointno & UE_ADDR; 2265 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2266 2267 if (pf == NULL) { 2268 /* should not happen */ 2269 parm->err = USB_ERR_INVAL; 2270 return; 2271 } 2272 } else { 2273 ep_no = 0; 2274 pf = NULL; 2275 } 2276 2277 /* align data */ 2278 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2279 2280 for (n = 0; n != ntd; n++) { 2281 2282 struct at91dci_td *td; 2283 2284 if (parm->buf) { 2285 2286 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2287 2288 /* init TD */ 2289 td->max_packet_size = xfer->max_packet_size; 2290 td->status_reg = AT91_UDP_CSR(ep_no); 2291 td->fifo_reg = AT91_UDP_FDR(ep_no); 2292 if (pf->support_multi_buffer) { 2293 td->support_multi_buffer = 1; 2294 } 2295 td->obj_next = last_obj; 2296 2297 last_obj = td; 2298 } 2299 parm->size[0] += sizeof(*td); 2300 } 2301 2302 xfer->td_start[0] = last_obj; 2303} 2304 2305static void 2306at91dci_xfer_unsetup(struct usb_xfer *xfer) 2307{ 2308 return; 2309} 2310 2311static void 2312at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2313 struct usb_endpoint *ep) 2314{ 2315 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2316 2317 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2318 ep, udev->address, 2319 edesc->bEndpointAddress, udev->flags.usb_mode, 2320 sc->sc_rt_addr); 2321 2322 if (udev->device_index != sc->sc_rt_addr) { 2323 2324 if (udev->speed != USB_SPEED_FULL) { 2325 /* not supported */ 2326 return; 2327 } 2328 switch (edesc->bmAttributes & UE_XFERTYPE) { 2329 case UE_CONTROL: 2330 ep->methods = &at91dci_device_ctrl_methods; 2331 break; 2332 case UE_INTERRUPT: 2333 ep->methods = &at91dci_device_intr_methods; 2334 break; 2335 case UE_ISOCHRONOUS: 2336 ep->methods = &at91dci_device_isoc_fs_methods; 2337 break; 2338 case UE_BULK: 2339 ep->methods = &at91dci_device_bulk_methods; 2340 break; 2341 default: 2342 /* do nothing */ 2343 break; 2344 } 2345 } 2346} 2347 2348static void 2349at91dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2350{ 2351 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 2352 2353 switch (state) { 2354 case USB_HW_POWER_SUSPEND: 2355 at91dci_suspend(sc); 2356 break; 2357 case USB_HW_POWER_SHUTDOWN: 2358 at91dci_uninit(sc); 2359 break; 2360 case USB_HW_POWER_RESUME: 2361 at91dci_resume(sc); 2362 break; 2363 default: 2364 break; 2365 } 2366} 2367 2368static const struct usb_bus_methods at91dci_bus_methods = 2369{ 2370 .endpoint_init = &at91dci_ep_init, 2371 .xfer_setup = &at91dci_xfer_setup, 2372 .xfer_unsetup = &at91dci_xfer_unsetup, 2373 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2374 .set_stall = &at91dci_set_stall, 2375 .xfer_stall = &at91dci_xfer_stall, 2376 .clear_stall = &at91dci_clear_stall, 2377 .roothub_exec = &at91dci_roothub_exec, 2378 .xfer_poll = &at91dci_do_poll, 2379 .set_hw_power_sleep = &at91dci_set_hw_power_sleep, 2380}; 2381