sibareg.h revision 183371
175584Sru/*- 275584Sru * Copyright (c) 2007 Bruce M. Simpson. 375584Sru * All rights reserved. 475584Sru * 575584Sru * Redistribution and use in source and binary forms, with or without 675584Sru * modification, are permitted provided that the following conditions 775584Sru * are met: 875584Sru * 1. Redistributions of source code must retain the above copyright 975584Sru * notice, this list of conditions and the following disclaimer. 1075584Sru * 2. Redistributions in binary form must reproduce the above copyright 1175584Sru * notice, this list of conditions and the following disclaimer in the 1275584Sru * documentation and/or other materials provided with the distribution. 1375584Sru * 1475584Sru * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1575584Sru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1675584Sru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1775584Sru * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1875584Sru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1975584Sru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2075584Sru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2175584Sru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2275584Sru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2375584Sru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2475584Sru * SUCH DAMAGE. 2575584Sru * 2675584Sru * $FreeBSD: head/sys/dev/siba/sibareg.h 183371 2008-09-26 03:57:23Z imp $ 2775584Sru */ 2875584Sru 2975584Sru/* 3075584Sru * TODO: sprom 3175584Sru * TODO: implement dma translation bits (if needed for system bus) 3275584Sru */ 3375584Sru 3475584Sru#ifndef _SIBA_SIBAREG_H_ 3575584Sru#define _SIBA_SIBAREG_H_ 3675584Sru 3775584Sru#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 3875584Sru#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 3975584Sru#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ 4075584Sru 4175584Sru/* offset of high ID register */ 4275584Sru#define SIBA_CORE_IDLO 0x00000ff8 4375584Sru#define SIBA_CORE_IDHI 0x00000ffc 4475584Sru 4575584Sru/* 4675584Sru * Offsets of ChipCommon core registers. 4775584Sru * XXX: move to siba_cc 4875584Sru */ 4975584Sru#define SIBA_CC_UART0 0x00000300 /* offset of UART0 */ 5075584Sru#define SIBA_CC_UART1 0x00000400 /* offset of UART1 */ 5175584Sru 5275584Sru#define SIBA_CC_CCID 0x0000 5375584Sru#define SIBA_CC_IDMASK 0x0000FFFF 5475584Sru#define SIBA_CC_REVMASK 0x000F0000 5575584Sru#define SIBA_CC_REVSHIFT 16 5675584Sru#define SIBA_CC_PACKMASK 0x00F00000 5775584Sru#define SIBA_CC_PACKSHIFT 20 5875584Sru#define SIBA_CC_NRCORESMASK 0x0F000000 5975584Sru#define SIBA_CC_NRCORESSHIFT 24 6075584Sru 6175584Sru#define SIBA_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ 6275584Sru#define SIBA_IDHIGH_CC 0x00008FF0 /* Core Code */ 6375584Sru#define SIBA_IDHIGH_CC_SHIFT 4 6475584Sru#define SIBA_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ 6575584Sru#define SIBA_IDHIGH_RCHI_SHIFT 8 6675584Sru#define SIBA_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ 6775584Sru#define SIBA_IDHIGH_VC_SHIFT 16 6875584Sru 6975584Sru#define SIBA_CCID_BCM4710 0x4710 7075584Sru#define SIBA_CCID_BCM4704 0x4704 7175584Sru#define SIBA_CCID_SENTRY5 0x5365 7275584Sru 7375584Sru#endif /* _SIBA_SIBAREG_H_ */ 7475584Sru