sibareg.h revision 183371
1/*- 2 * Copyright (c) 2007 Bruce M. Simpson. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/siba/sibareg.h 183371 2008-09-26 03:57:23Z imp $ 27 */ 28 29/* 30 * TODO: sprom 31 * TODO: implement dma translation bits (if needed for system bus) 32 */ 33 34#ifndef _SIBA_SIBAREG_H_ 35#define _SIBA_SIBAREG_H_ 36 37#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 38#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 39#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ 40 41/* offset of high ID register */ 42#define SIBA_CORE_IDLO 0x00000ff8 43#define SIBA_CORE_IDHI 0x00000ffc 44 45/* 46 * Offsets of ChipCommon core registers. 47 * XXX: move to siba_cc 48 */ 49#define SIBA_CC_UART0 0x00000300 /* offset of UART0 */ 50#define SIBA_CC_UART1 0x00000400 /* offset of UART1 */ 51 52#define SIBA_CC_CCID 0x0000 53#define SIBA_CC_IDMASK 0x0000FFFF 54#define SIBA_CC_REVMASK 0x000F0000 55#define SIBA_CC_REVSHIFT 16 56#define SIBA_CC_PACKMASK 0x00F00000 57#define SIBA_CC_PACKSHIFT 20 58#define SIBA_CC_NRCORESMASK 0x0F000000 59#define SIBA_CC_NRCORESSHIFT 24 60 61#define SIBA_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ 62#define SIBA_IDHIGH_CC 0x00008FF0 /* Core Code */ 63#define SIBA_IDHIGH_CC_SHIFT 4 64#define SIBA_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ 65#define SIBA_IDHIGH_RCHI_SHIFT 8 66#define SIBA_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ 67#define SIBA_IDHIGH_VC_SHIFT 16 68 69#define SIBA_CCID_BCM4710 0x4710 70#define SIBA_CCID_BCM4704 0x4704 71#define SIBA_CCID_SENTRY5 0x5365 72 73#endif /* _SIBA_SIBAREG_H_ */ 74