1/*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD: releng/11.0/sys/dev/sfxge/common/ef10_impl.h 301122 2016-06-01 14:03:07Z arybchik $ 31 */ 32 33#ifndef _SYS_EF10_IMPL_H 34#define _SYS_EF10_IMPL_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41#define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42#elif EFSYS_OPT_HUNTINGTON 43#define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44#elif EFSYS_OPT_MEDFORD 45#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46#endif 47 48/* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53#define EF10_NVRAM_CHUNK 0x80 54 55/* Alignment requirement for value written to RX WPTR: 56 * the WPTR must be aligned to an 8 descriptor boundary 57 */ 58#define EF10_RX_WPTR_ALIGN 8 59 60/* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64#define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66/* Invalid RSS context handle */ 67#define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70/* EV */ 71 72 __checkReturn efx_rc_t 73ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in uint32_t us, 88 __in efx_evq_t *eep); 89 90 void 91ef10_ev_qdestroy( 92 __in efx_evq_t *eep); 93 94 __checkReturn efx_rc_t 95ef10_ev_qprime( 96 __in efx_evq_t *eep, 97 __in unsigned int count); 98 99 void 100ef10_ev_qpost( 101 __in efx_evq_t *eep, 102 __in uint16_t data); 103 104 __checkReturn efx_rc_t 105ef10_ev_qmoderate( 106 __in efx_evq_t *eep, 107 __in unsigned int us); 108 109#if EFSYS_OPT_QSTATS 110 void 111ef10_ev_qstats_update( 112 __in efx_evq_t *eep, 113 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 114#endif /* EFSYS_OPT_QSTATS */ 115 116 void 117ef10_ev_rxlabel_init( 118 __in efx_evq_t *eep, 119 __in efx_rxq_t *erp, 120 __in unsigned int label); 121 122 void 123ef10_ev_rxlabel_fini( 124 __in efx_evq_t *eep, 125 __in unsigned int label); 126 127/* INTR */ 128 129 __checkReturn efx_rc_t 130ef10_intr_init( 131 __in efx_nic_t *enp, 132 __in efx_intr_type_t type, 133 __in efsys_mem_t *esmp); 134 135 void 136ef10_intr_enable( 137 __in efx_nic_t *enp); 138 139 void 140ef10_intr_disable( 141 __in efx_nic_t *enp); 142 143 void 144ef10_intr_disable_unlocked( 145 __in efx_nic_t *enp); 146 147 __checkReturn efx_rc_t 148ef10_intr_trigger( 149 __in efx_nic_t *enp, 150 __in unsigned int level); 151 152 void 153ef10_intr_status_line( 154 __in efx_nic_t *enp, 155 __out boolean_t *fatalp, 156 __out uint32_t *qmaskp); 157 158 void 159ef10_intr_status_message( 160 __in efx_nic_t *enp, 161 __in unsigned int message, 162 __out boolean_t *fatalp); 163 164 void 165ef10_intr_fatal( 166 __in efx_nic_t *enp); 167 void 168ef10_intr_fini( 169 __in efx_nic_t *enp); 170 171/* NIC */ 172 173extern __checkReturn efx_rc_t 174ef10_nic_probe( 175 __in efx_nic_t *enp); 176 177extern __checkReturn efx_rc_t 178ef10_nic_set_drv_limits( 179 __inout efx_nic_t *enp, 180 __in efx_drv_limits_t *edlp); 181 182extern __checkReturn efx_rc_t 183ef10_nic_get_vi_pool( 184 __in efx_nic_t *enp, 185 __out uint32_t *vi_countp); 186 187extern __checkReturn efx_rc_t 188ef10_nic_get_bar_region( 189 __in efx_nic_t *enp, 190 __in efx_nic_region_t region, 191 __out uint32_t *offsetp, 192 __out size_t *sizep); 193 194extern __checkReturn efx_rc_t 195ef10_nic_reset( 196 __in efx_nic_t *enp); 197 198extern __checkReturn efx_rc_t 199ef10_nic_init( 200 __in efx_nic_t *enp); 201 202#if EFSYS_OPT_DIAG 203 204extern __checkReturn efx_rc_t 205ef10_nic_register_test( 206 __in efx_nic_t *enp); 207 208#endif /* EFSYS_OPT_DIAG */ 209 210extern void 211ef10_nic_fini( 212 __in efx_nic_t *enp); 213 214extern void 215ef10_nic_unprobe( 216 __in efx_nic_t *enp); 217 218 219/* MAC */ 220 221extern __checkReturn efx_rc_t 222ef10_mac_poll( 223 __in efx_nic_t *enp, 224 __out efx_link_mode_t *link_modep); 225 226extern __checkReturn efx_rc_t 227ef10_mac_up( 228 __in efx_nic_t *enp, 229 __out boolean_t *mac_upp); 230 231extern __checkReturn efx_rc_t 232ef10_mac_addr_set( 233 __in efx_nic_t *enp); 234 235extern __checkReturn efx_rc_t 236ef10_mac_pdu_set( 237 __in efx_nic_t *enp); 238 239extern __checkReturn efx_rc_t 240ef10_mac_pdu_get( 241 __in efx_nic_t *enp, 242 __out size_t *pdu); 243 244extern __checkReturn efx_rc_t 245ef10_mac_reconfigure( 246 __in efx_nic_t *enp); 247 248extern __checkReturn efx_rc_t 249ef10_mac_multicast_list_set( 250 __in efx_nic_t *enp); 251 252extern __checkReturn efx_rc_t 253ef10_mac_filter_default_rxq_set( 254 __in efx_nic_t *enp, 255 __in efx_rxq_t *erp, 256 __in boolean_t using_rss); 257 258extern void 259ef10_mac_filter_default_rxq_clear( 260 __in efx_nic_t *enp); 261 262#if EFSYS_OPT_LOOPBACK 263 264extern __checkReturn efx_rc_t 265ef10_mac_loopback_set( 266 __in efx_nic_t *enp, 267 __in efx_link_mode_t link_mode, 268 __in efx_loopback_type_t loopback_type); 269 270#endif /* EFSYS_OPT_LOOPBACK */ 271 272#if EFSYS_OPT_MAC_STATS 273 274extern __checkReturn efx_rc_t 275ef10_mac_stats_update( 276 __in efx_nic_t *enp, 277 __in efsys_mem_t *esmp, 278 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 279 __inout_opt uint32_t *generationp); 280 281#endif /* EFSYS_OPT_MAC_STATS */ 282 283 284/* MCDI */ 285 286#if EFSYS_OPT_MCDI 287 288extern __checkReturn efx_rc_t 289ef10_mcdi_init( 290 __in efx_nic_t *enp, 291 __in const efx_mcdi_transport_t *mtp); 292 293extern void 294ef10_mcdi_fini( 295 __in efx_nic_t *enp); 296 297extern void 298ef10_mcdi_send_request( 299 __in efx_nic_t *enp, 300 __in void *hdrp, 301 __in size_t hdr_len, 302 __in void *sdup, 303 __in size_t sdu_len); 304 305extern __checkReturn boolean_t 306ef10_mcdi_poll_response( 307 __in efx_nic_t *enp); 308 309extern void 310ef10_mcdi_read_response( 311 __in efx_nic_t *enp, 312 __out_bcount(length) void *bufferp, 313 __in size_t offset, 314 __in size_t length); 315 316extern efx_rc_t 317ef10_mcdi_poll_reboot( 318 __in efx_nic_t *enp); 319 320extern __checkReturn efx_rc_t 321ef10_mcdi_feature_supported( 322 __in efx_nic_t *enp, 323 __in efx_mcdi_feature_id_t id, 324 __out boolean_t *supportedp); 325 326#endif /* EFSYS_OPT_MCDI */ 327 328/* NVRAM */ 329 330#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 331 332extern __checkReturn efx_rc_t 333ef10_nvram_buf_read_tlv( 334 __in efx_nic_t *enp, 335 __in_bcount(max_seg_size) caddr_t seg_data, 336 __in size_t max_seg_size, 337 __in uint32_t tag, 338 __deref_out_bcount_opt(*sizep) caddr_t *datap, 339 __out size_t *sizep); 340 341extern __checkReturn efx_rc_t 342ef10_nvram_buf_write_tlv( 343 __inout_bcount(partn_size) caddr_t partn_data, 344 __in size_t partn_size, 345 __in uint32_t tag, 346 __in_bcount(tag_size) caddr_t tag_data, 347 __in size_t tag_size, 348 __out size_t *total_lengthp); 349 350extern __checkReturn efx_rc_t 351ef10_nvram_partn_read_tlv( 352 __in efx_nic_t *enp, 353 __in uint32_t partn, 354 __in uint32_t tag, 355 __deref_out_bcount_opt(*sizep) caddr_t *datap, 356 __out size_t *sizep); 357 358extern __checkReturn efx_rc_t 359ef10_nvram_partn_write_tlv( 360 __in efx_nic_t *enp, 361 __in uint32_t partn, 362 __in uint32_t tag, 363 __in_bcount(size) caddr_t data, 364 __in size_t size); 365 366extern __checkReturn efx_rc_t 367ef10_nvram_partn_write_segment_tlv( 368 __in efx_nic_t *enp, 369 __in uint32_t partn, 370 __in uint32_t tag, 371 __in_bcount(size) caddr_t data, 372 __in size_t size, 373 __in boolean_t all_segments); 374 375extern __checkReturn efx_rc_t 376ef10_nvram_partn_lock( 377 __in efx_nic_t *enp, 378 __in uint32_t partn); 379 380extern void 381ef10_nvram_partn_unlock( 382 __in efx_nic_t *enp, 383 __in uint32_t partn); 384 385#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 386 387#if EFSYS_OPT_NVRAM 388 389#if EFSYS_OPT_DIAG 390 391extern __checkReturn efx_rc_t 392ef10_nvram_test( 393 __in efx_nic_t *enp); 394 395#endif /* EFSYS_OPT_DIAG */ 396 397extern __checkReturn efx_rc_t 398ef10_nvram_type_to_partn( 399 __in efx_nic_t *enp, 400 __in efx_nvram_type_t type, 401 __out uint32_t *partnp); 402 403extern __checkReturn efx_rc_t 404ef10_nvram_partn_size( 405 __in efx_nic_t *enp, 406 __in uint32_t partn, 407 __out size_t *sizep); 408 409extern __checkReturn efx_rc_t 410ef10_nvram_partn_rw_start( 411 __in efx_nic_t *enp, 412 __in uint32_t partn, 413 __out size_t *chunk_sizep); 414 415extern __checkReturn efx_rc_t 416ef10_nvram_partn_read_mode( 417 __in efx_nic_t *enp, 418 __in uint32_t partn, 419 __in unsigned int offset, 420 __out_bcount(size) caddr_t data, 421 __in size_t size, 422 __in uint32_t mode); 423 424extern __checkReturn efx_rc_t 425ef10_nvram_partn_read( 426 __in efx_nic_t *enp, 427 __in uint32_t partn, 428 __in unsigned int offset, 429 __out_bcount(size) caddr_t data, 430 __in size_t size); 431 432extern __checkReturn efx_rc_t 433ef10_nvram_partn_erase( 434 __in efx_nic_t *enp, 435 __in uint32_t partn, 436 __in unsigned int offset, 437 __in size_t size); 438 439extern __checkReturn efx_rc_t 440ef10_nvram_partn_write( 441 __in efx_nic_t *enp, 442 __in uint32_t partn, 443 __in unsigned int offset, 444 __out_bcount(size) caddr_t data, 445 __in size_t size); 446 447extern void 448ef10_nvram_partn_rw_finish( 449 __in efx_nic_t *enp, 450 __in uint32_t partn); 451 452extern __checkReturn efx_rc_t 453ef10_nvram_partn_get_version( 454 __in efx_nic_t *enp, 455 __in uint32_t partn, 456 __out uint32_t *subtypep, 457 __out_ecount(4) uint16_t version[4]); 458 459extern __checkReturn efx_rc_t 460ef10_nvram_partn_set_version( 461 __in efx_nic_t *enp, 462 __in uint32_t partn, 463 __in_ecount(4) uint16_t version[4]); 464 465extern __checkReturn efx_rc_t 466ef10_nvram_buffer_validate( 467 __in efx_nic_t *enp, 468 __in uint32_t partn, 469 __in_bcount(buffer_size) 470 caddr_t bufferp, 471 __in size_t buffer_size); 472 473extern __checkReturn efx_rc_t 474ef10_nvram_buffer_create( 475 __in efx_nic_t *enp, 476 __in uint16_t partn_type, 477 __in_bcount(buffer_size) 478 caddr_t bufferp, 479 __in size_t buffer_size); 480 481extern __checkReturn efx_rc_t 482ef10_nvram_buffer_find_item_start( 483 __in_bcount(buffer_size) 484 caddr_t bufferp, 485 __in size_t buffer_size, 486 __out uint32_t *startp 487 ); 488 489extern __checkReturn efx_rc_t 490ef10_nvram_buffer_find_end( 491 __in_bcount(buffer_size) 492 caddr_t bufferp, 493 __in size_t buffer_size, 494 __in uint32_t offset, 495 __out uint32_t *endp 496 ); 497 498extern __checkReturn __success(return != B_FALSE) boolean_t 499ef10_nvram_buffer_find_item( 500 __in_bcount(buffer_size) 501 caddr_t bufferp, 502 __in size_t buffer_size, 503 __in uint32_t offset, 504 __out uint32_t *startp, 505 __out uint32_t *lengthp 506 ); 507 508extern __checkReturn efx_rc_t 509ef10_nvram_buffer_get_item( 510 __in_bcount(buffer_size) 511 caddr_t bufferp, 512 __in size_t buffer_size, 513 __in uint32_t offset, 514 __in uint32_t length, 515 __out_bcount_part(item_max_size, *lengthp) 516 caddr_t itemp, 517 __in size_t item_max_size, 518 __out uint32_t *lengthp 519 ); 520 521extern __checkReturn efx_rc_t 522ef10_nvram_buffer_insert_item( 523 __in_bcount(buffer_size) 524 caddr_t bufferp, 525 __in size_t buffer_size, 526 __in uint32_t offset, 527 __in_bcount(length) caddr_t keyp, 528 __in uint32_t length, 529 __out uint32_t *lengthp 530 ); 531 532extern __checkReturn efx_rc_t 533ef10_nvram_buffer_delete_item( 534 __in_bcount(buffer_size) 535 caddr_t bufferp, 536 __in size_t buffer_size, 537 __in uint32_t offset, 538 __in uint32_t length, 539 __in uint32_t end 540 ); 541 542extern __checkReturn efx_rc_t 543ef10_nvram_buffer_finish( 544 __in_bcount(buffer_size) 545 caddr_t bufferp, 546 __in size_t buffer_size 547 ); 548 549#endif /* EFSYS_OPT_NVRAM */ 550 551 552/* PHY */ 553 554typedef struct ef10_link_state_s { 555 uint32_t els_adv_cap_mask; 556 uint32_t els_lp_cap_mask; 557 unsigned int els_fcntl; 558 efx_link_mode_t els_link_mode; 559#if EFSYS_OPT_LOOPBACK 560 efx_loopback_type_t els_loopback; 561#endif 562 boolean_t els_mac_up; 563} ef10_link_state_t; 564 565extern void 566ef10_phy_link_ev( 567 __in efx_nic_t *enp, 568 __in efx_qword_t *eqp, 569 __out efx_link_mode_t *link_modep); 570 571extern __checkReturn efx_rc_t 572ef10_phy_get_link( 573 __in efx_nic_t *enp, 574 __out ef10_link_state_t *elsp); 575 576extern __checkReturn efx_rc_t 577ef10_phy_power( 578 __in efx_nic_t *enp, 579 __in boolean_t on); 580 581extern __checkReturn efx_rc_t 582ef10_phy_reconfigure( 583 __in efx_nic_t *enp); 584 585extern __checkReturn efx_rc_t 586ef10_phy_verify( 587 __in efx_nic_t *enp); 588 589extern __checkReturn efx_rc_t 590ef10_phy_oui_get( 591 __in efx_nic_t *enp, 592 __out uint32_t *ouip); 593 594#if EFSYS_OPT_PHY_STATS 595 596extern __checkReturn efx_rc_t 597ef10_phy_stats_update( 598 __in efx_nic_t *enp, 599 __in efsys_mem_t *esmp, 600 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 601 602#endif /* EFSYS_OPT_PHY_STATS */ 603 604 605/* TX */ 606 607extern __checkReturn efx_rc_t 608ef10_tx_init( 609 __in efx_nic_t *enp); 610 611extern void 612ef10_tx_fini( 613 __in efx_nic_t *enp); 614 615extern __checkReturn efx_rc_t 616ef10_tx_qcreate( 617 __in efx_nic_t *enp, 618 __in unsigned int index, 619 __in unsigned int label, 620 __in efsys_mem_t *esmp, 621 __in size_t n, 622 __in uint32_t id, 623 __in uint16_t flags, 624 __in efx_evq_t *eep, 625 __in efx_txq_t *etp, 626 __out unsigned int *addedp); 627 628extern void 629ef10_tx_qdestroy( 630 __in efx_txq_t *etp); 631 632extern __checkReturn efx_rc_t 633ef10_tx_qpost( 634 __in efx_txq_t *etp, 635 __in_ecount(n) efx_buffer_t *eb, 636 __in unsigned int n, 637 __in unsigned int completed, 638 __inout unsigned int *addedp); 639 640extern void 641ef10_tx_qpush( 642 __in efx_txq_t *etp, 643 __in unsigned int added, 644 __in unsigned int pushed); 645 646extern __checkReturn efx_rc_t 647ef10_tx_qpace( 648 __in efx_txq_t *etp, 649 __in unsigned int ns); 650 651extern __checkReturn efx_rc_t 652ef10_tx_qflush( 653 __in efx_txq_t *etp); 654 655extern void 656ef10_tx_qenable( 657 __in efx_txq_t *etp); 658 659extern __checkReturn efx_rc_t 660ef10_tx_qpio_enable( 661 __in efx_txq_t *etp); 662 663extern void 664ef10_tx_qpio_disable( 665 __in efx_txq_t *etp); 666 667extern __checkReturn efx_rc_t 668ef10_tx_qpio_write( 669 __in efx_txq_t *etp, 670 __in_ecount(buf_length) uint8_t *buffer, 671 __in size_t buf_length, 672 __in size_t pio_buf_offset); 673 674extern __checkReturn efx_rc_t 675ef10_tx_qpio_post( 676 __in efx_txq_t *etp, 677 __in size_t pkt_length, 678 __in unsigned int completed, 679 __inout unsigned int *addedp); 680 681extern __checkReturn efx_rc_t 682ef10_tx_qdesc_post( 683 __in efx_txq_t *etp, 684 __in_ecount(n) efx_desc_t *ed, 685 __in unsigned int n, 686 __in unsigned int completed, 687 __inout unsigned int *addedp); 688 689extern void 690ef10_tx_qdesc_dma_create( 691 __in efx_txq_t *etp, 692 __in efsys_dma_addr_t addr, 693 __in size_t size, 694 __in boolean_t eop, 695 __out efx_desc_t *edp); 696 697extern void 698ef10_tx_qdesc_tso_create( 699 __in efx_txq_t *etp, 700 __in uint16_t ipv4_id, 701 __in uint32_t tcp_seq, 702 __in uint8_t tcp_flags, 703 __out efx_desc_t *edp); 704 705extern void 706ef10_tx_qdesc_tso2_create( 707 __in efx_txq_t *etp, 708 __in uint16_t ipv4_id, 709 __in uint32_t tcp_seq, 710 __in uint16_t tcp_mss, 711 __out_ecount(count) efx_desc_t *edp, 712 __in int count); 713 714extern void 715ef10_tx_qdesc_vlantci_create( 716 __in efx_txq_t *etp, 717 __in uint16_t vlan_tci, 718 __out efx_desc_t *edp); 719 720 721#if EFSYS_OPT_QSTATS 722 723extern void 724ef10_tx_qstats_update( 725 __in efx_txq_t *etp, 726 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 727 728#endif /* EFSYS_OPT_QSTATS */ 729 730typedef uint32_t efx_piobuf_handle_t; 731 732#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 733 734extern __checkReturn efx_rc_t 735ef10_nic_pio_alloc( 736 __inout efx_nic_t *enp, 737 __out uint32_t *bufnump, 738 __out efx_piobuf_handle_t *handlep, 739 __out uint32_t *blknump, 740 __out uint32_t *offsetp, 741 __out size_t *sizep); 742 743extern __checkReturn efx_rc_t 744ef10_nic_pio_free( 745 __inout efx_nic_t *enp, 746 __in uint32_t bufnum, 747 __in uint32_t blknum); 748 749extern __checkReturn efx_rc_t 750ef10_nic_pio_link( 751 __inout efx_nic_t *enp, 752 __in uint32_t vi_index, 753 __in efx_piobuf_handle_t handle); 754 755extern __checkReturn efx_rc_t 756ef10_nic_pio_unlink( 757 __inout efx_nic_t *enp, 758 __in uint32_t vi_index); 759 760 761/* VPD */ 762 763#if EFSYS_OPT_VPD 764 765extern __checkReturn efx_rc_t 766ef10_vpd_init( 767 __in efx_nic_t *enp); 768 769extern __checkReturn efx_rc_t 770ef10_vpd_size( 771 __in efx_nic_t *enp, 772 __out size_t *sizep); 773 774extern __checkReturn efx_rc_t 775ef10_vpd_read( 776 __in efx_nic_t *enp, 777 __out_bcount(size) caddr_t data, 778 __in size_t size); 779 780extern __checkReturn efx_rc_t 781ef10_vpd_verify( 782 __in efx_nic_t *enp, 783 __in_bcount(size) caddr_t data, 784 __in size_t size); 785 786extern __checkReturn efx_rc_t 787ef10_vpd_reinit( 788 __in efx_nic_t *enp, 789 __in_bcount(size) caddr_t data, 790 __in size_t size); 791 792extern __checkReturn efx_rc_t 793ef10_vpd_get( 794 __in efx_nic_t *enp, 795 __in_bcount(size) caddr_t data, 796 __in size_t size, 797 __inout efx_vpd_value_t *evvp); 798 799extern __checkReturn efx_rc_t 800ef10_vpd_set( 801 __in efx_nic_t *enp, 802 __in_bcount(size) caddr_t data, 803 __in size_t size, 804 __in efx_vpd_value_t *evvp); 805 806extern __checkReturn efx_rc_t 807ef10_vpd_next( 808 __in efx_nic_t *enp, 809 __in_bcount(size) caddr_t data, 810 __in size_t size, 811 __out efx_vpd_value_t *evvp, 812 __inout unsigned int *contp); 813 814extern __checkReturn efx_rc_t 815ef10_vpd_write( 816 __in efx_nic_t *enp, 817 __in_bcount(size) caddr_t data, 818 __in size_t size); 819 820extern void 821ef10_vpd_fini( 822 __in efx_nic_t *enp); 823 824#endif /* EFSYS_OPT_VPD */ 825 826 827/* RX */ 828 829extern __checkReturn efx_rc_t 830ef10_rx_init( 831 __in efx_nic_t *enp); 832 833#if EFSYS_OPT_RX_SCATTER 834extern __checkReturn efx_rc_t 835ef10_rx_scatter_enable( 836 __in efx_nic_t *enp, 837 __in unsigned int buf_size); 838#endif /* EFSYS_OPT_RX_SCATTER */ 839 840 841#if EFSYS_OPT_RX_SCALE 842 843extern __checkReturn efx_rc_t 844ef10_rx_scale_mode_set( 845 __in efx_nic_t *enp, 846 __in efx_rx_hash_alg_t alg, 847 __in efx_rx_hash_type_t type, 848 __in boolean_t insert); 849 850extern __checkReturn efx_rc_t 851ef10_rx_scale_key_set( 852 __in efx_nic_t *enp, 853 __in_ecount(n) uint8_t *key, 854 __in size_t n); 855 856extern __checkReturn efx_rc_t 857ef10_rx_scale_tbl_set( 858 __in efx_nic_t *enp, 859 __in_ecount(n) unsigned int *table, 860 __in size_t n); 861 862extern __checkReturn uint32_t 863ef10_rx_prefix_hash( 864 __in efx_nic_t *enp, 865 __in efx_rx_hash_alg_t func, 866 __in uint8_t *buffer); 867 868#endif /* EFSYS_OPT_RX_SCALE */ 869 870extern __checkReturn efx_rc_t 871ef10_rx_prefix_pktlen( 872 __in efx_nic_t *enp, 873 __in uint8_t *buffer, 874 __out uint16_t *lengthp); 875 876extern void 877ef10_rx_qpost( 878 __in efx_rxq_t *erp, 879 __in_ecount(n) efsys_dma_addr_t *addrp, 880 __in size_t size, 881 __in unsigned int n, 882 __in unsigned int completed, 883 __in unsigned int added); 884 885extern void 886ef10_rx_qpush( 887 __in efx_rxq_t *erp, 888 __in unsigned int added, 889 __inout unsigned int *pushedp); 890 891extern __checkReturn efx_rc_t 892ef10_rx_qflush( 893 __in efx_rxq_t *erp); 894 895extern void 896ef10_rx_qenable( 897 __in efx_rxq_t *erp); 898 899extern __checkReturn efx_rc_t 900ef10_rx_qcreate( 901 __in efx_nic_t *enp, 902 __in unsigned int index, 903 __in unsigned int label, 904 __in efx_rxq_type_t type, 905 __in efsys_mem_t *esmp, 906 __in size_t n, 907 __in uint32_t id, 908 __in efx_evq_t *eep, 909 __in efx_rxq_t *erp); 910 911extern void 912ef10_rx_qdestroy( 913 __in efx_rxq_t *erp); 914 915extern void 916ef10_rx_fini( 917 __in efx_nic_t *enp); 918 919#if EFSYS_OPT_FILTER 920 921typedef struct ef10_filter_handle_s { 922 uint32_t efh_lo; 923 uint32_t efh_hi; 924} ef10_filter_handle_t; 925 926typedef struct ef10_filter_entry_s { 927 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 928 ef10_filter_handle_t efe_handle; 929} ef10_filter_entry_t; 930 931/* 932 * BUSY flag indicates that an update is in progress. 933 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 934 */ 935#define EFX_EF10_FILTER_FLAG_BUSY 1U 936#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 937#define EFX_EF10_FILTER_FLAGS 3U 938 939/* 940 * Size of the hash table used by the driver. Doesn't need to be the 941 * same size as the hardware's table. 942 */ 943#define EFX_EF10_FILTER_TBL_ROWS 8192 944 945/* Only need to allow for one directed and one unknown unicast filter */ 946#define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 947 948/* Allow for the broadcast address to be added to the multicast list */ 949#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 950 951typedef struct ef10_filter_table_s { 952 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 953 efx_rxq_t * eft_default_rxq; 954 boolean_t eft_using_rss; 955 uint32_t eft_unicst_filter_indexes[ 956 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 957 boolean_t eft_unicst_filter_count; 958 uint32_t eft_mulcst_filter_indexes[ 959 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 960 uint32_t eft_mulcst_filter_count; 961 boolean_t eft_using_all_mulcst; 962} ef10_filter_table_t; 963 964 __checkReturn efx_rc_t 965ef10_filter_init( 966 __in efx_nic_t *enp); 967 968 void 969ef10_filter_fini( 970 __in efx_nic_t *enp); 971 972 __checkReturn efx_rc_t 973ef10_filter_restore( 974 __in efx_nic_t *enp); 975 976 __checkReturn efx_rc_t 977ef10_filter_add( 978 __in efx_nic_t *enp, 979 __inout efx_filter_spec_t *spec, 980 __in boolean_t may_replace); 981 982 __checkReturn efx_rc_t 983ef10_filter_delete( 984 __in efx_nic_t *enp, 985 __inout efx_filter_spec_t *spec); 986 987extern __checkReturn efx_rc_t 988ef10_filter_supported_filters( 989 __in efx_nic_t *enp, 990 __out uint32_t *list, 991 __out size_t *length); 992 993extern __checkReturn efx_rc_t 994ef10_filter_reconfigure( 995 __in efx_nic_t *enp, 996 __in_ecount(6) uint8_t const *mac_addr, 997 __in boolean_t all_unicst, 998 __in boolean_t mulcst, 999 __in boolean_t all_mulcst, 1000 __in boolean_t brdcst, 1001 __in_ecount(6*count) uint8_t const *addrs, 1002 __in uint32_t count); 1003 1004extern void 1005ef10_filter_get_default_rxq( 1006 __in efx_nic_t *enp, 1007 __out efx_rxq_t **erpp, 1008 __out boolean_t *using_rss); 1009 1010extern void 1011ef10_filter_default_rxq_set( 1012 __in efx_nic_t *enp, 1013 __in efx_rxq_t *erp, 1014 __in boolean_t using_rss); 1015 1016extern void 1017ef10_filter_default_rxq_clear( 1018 __in efx_nic_t *enp); 1019 1020 1021#endif /* EFSYS_OPT_FILTER */ 1022 1023extern __checkReturn efx_rc_t 1024efx_mcdi_get_function_info( 1025 __in efx_nic_t *enp, 1026 __out uint32_t *pfp, 1027 __out_opt uint32_t *vfp); 1028 1029extern __checkReturn efx_rc_t 1030efx_mcdi_privilege_mask( 1031 __in efx_nic_t *enp, 1032 __in uint32_t pf, 1033 __in uint32_t vf, 1034 __out uint32_t *maskp); 1035 1036extern __checkReturn efx_rc_t 1037efx_mcdi_get_port_assignment( 1038 __in efx_nic_t *enp, 1039 __out uint32_t *portp); 1040 1041extern __checkReturn efx_rc_t 1042efx_mcdi_get_port_modes( 1043 __in efx_nic_t *enp, 1044 __out uint32_t *modesp, 1045 __out_opt uint32_t *current_modep); 1046 1047extern __checkReturn efx_rc_t 1048ef10_nic_get_port_mode_bandwidth( 1049 __in uint32_t port_mode, 1050 __out uint32_t *bandwidth_mbpsp); 1051 1052extern __checkReturn efx_rc_t 1053efx_mcdi_get_mac_address_pf( 1054 __in efx_nic_t *enp, 1055 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1056 1057extern __checkReturn efx_rc_t 1058efx_mcdi_get_mac_address_vf( 1059 __in efx_nic_t *enp, 1060 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1061 1062extern __checkReturn efx_rc_t 1063efx_mcdi_get_clock( 1064 __in efx_nic_t *enp, 1065 __out uint32_t *sys_freqp, 1066 __out uint32_t *dpcpu_freqp); 1067 1068 1069extern __checkReturn efx_rc_t 1070efx_mcdi_get_vector_cfg( 1071 __in efx_nic_t *enp, 1072 __out_opt uint32_t *vec_basep, 1073 __out_opt uint32_t *pf_nvecp, 1074 __out_opt uint32_t *vf_nvecp); 1075 1076extern __checkReturn efx_rc_t 1077ef10_get_datapath_caps( 1078 __in efx_nic_t *enp); 1079 1080extern __checkReturn efx_rc_t 1081ef10_get_privilege_mask( 1082 __in efx_nic_t *enp, 1083 __out uint32_t *maskp); 1084 1085extern __checkReturn efx_rc_t 1086ef10_external_port_mapping( 1087 __in efx_nic_t *enp, 1088 __in uint32_t port, 1089 __out uint8_t *external_portp); 1090 1091 1092#ifdef __cplusplus 1093} 1094#endif 1095 1096#endif /* _SYS_EF10_IMPL_H */ 1097