1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: releng/11.0/sys/dev/sdhci/sdhci_pci.c 299414 2016-05-11 07:50:35Z trasz $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <dev/pci/pcireg.h> 43#include <dev/pci/pcivar.h> 44 45#include <machine/bus.h> 46#include <machine/resource.h> 47#include <machine/stdarg.h> 48 49#include <dev/mmc/bridge.h> 50#include <dev/mmc/mmcreg.h> 51#include <dev/mmc/mmcbrvar.h> 52 53#include "sdhci.h" 54#include "mmcbr_if.h" 55#include "sdhci_if.h" 56 57/* 58 * PCI registers 59 */ 60 61#define PCI_SDHCI_IFPIO 0x00 62#define PCI_SDHCI_IFDMA 0x01 63#define PCI_SDHCI_IFVENDOR 0x02 64 65#define PCI_SLOT_INFO 0x40 /* 8 bits */ 66#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69/* 70 * RICOH specific PCI registers 71 */ 72#define SDHC_PCI_MODE_KEY 0xf9 73#define SDHC_PCI_MODE 0x150 74#define SDHC_PCI_MODE_SD20 0x10 75#define SDHC_PCI_BASE_FREQ_KEY 0xfc 76#define SDHC_PCI_BASE_FREQ 0xe1 77 78static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 const char *desc; 82 u_int quirks; 83} sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87 SDHCI_QUIRK_FORCE_DMA | 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90 SDHCI_QUIRK_LOWER_FREQUENCY }, 91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92 SDHCI_QUIRK_FORCE_DMA }, 93 { 0x05501524, 0xffff, "ENE CB712 SD", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x05511524, 0xffff, "ENE CB712 SD 2", 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07501524, 0xffff, "ENE CB714 SD", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x07511524, 0xffff, "ENE CB714 SD 2", 101 SDHCI_QUIRK_RESET_ON_IOS | 102 SDHCI_QUIRK_BROKEN_TIMINGS }, 103 { 0x410111ab, 0xffff, "Marvell CaFe SD", 104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106 SDHCI_QUIRK_32BIT_DMA_SIZE | 107 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 109 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 110 { 0, 0xffff, NULL, 111 0 } 112}; 113 114struct sdhci_pci_softc { 115 u_int quirks; /* Chip specific quirks */ 116 struct resource *irq_res; /* IRQ resource */ 117 void *intrhand; /* Interrupt handle */ 118 119 int num_slots; /* Number of slots on this controller */ 120 struct sdhci_slot slots[6]; 121 struct resource *mem_res[6]; /* Memory resource */ 122 uint8_t cfg_freq; /* Saved mode */ 123 uint8_t cfg_mode; /* Saved frequency */ 124}; 125 126static int sdhci_enable_msi = 1; 127SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 128 0, "Enable MSI interrupts"); 129 130static uint8_t 131sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 132{ 133 struct sdhci_pci_softc *sc = device_get_softc(dev); 134 135 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 136 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 137 return bus_read_1(sc->mem_res[slot->num], off); 138} 139 140static void 141sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 142{ 143 struct sdhci_pci_softc *sc = device_get_softc(dev); 144 145 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 146 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 147 bus_write_1(sc->mem_res[slot->num], off, val); 148} 149 150static uint16_t 151sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 152{ 153 struct sdhci_pci_softc *sc = device_get_softc(dev); 154 155 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 157 return bus_read_2(sc->mem_res[slot->num], off); 158} 159 160static void 161sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 162{ 163 struct sdhci_pci_softc *sc = device_get_softc(dev); 164 165 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167 bus_write_2(sc->mem_res[slot->num], off, val); 168} 169 170static uint32_t 171sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 172{ 173 struct sdhci_pci_softc *sc = device_get_softc(dev); 174 175 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 176 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 177 return bus_read_4(sc->mem_res[slot->num], off); 178} 179 180static void 181sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 182{ 183 struct sdhci_pci_softc *sc = device_get_softc(dev); 184 185 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 186 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 187 bus_write_4(sc->mem_res[slot->num], off, val); 188} 189 190static void 191sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 192 bus_size_t off, uint32_t *data, bus_size_t count) 193{ 194 struct sdhci_pci_softc *sc = device_get_softc(dev); 195 196 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 197} 198 199static void 200sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 201 bus_size_t off, uint32_t *data, bus_size_t count) 202{ 203 struct sdhci_pci_softc *sc = device_get_softc(dev); 204 205 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 206} 207 208static void sdhci_pci_intr(void *arg); 209 210static void 211sdhci_lower_frequency(device_t dev) 212{ 213 struct sdhci_pci_softc *sc = device_get_softc(dev); 214 215 /* 216 * Enable SD2.0 mode. 217 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 218 */ 219 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 220 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 221 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 222 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 223 224 /* 225 * Some SD/MMC cards don't work with the default base 226 * clock frequency of 200 MHz. Lower it to 50 MHz. 227 */ 228 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 229 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 230 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 231 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 232} 233 234static void 235sdhci_restore_frequency(device_t dev) 236{ 237 struct sdhci_pci_softc *sc = device_get_softc(dev); 238 239 /* Restore mode. */ 240 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 241 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 242 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 243 244 /* Restore frequency. */ 245 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 246 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 247 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 248} 249 250static int 251sdhci_pci_probe(device_t dev) 252{ 253 uint32_t model; 254 uint16_t subvendor; 255 uint8_t class, subclass; 256 int i, result; 257 258 model = (uint32_t)pci_get_device(dev) << 16; 259 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 260 subvendor = pci_get_subvendor(dev); 261 class = pci_get_class(dev); 262 subclass = pci_get_subclass(dev); 263 264 result = ENXIO; 265 for (i = 0; sdhci_devices[i].model != 0; i++) { 266 if (sdhci_devices[i].model == model && 267 (sdhci_devices[i].subvendor == 0xffff || 268 sdhci_devices[i].subvendor == subvendor)) { 269 device_set_desc(dev, sdhci_devices[i].desc); 270 result = BUS_PROBE_DEFAULT; 271 break; 272 } 273 } 274 if (result == ENXIO && class == PCIC_BASEPERIPH && 275 subclass == PCIS_BASEPERIPH_SDHC) { 276 device_set_desc(dev, "Generic SD HCI"); 277 result = BUS_PROBE_GENERIC; 278 } 279 280 return (result); 281} 282 283static int 284sdhci_pci_attach(device_t dev) 285{ 286 struct sdhci_pci_softc *sc = device_get_softc(dev); 287 uint32_t model; 288 uint16_t subvendor; 289 int bar, err, rid, slots, i; 290 291 model = (uint32_t)pci_get_device(dev) << 16; 292 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 293 subvendor = pci_get_subvendor(dev); 294 /* Apply chip specific quirks. */ 295 for (i = 0; sdhci_devices[i].model != 0; i++) { 296 if (sdhci_devices[i].model == model && 297 (sdhci_devices[i].subvendor == 0xffff || 298 sdhci_devices[i].subvendor == subvendor)) { 299 sc->quirks = sdhci_devices[i].quirks; 300 break; 301 } 302 } 303 /* Some controllers need to be bumped into the right mode. */ 304 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 305 sdhci_lower_frequency(dev); 306 /* Read slots info from PCI registers. */ 307 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 308 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 309 slots = PCI_SLOT_INFO_SLOTS(slots); 310 if (slots > 6 || bar > 5) { 311 device_printf(dev, "Incorrect slots information (%d, %d).\n", 312 slots, bar); 313 return (EINVAL); 314 } 315 /* Allocate IRQ. */ 316 i = 1; 317 rid = 0; 318 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 319 rid = 1; 320 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 321 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 322 if (sc->irq_res == NULL) { 323 device_printf(dev, "Can't allocate IRQ\n"); 324 pci_release_msi(dev); 325 return (ENOMEM); 326 } 327 /* Scan all slots. */ 328 for (i = 0; i < slots; i++) { 329 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 330 331 /* Allocate memory. */ 332 rid = PCIR_BAR(bar + i); 333 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 334 &rid, RF_ACTIVE); 335 if (sc->mem_res[i] == NULL) { 336 device_printf(dev, "Can't allocate memory for slot %d\n", i); 337 continue; 338 } 339 340 slot->quirks = sc->quirks; 341 342 if (sdhci_init_slot(dev, slot, i) != 0) 343 continue; 344 345 sc->num_slots++; 346 } 347 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 348 /* Activate the interrupt */ 349 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 350 NULL, sdhci_pci_intr, sc, &sc->intrhand); 351 if (err) 352 device_printf(dev, "Can't setup IRQ\n"); 353 pci_enable_busmaster(dev); 354 /* Process cards detection. */ 355 for (i = 0; i < sc->num_slots; i++) { 356 struct sdhci_slot *slot = &sc->slots[i]; 357 358 sdhci_start_slot(slot); 359 } 360 361 return (0); 362} 363 364static int 365sdhci_pci_detach(device_t dev) 366{ 367 struct sdhci_pci_softc *sc = device_get_softc(dev); 368 int i; 369 370 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 371 bus_release_resource(dev, SYS_RES_IRQ, 372 rman_get_rid(sc->irq_res), sc->irq_res); 373 pci_release_msi(dev); 374 375 for (i = 0; i < sc->num_slots; i++) { 376 struct sdhci_slot *slot = &sc->slots[i]; 377 378 sdhci_cleanup_slot(slot); 379 bus_release_resource(dev, SYS_RES_MEMORY, 380 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 381 } 382 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 383 sdhci_restore_frequency(dev); 384 return (0); 385} 386 387static int 388sdhci_pci_shutdown(device_t dev) 389{ 390 struct sdhci_pci_softc *sc = device_get_softc(dev); 391 392 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 393 sdhci_restore_frequency(dev); 394 return (0); 395} 396 397static int 398sdhci_pci_suspend(device_t dev) 399{ 400 struct sdhci_pci_softc *sc = device_get_softc(dev); 401 int i, err; 402 403 err = bus_generic_suspend(dev); 404 if (err) 405 return (err); 406 for (i = 0; i < sc->num_slots; i++) 407 sdhci_generic_suspend(&sc->slots[i]); 408 return (0); 409} 410 411static int 412sdhci_pci_resume(device_t dev) 413{ 414 struct sdhci_pci_softc *sc = device_get_softc(dev); 415 int i, err; 416 417 for (i = 0; i < sc->num_slots; i++) 418 sdhci_generic_resume(&sc->slots[i]); 419 err = bus_generic_resume(dev); 420 if (err) 421 return (err); 422 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 423 sdhci_lower_frequency(dev); 424 return (0); 425} 426 427static void 428sdhci_pci_intr(void *arg) 429{ 430 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 431 int i; 432 433 for (i = 0; i < sc->num_slots; i++) { 434 struct sdhci_slot *slot = &sc->slots[i]; 435 sdhci_generic_intr(slot); 436 } 437} 438 439static device_method_t sdhci_methods[] = { 440 /* device_if */ 441 DEVMETHOD(device_probe, sdhci_pci_probe), 442 DEVMETHOD(device_attach, sdhci_pci_attach), 443 DEVMETHOD(device_detach, sdhci_pci_detach), 444 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 445 DEVMETHOD(device_suspend, sdhci_pci_suspend), 446 DEVMETHOD(device_resume, sdhci_pci_resume), 447 448 /* Bus interface */ 449 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 450 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 451 452 /* mmcbr_if */ 453 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 454 DEVMETHOD(mmcbr_request, sdhci_generic_request), 455 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 456 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 457 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 458 459 /* SDHCI registers accessors */ 460 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 461 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 462 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 463 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 464 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 465 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 466 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 467 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 468 469 DEVMETHOD_END 470}; 471 472static driver_t sdhci_pci_driver = { 473 "sdhci_pci", 474 sdhci_methods, 475 sizeof(struct sdhci_pci_softc), 476}; 477static devclass_t sdhci_pci_devclass; 478 479DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 480 NULL); 481MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 482DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); 483MODULE_DEPEND(sdhci_pci, mmc, 1, 1, 1); 484