1/*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD: releng/11.0/sys/dev/mpr/mpi/mpi2_cnfg.h 299263 2016-05-09 16:12:32Z slm $ 33 */ 34 35/* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2_cnfg.h 42 * Title: MPI Configuration messages and pages 43 * Creation Date: November 10, 2006 44 * 45 * mpi2_cnfg.h Version: 02.00.35 46 * 47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 48 * prefix are for use only on MPI v2.5 products, and must not be used 49 * with MPI v2.0 products. Unless otherwise noted, names beginning with 50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 51 * 52 * Version History 53 * --------------- 54 * 55 * Date Version Description 56 * -------- -------- ------------------------------------------------------ 57 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 58 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 59 * Added Manufacturing Page 11. 60 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 61 * define. 62 * 06-26-07 02.00.02 Adding generic structure for product-specific 63 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 64 * Rework of BIOS Page 2 configuration page. 65 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 66 * forms. 67 * Added configuration pages IOC Page 8 and Driver 68 * Persistent Mapping Page 0. 69 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 70 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 71 * RAID Physical Disk Pages 0 and 1, RAID Configuration 72 * Page 0). 73 * Added new value for AccessStatus field of SAS Device 74 * Page 0 (_SATA_NEEDS_INITIALIZATION). 75 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 76 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 77 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 78 * NVDATA. 79 * Modified IOC Page 7 to use masks and added field for 80 * SASBroadcastPrimitiveMasks. 81 * Added MPI2_CONFIG_PAGE_BIOS_4. 82 * Added MPI2_CONFIG_PAGE_LOG_0. 83 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 84 * Added SAS Device IDs. 85 * Updated Integrated RAID configuration pages including 86 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 87 * Page 0. 88 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 89 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 90 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 91 * Added missing MaxNumRoutedSasAddresses field to 92 * MPI2_CONFIG_PAGE_EXPANDER_0. 93 * Added SAS Port Page 0. 94 * Modified structure layout for 95 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 96 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 97 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 98 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 99 * to 0x000000FF. 100 * Added two new values for the Physical Disk Coercion Size 101 * bits in the Flags field of Manufacturing Page 4. 102 * Added product-specific Manufacturing pages 16 to 31. 103 * Modified Flags bits for controlling write cache on SATA 104 * drives in IO Unit Page 1. 105 * Added new bit to AdditionalControlFlags of SAS IO Unit 106 * Page 1 to control Invalid Topology Correction. 107 * Added additional defines for RAID Volume Page 0 108 * VolumeStatusFlags field. 109 * Modified meaning of RAID Volume Page 0 VolumeSettings 110 * define for auto-configure of hot-swap drives. 111 * Added SupportedPhysDisks field to RAID Volume Page 1 and 112 * added related defines. 113 * Added PhysDiskAttributes field (and related defines) to 114 * RAID Physical Disk Page 0. 115 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 116 * Added three new DiscoveryStatus bits for SAS IO Unit 117 * Page 0 and SAS Expander Page 0. 118 * Removed multiplexing information from SAS IO Unit pages. 119 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 120 * Removed Zone Address Resolved bit from PhyInfo and from 121 * Expander Page 0 Flags field. 122 * Added two new AccessStatus values to SAS Device Page 0 123 * for indicating routing problems. Added 3 reserved words 124 * to this page. 125 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 126 * Inserted missing reserved field into structure for IOC 127 * Page 6. 128 * Added more pending task bits to RAID Volume Page 0 129 * VolumeStatusFlags defines. 130 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 131 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 132 * and SAS Expander Page 0 to flag a downstream initiator 133 * when in simplified routing mode. 134 * Removed SATA Init Failure defines for DiscoveryStatus 135 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 136 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 137 * Added PortGroups, DmaGroup, and ControlGroup fields to 138 * SAS Device Page 0. 139 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 140 * Unit Page 6. 141 * Added expander reduced functionality data to SAS 142 * Expander Page 0. 143 * Added SAS PHY Page 2 and SAS PHY Page 3. 144 * 07-30-09 02.00.12 Added IO Unit Page 7. 145 * Added new device ids. 146 * Added SAS IO Unit Page 5. 147 * Added partial and slumber power management capable flags 148 * to SAS Device Page 0 Flags field. 149 * Added PhyInfo defines for power condition. 150 * Added Ethernet configuration pages. 151 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 152 * Added SAS PHY Page 4 structure and defines. 153 * 02-10-10 02.00.14 Modified the comments for the configuration page 154 * structures that contain an array of data. The host 155 * should use the "count" field in the page data (e.g. the 156 * NumPhys field) to determine the number of valid elements 157 * in the array. 158 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 159 * Added PowerManagementCapabilities to IO Unit Page 7. 160 * Added PortWidthModGroup field to 161 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 162 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 163 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 164 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 165 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 166 * define. 167 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 168 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 169 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 170 * defines. 171 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 172 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 173 * the Pinout field. 174 * Added BoardTemperature and BoardTemperatureUnits fields 175 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 176 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 177 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 178 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 179 * Added IO Unit Page 8, IO Unit Page 9, 180 * and IO Unit Page 10. 181 * Added SASNotifyPrimitiveMasks field to 182 * MPI2_CONFIG_PAGE_IOC_7. 183 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 184 * 05-25-11 02.00.20 Cleaned up a few comments. 185 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 186 * for PCIe link as obsolete. 187 * Added SpinupFlags field containing a Disable Spin-up bit 188 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 189 * Unit Page 4. 190 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 191 * Added UEFIVersion field to BIOS Page 1 and defined new 192 * BiosOptions bits. 193 * Incorporating additions for MPI v2.5. 194 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 195 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 196 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 197 * obsolete for MPI v2.5 and later. 198 * Added some defines for 12G SAS speeds. 199 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 200 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 201 * match the specification. 202 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 203 * future use. 204 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 205 * MPI2_CONFIG_PAGE_MAN_7. 206 * Added EnclosureLevel and ConnectorName fields to 207 * MPI2_CONFIG_PAGE_SAS_DEV_0. 208 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 209 * MPI2_CONFIG_PAGE_SAS_DEV_0. 210 * Added EnclosureLevel field to 211 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 212 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 213 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 214 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 215 * MPI2_CONFIG_PAGE_BIOS_1. 216 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 217 * more defines for the BiosOptions field. 218 * 11-18-14 02.00.30 Updated copyright information. 219 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 220 * Added AdapterOrderAux fields to BIOS Page 3. 221 * 03-16-15 02.00.31 Updated for MPI v2.6. 222 * Added BoardPowerRequirement, PCISlotPowerAllocation, and 223 * Flags field to IO Unit Page 7. 224 * Added IO Unit Page 11. 225 * Added new SAS Phy Event codes 226 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 227 * MPI2_CONFIG_PAGE_BIOS_1. 228 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 229 * -------------------------------------------------------------------------- 230 */ 231 232#ifndef MPI2_CNFG_H 233#define MPI2_CNFG_H 234 235/***************************************************************************** 236* Configuration Page Header and defines 237*****************************************************************************/ 238 239/* Config Page Header */ 240typedef struct _MPI2_CONFIG_PAGE_HEADER 241{ 242 U8 PageVersion; /* 0x00 */ 243 U8 PageLength; /* 0x01 */ 244 U8 PageNumber; /* 0x02 */ 245 U8 PageType; /* 0x03 */ 246} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 247 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 248 249typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 250{ 251 MPI2_CONFIG_PAGE_HEADER Struct; 252 U8 Bytes[4]; 253 U16 Word16[2]; 254 U32 Word32; 255} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 256 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 257 258/* Extended Config Page Header */ 259typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 260{ 261 U8 PageVersion; /* 0x00 */ 262 U8 Reserved1; /* 0x01 */ 263 U8 PageNumber; /* 0x02 */ 264 U8 PageType; /* 0x03 */ 265 U16 ExtPageLength; /* 0x04 */ 266 U8 ExtPageType; /* 0x06 */ 267 U8 Reserved2; /* 0x07 */ 268} MPI2_CONFIG_EXTENDED_PAGE_HEADER, 269 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 270 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 271 272typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 273{ 274 MPI2_CONFIG_PAGE_HEADER Struct; 275 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 276 U8 Bytes[8]; 277 U16 Word16[4]; 278 U32 Word32[2]; 279} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 280 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 281 282 283/* PageType field values */ 284#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 285#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 286#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 287#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 288 289#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 290#define MPI2_CONFIG_PAGETYPE_IOC (0x01) 291#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 292#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 293#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 294#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 295#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 296#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 297 298#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 299 300 301/* ExtPageType field values */ 302#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 303#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 304#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 305#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 306#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 307#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 308#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 309#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 310#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 311#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 312#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 313 314 315/***************************************************************************** 316* PageAddress defines 317*****************************************************************************/ 318 319/* RAID Volume PageAddress format */ 320#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 321#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 322#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 323 324#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 325 326 327/* RAID Physical Disk PageAddress format */ 328#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 329#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 330#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 331#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 332 333#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 334#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 335 336 337/* SAS Expander PageAddress format */ 338#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 339#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 340#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 341#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 342 343#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 344#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 345#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 346 347 348/* SAS Device PageAddress format */ 349#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 350#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 351#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 352 353#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 354 355 356/* SAS PHY PageAddress format */ 357#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 358#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 359#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 360 361#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 362#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 363 364 365/* SAS Port PageAddress format */ 366#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 367#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 368#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 369 370#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 371 372 373/* SAS Enclosure PageAddress format */ 374#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 375#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 376#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 377 378#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 379 380 381/* RAID Configuration PageAddress format */ 382#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 383#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 384#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 385#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 386 387#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 388 389 390/* Driver Persistent Mapping PageAddress format */ 391#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 392#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 393 394#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 395#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 396#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 397 398 399/* Ethernet PageAddress format */ 400#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 401#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 402 403#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 404 405 406/**************************************************************************** 407* Configuration messages 408****************************************************************************/ 409 410/* Configuration Request Message */ 411typedef struct _MPI2_CONFIG_REQUEST 412{ 413 U8 Action; /* 0x00 */ 414 U8 SGLFlags; /* 0x01 */ 415 U8 ChainOffset; /* 0x02 */ 416 U8 Function; /* 0x03 */ 417 U16 ExtPageLength; /* 0x04 */ 418 U8 ExtPageType; /* 0x06 */ 419 U8 MsgFlags; /* 0x07 */ 420 U8 VP_ID; /* 0x08 */ 421 U8 VF_ID; /* 0x09 */ 422 U16 Reserved1; /* 0x0A */ 423 U8 Reserved2; /* 0x0C */ 424 U8 ProxyVF_ID; /* 0x0D */ 425 U16 Reserved4; /* 0x0E */ 426 U32 Reserved3; /* 0x10 */ 427 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 428 U32 PageAddress; /* 0x18 */ 429 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 430} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 431 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 432 433/* values for the Action field */ 434#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 435#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 436#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 437#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 438#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 439#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 440#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 441#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 442 443/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 444 445 446/* Config Reply Message */ 447typedef struct _MPI2_CONFIG_REPLY 448{ 449 U8 Action; /* 0x00 */ 450 U8 SGLFlags; /* 0x01 */ 451 U8 MsgLength; /* 0x02 */ 452 U8 Function; /* 0x03 */ 453 U16 ExtPageLength; /* 0x04 */ 454 U8 ExtPageType; /* 0x06 */ 455 U8 MsgFlags; /* 0x07 */ 456 U8 VP_ID; /* 0x08 */ 457 U8 VF_ID; /* 0x09 */ 458 U16 Reserved1; /* 0x0A */ 459 U16 Reserved2; /* 0x0C */ 460 U16 IOCStatus; /* 0x0E */ 461 U32 IOCLogInfo; /* 0x10 */ 462 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 463} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 464 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 465 466 467 468/***************************************************************************** 469* 470* C o n f i g u r a t i o n P a g e s 471* 472*****************************************************************************/ 473 474/**************************************************************************** 475* Manufacturing Config pages 476****************************************************************************/ 477 478#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 479 480/* MPI v2.0 SAS products */ 481#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 482#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 483#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 484#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 485#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 486#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 487#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 488 489#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 490 491#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 492#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 493#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 494#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 495#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 496#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 497#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 498#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 499#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 500 501/* MPI v2.5 SAS products */ 502#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 503#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 504#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 505#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 506#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 507#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 508 509/* MPI v2.6 SAS Products */ 510#define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 511#define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 512#define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 513#define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 514#define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 515#define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 516#define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 517#define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 518#define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 519#define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 520 521/* Manufacturing Page 0 */ 522 523typedef struct _MPI2_CONFIG_PAGE_MAN_0 524{ 525 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 526 U8 ChipName[16]; /* 0x04 */ 527 U8 ChipRevision[8]; /* 0x14 */ 528 U8 BoardName[16]; /* 0x1C */ 529 U8 BoardAssembly[16]; /* 0x2C */ 530 U8 BoardTracerNumber[16]; /* 0x3C */ 531} MPI2_CONFIG_PAGE_MAN_0, 532 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 533 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 534 535#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 536 537 538/* Manufacturing Page 1 */ 539 540typedef struct _MPI2_CONFIG_PAGE_MAN_1 541{ 542 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 543 U8 VPD[256]; /* 0x04 */ 544} MPI2_CONFIG_PAGE_MAN_1, 545 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 546 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 547 548#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 549 550 551typedef struct _MPI2_CHIP_REVISION_ID 552{ 553 U16 DeviceID; /* 0x00 */ 554 U8 PCIRevisionID; /* 0x02 */ 555 U8 Reserved; /* 0x03 */ 556} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 557 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 558 559 560/* Manufacturing Page 2 */ 561 562/* 563 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 564 * one and check Header.PageLength at runtime. 565 */ 566#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 567#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 568#endif 569 570typedef struct _MPI2_CONFIG_PAGE_MAN_2 571{ 572 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 573 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 574 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 575} MPI2_CONFIG_PAGE_MAN_2, 576 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 577 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 578 579#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 580 581 582/* Manufacturing Page 3 */ 583 584/* 585 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 586 * one and check Header.PageLength at runtime. 587 */ 588#ifndef MPI2_MAN_PAGE_3_INFO_WORDS 589#define MPI2_MAN_PAGE_3_INFO_WORDS (1) 590#endif 591 592typedef struct _MPI2_CONFIG_PAGE_MAN_3 593{ 594 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 595 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 596 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 597} MPI2_CONFIG_PAGE_MAN_3, 598 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 599 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 600 601#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 602 603 604/* Manufacturing Page 4 */ 605 606typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 607{ 608 U8 PowerSaveFlags; /* 0x00 */ 609 U8 InternalOperationsSleepTime; /* 0x01 */ 610 U8 InternalOperationsRunTime; /* 0x02 */ 611 U8 HostIdleTime; /* 0x03 */ 612} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 613 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 614 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 615 616/* defines for the PowerSaveFlags field */ 617#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 618#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 619#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 620#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 621 622typedef struct _MPI2_CONFIG_PAGE_MAN_4 623{ 624 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 625 U32 Reserved1; /* 0x04 */ 626 U32 Flags; /* 0x08 */ 627 U8 InquirySize; /* 0x0C */ 628 U8 Reserved2; /* 0x0D */ 629 U16 Reserved3; /* 0x0E */ 630 U8 InquiryData[56]; /* 0x10 */ 631 U32 RAID0VolumeSettings; /* 0x48 */ 632 U32 RAID1EVolumeSettings; /* 0x4C */ 633 U32 RAID1VolumeSettings; /* 0x50 */ 634 U32 RAID10VolumeSettings; /* 0x54 */ 635 U32 Reserved4; /* 0x58 */ 636 U32 Reserved5; /* 0x5C */ 637 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 638 U8 MaxOCEDisks; /* 0x64 */ 639 U8 ResyncRate; /* 0x65 */ 640 U16 DataScrubDuration; /* 0x66 */ 641 U8 MaxHotSpares; /* 0x68 */ 642 U8 MaxPhysDisksPerVol; /* 0x69 */ 643 U8 MaxPhysDisks; /* 0x6A */ 644 U8 MaxVolumes; /* 0x6B */ 645} MPI2_CONFIG_PAGE_MAN_4, 646 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 647 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 648 649#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 650 651/* Manufacturing Page 4 Flags field */ 652#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 653#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 654 655#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 656#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 657#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 658 659#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 660#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 661#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 662#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 663#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 664 665#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 666#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 667#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 668#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 669 670#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 671#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 672#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 673#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 674#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 675#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 676#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 677#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 678 679 680/* Manufacturing Page 5 */ 681 682/* 683 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 684 * one and check the value returned for NumPhys at runtime. 685 */ 686#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 687#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 688#endif 689 690typedef struct _MPI2_MANUFACTURING5_ENTRY 691{ 692 U64 WWID; /* 0x00 */ 693 U64 DeviceName; /* 0x08 */ 694} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 695 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 696 697typedef struct _MPI2_CONFIG_PAGE_MAN_5 698{ 699 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 700 U8 NumPhys; /* 0x04 */ 701 U8 Reserved1; /* 0x05 */ 702 U16 Reserved2; /* 0x06 */ 703 U32 Reserved3; /* 0x08 */ 704 U32 Reserved4; /* 0x0C */ 705 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 706} MPI2_CONFIG_PAGE_MAN_5, 707 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 708 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 709 710#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 711 712 713/* Manufacturing Page 6 */ 714 715typedef struct _MPI2_CONFIG_PAGE_MAN_6 716{ 717 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 718 U32 ProductSpecificInfo;/* 0x04 */ 719} MPI2_CONFIG_PAGE_MAN_6, 720 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 721 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 722 723#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 724 725 726/* Manufacturing Page 7 */ 727 728typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 729{ 730 U32 Pinout; /* 0x00 */ 731 U8 Connector[16]; /* 0x04 */ 732 U8 Location; /* 0x14 */ 733 U8 ReceptacleID; /* 0x15 */ 734 U16 Slot; /* 0x16 */ 735 U32 Reserved2; /* 0x18 */ 736} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 737 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 738 739/* defines for the Pinout field */ 740#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 741#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 742 743#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 744#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 745#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 746#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 747#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 748#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 749#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 750#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 751#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 752#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 753#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 754#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 755#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 756#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 757#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 758 759/* defines for the Location field */ 760#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 761#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 762#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 763#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 764#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 765#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 766#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 767 768/* 769 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 770 * one and check the value returned for NumPhys at runtime. 771 */ 772#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 773#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 774#endif 775 776typedef struct _MPI2_CONFIG_PAGE_MAN_7 777{ 778 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 779 U32 Reserved1; /* 0x04 */ 780 U32 Reserved2; /* 0x08 */ 781 U32 Flags; /* 0x0C */ 782 U8 EnclosureName[16]; /* 0x10 */ 783 U8 NumPhys; /* 0x20 */ 784 U8 Reserved3; /* 0x21 */ 785 U16 Reserved4; /* 0x22 */ 786 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 787} MPI2_CONFIG_PAGE_MAN_7, 788 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 789 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 790 791#define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 792 793/* defines for the Flags field */ 794#define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 795#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 796#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 797 798 799/* 800 * Generic structure to use for product-specific manufacturing pages 801 * (currently Manufacturing Page 8 through Manufacturing Page 31). 802 */ 803 804typedef struct _MPI2_CONFIG_PAGE_MAN_PS 805{ 806 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 807 U32 ProductSpecificInfo;/* 0x04 */ 808} MPI2_CONFIG_PAGE_MAN_PS, 809 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 810 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 811 812#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 813#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 814#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 815#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 816#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 817#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 818#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 819#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 820#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 821#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 822#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 823#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 824#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 825#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 826#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 827#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 828#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 829#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 830#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 831#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 832#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 833#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 834#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 835#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 836 837 838/**************************************************************************** 839* IO Unit Config Pages 840****************************************************************************/ 841 842/* IO Unit Page 0 */ 843 844typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 845{ 846 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 847 U64 UniqueValue; /* 0x04 */ 848 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 849 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 850} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 851 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 852 853#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 854 855 856/* IO Unit Page 1 */ 857 858typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 859{ 860 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 861 U32 Flags; /* 0x04 */ 862} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 863 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 864 865#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 866 867/* IO Unit Page 1 Flags defines */ 868#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 869#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 870#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 871#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 872#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 873#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 874#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 875#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 876#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 877#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 878#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 879#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 880#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 881 882 883/* IO Unit Page 3 */ 884 885/* 886 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 887 * one and check the value returned for GPIOCount at runtime. 888 */ 889#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 890#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 891#endif 892 893typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 894{ 895 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 896 U8 GPIOCount; /* 0x04 */ 897 U8 Reserved1; /* 0x05 */ 898 U16 Reserved2; /* 0x06 */ 899 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 900} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 901 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 902 903#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 904 905/* defines for IO Unit Page 3 GPIOVal field */ 906#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 907#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 908#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 909#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 910 911 912/* IO Unit Page 5 */ 913 914/* 915 * Upper layer code (drivers, utilities, etc.) should leave this define set to 916 * one and check the value returned for NumDmaEngines at runtime. 917 */ 918#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 919#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 920#endif 921 922typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 923{ 924 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 925 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 926 U64 RaidAcceleratorBufferSize; /* 0x0C */ 927 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 928 U8 RAControlSize; /* 0x1C */ 929 U8 NumDmaEngines; /* 0x1D */ 930 U8 RAMinControlSize; /* 0x1E */ 931 U8 RAMaxControlSize; /* 0x1F */ 932 U32 Reserved1; /* 0x20 */ 933 U32 Reserved2; /* 0x24 */ 934 U32 Reserved3; /* 0x28 */ 935 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 936} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 937 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 938 939#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 940 941/* defines for IO Unit Page 5 DmaEngineCapabilities field */ 942#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 943#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 944 945#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 946#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 947#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 948#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 949 950 951/* IO Unit Page 6 */ 952 953typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 954{ 955 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 956 U16 Flags; /* 0x04 */ 957 U8 RAHostControlSize; /* 0x06 */ 958 U8 Reserved0; /* 0x07 */ 959 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 960 U32 Reserved1; /* 0x10 */ 961 U32 Reserved2; /* 0x14 */ 962 U32 Reserved3; /* 0x18 */ 963} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 964 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 965 966#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 967 968/* defines for IO Unit Page 6 Flags field */ 969#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 970 971 972/* IO Unit Page 7 */ 973 974typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 975{ 976 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 977 U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */ 978 U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */ 979 U8 PCIeWidth; /* 0x06 */ 980 U8 PCIeSpeed; /* 0x07 */ 981 U32 ProcessorState; /* 0x08 */ 982 U32 PowerManagementCapabilities; /* 0x0C */ 983 U16 IOCTemperature; /* 0x10 */ 984 U8 IOCTemperatureUnits; /* 0x12 */ 985 U8 IOCSpeed; /* 0x13 */ 986 U16 BoardTemperature; /* 0x14 */ 987 U8 BoardTemperatureUnits; /* 0x16 */ 988 U8 Reserved3; /* 0x17 */ 989 U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ 990 U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ 991 U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ 992 U8 Reserved6; /* 0x21 */ 993 U16 Reserved7; /* 0x22 */ 994 U32 Reserved8; /* 0x24 */ 995} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 996 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 997 998#define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 999 1000/* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1001#define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1002#define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1003#define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1004#define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1005#define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1006 1007#define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1008#define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1009#define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1010#define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1011#define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1012#define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1013 1014 1015/* defines for IO Unit Page 7 PCIeWidth field */ 1016#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1017#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1018#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1019#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1020 1021/* defines for IO Unit Page 7 PCIeSpeed field */ 1022#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1023#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1024#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1025 1026/* defines for IO Unit Page 7 ProcessorState field */ 1027#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1028#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1029 1030#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1031#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1032#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1033 1034/* defines for IO Unit Page 7 PowerManagementCapabilities field */ 1035#define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1036#define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1037#define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1038#define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1039#define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1040#define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1041#define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1042#define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1043#define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1044#define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1045#define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1046#define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1047#define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1048#define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1049#define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1050#define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */ 1051#define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */ 1052#define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */ 1053#define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */ 1054 1055/* obsolete names for the PowerManagementCapabilities bits (above) */ 1056#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1057#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1058#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1059#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 1060#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 1061 1062 1063/* defines for IO Unit Page 7 IOCTemperatureUnits field */ 1064#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1065#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1066#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1067 1068/* defines for IO Unit Page 7 IOCSpeed field */ 1069#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1070#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1071#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1072#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1073 1074/* defines for IO Unit Page 7 BoardTemperatureUnits field */ 1075#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1076#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1077#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1078 1079/* defines for IO Unit Page 7 Flags field */ 1080#define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1081 1082/* IO Unit Page 8 */ 1083 1084#define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1085 1086typedef struct _MPI2_IOUNIT8_SENSOR 1087{ 1088 U16 Flags; /* 0x00 */ 1089 U16 Reserved1; /* 0x02 */ 1090 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 1091 U32 Reserved2; /* 0x0C */ 1092 U32 Reserved3; /* 0x10 */ 1093 U32 Reserved4; /* 0x14 */ 1094} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 1095 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 1096 1097/* defines for IO Unit Page 8 Sensor Flags field */ 1098#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1099#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1100#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1101#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1102 1103/* 1104 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1105 * one and check the value returned for NumSensors at runtime. 1106 */ 1107#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1108#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1109#endif 1110 1111typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 1112{ 1113 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1114 U32 Reserved1; /* 0x04 */ 1115 U32 Reserved2; /* 0x08 */ 1116 U8 NumSensors; /* 0x0C */ 1117 U8 PollingInterval; /* 0x0D */ 1118 U16 Reserved3; /* 0x0E */ 1119 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 1120} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1121 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 1122 1123#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1124 1125 1126/* IO Unit Page 9 */ 1127 1128typedef struct _MPI2_IOUNIT9_SENSOR 1129{ 1130 U16 CurrentTemperature; /* 0x00 */ 1131 U16 Reserved1; /* 0x02 */ 1132 U8 Flags; /* 0x04 */ 1133 U8 Reserved2; /* 0x05 */ 1134 U16 Reserved3; /* 0x06 */ 1135 U32 Reserved4; /* 0x08 */ 1136 U32 Reserved5; /* 0x0C */ 1137} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1138 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1139 1140/* defines for IO Unit Page 9 Sensor Flags field */ 1141#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1142 1143/* 1144 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1145 * one and check the value returned for NumSensors at runtime. 1146 */ 1147#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1148#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1149#endif 1150 1151typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 1152{ 1153 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1154 U32 Reserved1; /* 0x04 */ 1155 U32 Reserved2; /* 0x08 */ 1156 U8 NumSensors; /* 0x0C */ 1157 U8 Reserved4; /* 0x0D */ 1158 U16 Reserved3; /* 0x0E */ 1159 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1160} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1161 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1162 1163#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1164 1165 1166/* IO Unit Page 10 */ 1167 1168typedef struct _MPI2_IOUNIT10_FUNCTION 1169{ 1170 U8 CreditPercent; /* 0x00 */ 1171 U8 Reserved1; /* 0x01 */ 1172 U16 Reserved2; /* 0x02 */ 1173} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1174 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1175 1176/* 1177 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1178 * one and check the value returned for NumFunctions at runtime. 1179 */ 1180#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1181#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1182#endif 1183 1184typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 1185{ 1186 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1187 U8 NumFunctions; /* 0x04 */ 1188 U8 Reserved1; /* 0x05 */ 1189 U16 Reserved2; /* 0x06 */ 1190 U32 Reserved3; /* 0x08 */ 1191 U32 Reserved4; /* 0x0C */ 1192 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ 1193} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1194 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1195 1196#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1197 1198 1199/* IO Unit Page 11 (for MPI v2.6 and later) */ 1200 1201typedef struct _MPI26_IOUNIT11_SPINUP_GROUP 1202{ 1203 U8 MaxTargetSpinup; /* 0x00 */ 1204 U8 SpinupDelay; /* 0x01 */ 1205 U8 SpinupFlags; /* 0x02 */ 1206 U8 Reserved1; /* 0x03 */ 1207} MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1208 Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; 1209 1210/* defines for IO Unit Page 11 SpinupFlags */ 1211#define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1212 1213 1214/* 1215 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1216 * four and check the value returned for NumPhys at runtime. 1217 */ 1218#ifndef MPI26_IOUNITPAGE11_PHY_MAX 1219#define MPI26_IOUNITPAGE11_PHY_MAX (4) 1220#endif 1221 1222typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 1223{ 1224 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1225 U32 Reserved1; /* 0x04 */ 1226 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1227 U32 Reserved2; /* 0x18 */ 1228 U32 Reserved3; /* 0x1C */ 1229 U32 Reserved4; /* 0x20 */ 1230 U8 BootDeviceWaitTime; /* 0x24 */ 1231 U8 Reserved5; /* 0x25 */ 1232 U16 Reserved6; /* 0x26 */ 1233 U8 NumPhys; /* 0x28 */ 1234 U8 PEInitialSpinupDelay; /* 0x29 */ 1235 U8 PEReplyDelay; /* 0x2A */ 1236 U8 Flags; /* 0x2B */ 1237 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ 1238} MPI26_CONFIG_PAGE_IO_UNIT_11, 1239 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1240 Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; 1241 1242#define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1243 1244/* defines for Flags field */ 1245#define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1246 1247/* defines for PHY field */ 1248#define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1249 1250 1251 1252 1253 1254 1255/**************************************************************************** 1256* IOC Config Pages 1257****************************************************************************/ 1258 1259/* IOC Page 0 */ 1260 1261typedef struct _MPI2_CONFIG_PAGE_IOC_0 1262{ 1263 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1264 U32 Reserved1; /* 0x04 */ 1265 U32 Reserved2; /* 0x08 */ 1266 U16 VendorID; /* 0x0C */ 1267 U16 DeviceID; /* 0x0E */ 1268 U8 RevisionID; /* 0x10 */ 1269 U8 Reserved3; /* 0x11 */ 1270 U16 Reserved4; /* 0x12 */ 1271 U32 ClassCode; /* 0x14 */ 1272 U16 SubsystemVendorID; /* 0x18 */ 1273 U16 SubsystemID; /* 0x1A */ 1274} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1275 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1276 1277#define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1278 1279 1280/* IOC Page 1 */ 1281 1282typedef struct _MPI2_CONFIG_PAGE_IOC_1 1283{ 1284 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1285 U32 Flags; /* 0x04 */ 1286 U32 CoalescingTimeout; /* 0x08 */ 1287 U8 CoalescingDepth; /* 0x0C */ 1288 U8 PCISlotNum; /* 0x0D */ 1289 U8 PCIBusNum; /* 0x0E */ 1290 U8 PCIDomainSegment; /* 0x0F */ 1291 U32 Reserved1; /* 0x10 */ 1292 U32 Reserved2; /* 0x14 */ 1293} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1294 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1295 1296#define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1297 1298/* defines for IOC Page 1 Flags field */ 1299#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1300 1301#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1302#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1303#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1304 1305/* IOC Page 6 */ 1306 1307typedef struct _MPI2_CONFIG_PAGE_IOC_6 1308{ 1309 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1310 U32 CapabilitiesFlags; /* 0x04 */ 1311 U8 MaxDrivesRAID0; /* 0x08 */ 1312 U8 MaxDrivesRAID1; /* 0x09 */ 1313 U8 MaxDrivesRAID1E; /* 0x0A */ 1314 U8 MaxDrivesRAID10; /* 0x0B */ 1315 U8 MinDrivesRAID0; /* 0x0C */ 1316 U8 MinDrivesRAID1; /* 0x0D */ 1317 U8 MinDrivesRAID1E; /* 0x0E */ 1318 U8 MinDrivesRAID10; /* 0x0F */ 1319 U32 Reserved1; /* 0x10 */ 1320 U8 MaxGlobalHotSpares; /* 0x14 */ 1321 U8 MaxPhysDisks; /* 0x15 */ 1322 U8 MaxVolumes; /* 0x16 */ 1323 U8 MaxConfigs; /* 0x17 */ 1324 U8 MaxOCEDisks; /* 0x18 */ 1325 U8 Reserved2; /* 0x19 */ 1326 U16 Reserved3; /* 0x1A */ 1327 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1328 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1329 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1330 U32 Reserved4; /* 0x28 */ 1331 U32 Reserved5; /* 0x2C */ 1332 U16 DefaultMetadataSize; /* 0x30 */ 1333 U16 Reserved6; /* 0x32 */ 1334 U16 MaxBadBlockTableEntries; /* 0x34 */ 1335 U16 Reserved7; /* 0x36 */ 1336 U32 IRNvsramVersion; /* 0x38 */ 1337} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1338 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1339 1340#define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1341 1342/* defines for IOC Page 6 CapabilitiesFlags */ 1343#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1344#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1345#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1346#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1347#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1348#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1349 1350 1351/* IOC Page 7 */ 1352 1353#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1354 1355typedef struct _MPI2_CONFIG_PAGE_IOC_7 1356{ 1357 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1358 U32 Reserved1; /* 0x04 */ 1359 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1360 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1361 U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1362 U32 Reserved3; /* 0x1C */ 1363} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1364 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1365 1366#define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1367 1368 1369/* IOC Page 8 */ 1370 1371typedef struct _MPI2_CONFIG_PAGE_IOC_8 1372{ 1373 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1374 U8 NumDevsPerEnclosure; /* 0x04 */ 1375 U8 Reserved1; /* 0x05 */ 1376 U16 Reserved2; /* 0x06 */ 1377 U16 MaxPersistentEntries; /* 0x08 */ 1378 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1379 U16 Flags; /* 0x0C */ 1380 U16 Reserved3; /* 0x0E */ 1381 U16 IRVolumeMappingFlags; /* 0x10 */ 1382 U16 Reserved4; /* 0x12 */ 1383 U32 Reserved5; /* 0x14 */ 1384} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1385 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1386 1387#define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1388 1389/* defines for IOC Page 8 Flags field */ 1390#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1391#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1392 1393#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1394#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1395#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1396 1397#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1398#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1399 1400/* defines for IOC Page 8 IRVolumeMappingFlags */ 1401#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1402#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1403#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1404 1405 1406/**************************************************************************** 1407* BIOS Config Pages 1408****************************************************************************/ 1409 1410/* BIOS Page 1 */ 1411 1412typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1413{ 1414 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1415 U32 BiosOptions; /* 0x04 */ 1416 U32 IOCSettings; /* 0x08 */ 1417 U8 SSUTimeout; /* 0x0C */ 1418 U8 Reserved1; /* 0x0D */ 1419 U16 Reserved2; /* 0x0E */ 1420 U32 DeviceSettings; /* 0x10 */ 1421 U16 NumberOfDevices; /* 0x14 */ 1422 U16 UEFIVersion; /* 0x16 */ 1423 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1424 U16 IOTimeoutSequential; /* 0x1A */ 1425 U16 IOTimeoutOther; /* 0x1C */ 1426 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1427} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1428 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1429 1430#define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1431 1432/* values for BIOS Page 1 BiosOptions field */ 1433#define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1434#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1435 1436#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1437#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1438#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1439#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1440#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1441#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1442 1443#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1444 1445#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1446#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1447#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1448#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1449#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1450 1451#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1452#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1453 1454#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1455#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1456#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1457#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1458 1459#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1460 1461/* values for BIOS Page 1 IOCSettings field */ 1462#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1463#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1464#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1465 1466#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1467#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1468#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1469#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1470 1471#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1472#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1473#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1474#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1475#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1476 1477#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1478 1479/* values for BIOS Page 1 DeviceSettings field */ 1480#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1481#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1482#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1483#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1484#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1485 1486/* defines for BIOS Page 1 UEFIVersion field */ 1487#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1488#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1489#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1490#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1491 1492 1493 1494/* BIOS Page 2 */ 1495 1496typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1497{ 1498 U32 Reserved1; /* 0x00 */ 1499 U32 Reserved2; /* 0x04 */ 1500 U32 Reserved3; /* 0x08 */ 1501 U32 Reserved4; /* 0x0C */ 1502 U32 Reserved5; /* 0x10 */ 1503 U32 Reserved6; /* 0x14 */ 1504} MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1505 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1506 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1507 1508typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1509{ 1510 U64 SASAddress; /* 0x00 */ 1511 U8 LUN[8]; /* 0x08 */ 1512 U32 Reserved1; /* 0x10 */ 1513 U32 Reserved2; /* 0x14 */ 1514} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1515 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1516 1517typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1518{ 1519 U64 EnclosureLogicalID; /* 0x00 */ 1520 U32 Reserved1; /* 0x08 */ 1521 U32 Reserved2; /* 0x0C */ 1522 U16 SlotNumber; /* 0x10 */ 1523 U16 Reserved3; /* 0x12 */ 1524 U32 Reserved4; /* 0x14 */ 1525} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1526 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1527 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1528 1529typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1530{ 1531 U64 DeviceName; /* 0x00 */ 1532 U8 LUN[8]; /* 0x08 */ 1533 U32 Reserved1; /* 0x10 */ 1534 U32 Reserved2; /* 0x14 */ 1535} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1536 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1537 1538typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1539{ 1540 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1541 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1542 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1543 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1544} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1545 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1546 1547typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1548{ 1549 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1550 U32 Reserved1; /* 0x04 */ 1551 U32 Reserved2; /* 0x08 */ 1552 U32 Reserved3; /* 0x0C */ 1553 U32 Reserved4; /* 0x10 */ 1554 U32 Reserved5; /* 0x14 */ 1555 U32 Reserved6; /* 0x18 */ 1556 U8 ReqBootDeviceForm; /* 0x1C */ 1557 U8 Reserved7; /* 0x1D */ 1558 U16 Reserved8; /* 0x1E */ 1559 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1560 U8 ReqAltBootDeviceForm; /* 0x38 */ 1561 U8 Reserved9; /* 0x39 */ 1562 U16 Reserved10; /* 0x3A */ 1563 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1564 U8 CurrentBootDeviceForm; /* 0x58 */ 1565 U8 Reserved11; /* 0x59 */ 1566 U16 Reserved12; /* 0x5A */ 1567 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1568} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1569 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1570 1571#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1572 1573/* values for BIOS Page 2 BootDeviceForm fields */ 1574#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1575#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1576#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1577#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1578#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1579 1580 1581/* BIOS Page 3 */ 1582 1583#define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1584 1585typedef struct _MPI2_ADAPTER_INFO 1586{ 1587 U8 PciBusNumber; /* 0x00 */ 1588 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1589 U16 AdapterFlags; /* 0x02 */ 1590} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1591 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1592 1593#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1594#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1595 1596typedef struct _MPI2_ADAPTER_ORDER_AUX 1597{ 1598 U64 WWID; /* 0x00 */ 1599 U32 Reserved1; /* 0x08 */ 1600 U32 Reserved2; /* 0x0C */ 1601} MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, 1602 Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; 1603 1604typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1605{ 1606 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1607 U32 GlobalFlags; /* 0x04 */ 1608 U32 BiosVersion; /* 0x08 */ 1609 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ 1610 U32 Reserved1; /* 0x1C */ 1611 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ 1612} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1613 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1614 1615#define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1616 1617/* values for BIOS Page 3 GlobalFlags */ 1618#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1619#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1620#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1621 1622#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1623#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1624#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1625#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1626 1627 1628/* BIOS Page 4 */ 1629 1630/* 1631 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1632 * one and check the value returned for NumPhys at runtime. 1633 */ 1634#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1635#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1636#endif 1637 1638typedef struct _MPI2_BIOS4_ENTRY 1639{ 1640 U64 ReassignmentWWID; /* 0x00 */ 1641 U64 ReassignmentDeviceName; /* 0x08 */ 1642} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1643 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1644 1645typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1646{ 1647 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1648 U8 NumPhys; /* 0x04 */ 1649 U8 Reserved1; /* 0x05 */ 1650 U16 Reserved2; /* 0x06 */ 1651 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1652} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1653 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1654 1655#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1656 1657 1658/**************************************************************************** 1659* RAID Volume Config Pages 1660****************************************************************************/ 1661 1662/* RAID Volume Page 0 */ 1663 1664typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1665{ 1666 U8 RAIDSetNum; /* 0x00 */ 1667 U8 PhysDiskMap; /* 0x01 */ 1668 U8 PhysDiskNum; /* 0x02 */ 1669 U8 Reserved; /* 0x03 */ 1670} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1671 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1672 1673/* defines for the PhysDiskMap field */ 1674#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1675#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1676 1677typedef struct _MPI2_RAIDVOL0_SETTINGS 1678{ 1679 U16 Settings; /* 0x00 */ 1680 U8 HotSparePool; /* 0x01 */ 1681 U8 Reserved; /* 0x02 */ 1682} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1683 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1684 1685/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1686#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1687#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1688#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1689#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1690#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1691#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1692#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1693#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1694 1695/* RAID Volume Page 0 VolumeSettings defines */ 1696#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1697#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1698 1699#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1700#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1701#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1702#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1703 1704/* 1705 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1706 * one and check the value returned for NumPhysDisks at runtime. 1707 */ 1708#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1709#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1710#endif 1711 1712typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1713{ 1714 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1715 U16 DevHandle; /* 0x04 */ 1716 U8 VolumeState; /* 0x06 */ 1717 U8 VolumeType; /* 0x07 */ 1718 U32 VolumeStatusFlags; /* 0x08 */ 1719 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1720 U64 MaxLBA; /* 0x10 */ 1721 U32 StripeSize; /* 0x18 */ 1722 U16 BlockSize; /* 0x1C */ 1723 U16 Reserved1; /* 0x1E */ 1724 U8 SupportedPhysDisks; /* 0x20 */ 1725 U8 ResyncRate; /* 0x21 */ 1726 U16 DataScrubDuration; /* 0x22 */ 1727 U8 NumPhysDisks; /* 0x24 */ 1728 U8 Reserved2; /* 0x25 */ 1729 U8 Reserved3; /* 0x26 */ 1730 U8 InactiveStatus; /* 0x27 */ 1731 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1732} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1733 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1734 1735#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1736 1737/* values for RAID VolumeState */ 1738#define MPI2_RAID_VOL_STATE_MISSING (0x00) 1739#define MPI2_RAID_VOL_STATE_FAILED (0x01) 1740#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1741#define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1742#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1743#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1744 1745/* values for RAID VolumeType */ 1746#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1747#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1748#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1749#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1750#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1751 1752/* values for RAID Volume Page 0 VolumeStatusFlags field */ 1753#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1754#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1755#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1756#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1757#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1758#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1759#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1760#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1761#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1762#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1763#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1764#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1765#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1766#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1767#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1768#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1769#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1770#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1771#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1772 1773/* values for RAID Volume Page 0 SupportedPhysDisks field */ 1774#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1775#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1776#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1777#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1778 1779/* values for RAID Volume Page 0 InactiveStatus field */ 1780#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1781#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1782#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1783#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1784#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1785#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1786#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1787 1788 1789/* RAID Volume Page 1 */ 1790 1791typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1792{ 1793 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1794 U16 DevHandle; /* 0x04 */ 1795 U16 Reserved0; /* 0x06 */ 1796 U8 GUID[24]; /* 0x08 */ 1797 U8 Name[16]; /* 0x20 */ 1798 U64 WWID; /* 0x30 */ 1799 U32 Reserved1; /* 0x38 */ 1800 U32 Reserved2; /* 0x3C */ 1801} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1802 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1803 1804#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1805 1806 1807/**************************************************************************** 1808* RAID Physical Disk Config Pages 1809****************************************************************************/ 1810 1811/* RAID Physical Disk Page 0 */ 1812 1813typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1814{ 1815 U16 Reserved1; /* 0x00 */ 1816 U8 HotSparePool; /* 0x02 */ 1817 U8 Reserved2; /* 0x03 */ 1818} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1819 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1820 1821/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1822 1823typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1824{ 1825 U8 VendorID[8]; /* 0x00 */ 1826 U8 ProductID[16]; /* 0x08 */ 1827 U8 ProductRevLevel[4]; /* 0x18 */ 1828 U8 SerialNum[32]; /* 0x1C */ 1829} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1830 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1831 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1832 1833typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1834{ 1835 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1836 U16 DevHandle; /* 0x04 */ 1837 U8 Reserved1; /* 0x06 */ 1838 U8 PhysDiskNum; /* 0x07 */ 1839 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1840 U32 Reserved2; /* 0x0C */ 1841 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1842 U32 Reserved3; /* 0x4C */ 1843 U8 PhysDiskState; /* 0x50 */ 1844 U8 OfflineReason; /* 0x51 */ 1845 U8 IncompatibleReason; /* 0x52 */ 1846 U8 PhysDiskAttributes; /* 0x53 */ 1847 U32 PhysDiskStatusFlags; /* 0x54 */ 1848 U64 DeviceMaxLBA; /* 0x58 */ 1849 U64 HostMaxLBA; /* 0x60 */ 1850 U64 CoercedMaxLBA; /* 0x68 */ 1851 U16 BlockSize; /* 0x70 */ 1852 U16 Reserved5; /* 0x72 */ 1853 U32 Reserved6; /* 0x74 */ 1854} MPI2_CONFIG_PAGE_RD_PDISK_0, 1855 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1856 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1857 1858#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1859 1860/* PhysDiskState defines */ 1861#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1862#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1863#define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1864#define MPI2_RAID_PD_STATE_ONLINE (0x03) 1865#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1866#define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1867#define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1868#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1869 1870/* OfflineReason defines */ 1871#define MPI2_PHYSDISK0_ONLINE (0x00) 1872#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1873#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1874#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1875#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1876#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1877#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1878 1879/* IncompatibleReason defines */ 1880#define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1881#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1882#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1883#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1884#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1885#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1886#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1887#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1888 1889/* PhysDiskAttributes defines */ 1890#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1891#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1892#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1893 1894#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1895#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1896#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1897 1898/* PhysDiskStatusFlags defines */ 1899#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1900#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1901#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1902#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1903#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1904#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1905#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1906#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1907 1908 1909/* RAID Physical Disk Page 1 */ 1910 1911/* 1912 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1913 * one and check the value returned for NumPhysDiskPaths at runtime. 1914 */ 1915#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1916#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1917#endif 1918 1919typedef struct _MPI2_RAIDPHYSDISK1_PATH 1920{ 1921 U16 DevHandle; /* 0x00 */ 1922 U16 Reserved1; /* 0x02 */ 1923 U64 WWID; /* 0x04 */ 1924 U64 OwnerWWID; /* 0x0C */ 1925 U8 OwnerIdentifier; /* 0x14 */ 1926 U8 Reserved2; /* 0x15 */ 1927 U16 Flags; /* 0x16 */ 1928} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1929 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1930 1931/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1932#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1933#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1934#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1935 1936typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1937{ 1938 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1939 U8 NumPhysDiskPaths; /* 0x04 */ 1940 U8 PhysDiskNum; /* 0x05 */ 1941 U16 Reserved1; /* 0x06 */ 1942 U32 Reserved2; /* 0x08 */ 1943 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1944} MPI2_CONFIG_PAGE_RD_PDISK_1, 1945 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1946 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1947 1948#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1949 1950 1951/**************************************************************************** 1952* values for fields used by several types of SAS Config Pages 1953****************************************************************************/ 1954 1955/* values for NegotiatedLinkRates fields */ 1956#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1957#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1958#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1959/* link rates used for Negotiated Physical and Logical Link Rate */ 1960#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1961#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1962#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1963#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1964#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1965#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1966#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1967#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1968#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1969#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1970#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 1971 1972 1973/* values for AttachedPhyInfo fields */ 1974#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1975#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1976#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1977 1978#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1979#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1980#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1981#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1982#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1983#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1984#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1985#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1986#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1987#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1988 1989 1990/* values for PhyInfo fields */ 1991#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1992 1993#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1994#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1995#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1996#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1997#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1998 1999#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2000#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2001#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2002#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2003#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2004#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2005 2006#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2007#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2008#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2009#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2010#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2011#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2012#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2013#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2014#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2015#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2016 2017#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2018#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2019#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2020#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2021 2022#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2023#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2024 2025#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2026#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2027#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2028#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2029 2030 2031/* values for SAS ProgrammedLinkRate fields */ 2032#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2033#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2034#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2035#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2036#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2037#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2038#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2039#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2040#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2041#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2042#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2043#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2044 2045 2046/* values for SAS HwLinkRate fields */ 2047#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2048#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2049#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2050#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2051#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2052#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2053#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2054#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2055#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2056#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2057 2058 2059 2060/**************************************************************************** 2061* SAS IO Unit Config Pages 2062****************************************************************************/ 2063 2064/* SAS IO Unit Page 0 */ 2065 2066typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 2067{ 2068 U8 Port; /* 0x00 */ 2069 U8 PortFlags; /* 0x01 */ 2070 U8 PhyFlags; /* 0x02 */ 2071 U8 NegotiatedLinkRate; /* 0x03 */ 2072 U32 ControllerPhyDeviceInfo;/* 0x04 */ 2073 U16 AttachedDevHandle; /* 0x08 */ 2074 U16 ControllerDevHandle; /* 0x0A */ 2075 U32 DiscoveryStatus; /* 0x0C */ 2076 U32 Reserved; /* 0x10 */ 2077} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2078 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 2079 2080/* 2081 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2082 * one and check the value returned for NumPhys at runtime. 2083 */ 2084#ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2085#define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2086#endif 2087 2088typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 2089{ 2090 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2091 U32 Reserved1; /* 0x08 */ 2092 U8 NumPhys; /* 0x0C */ 2093 U8 Reserved2; /* 0x0D */ 2094 U16 Reserved3; /* 0x0E */ 2095 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 2096} MPI2_CONFIG_PAGE_SASIOUNIT_0, 2097 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2098 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 2099 2100#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2101 2102/* values for SAS IO Unit Page 0 PortFlags */ 2103#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2104#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2105 2106/* values for SAS IO Unit Page 0 PhyFlags */ 2107#define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2108#define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2109#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2110#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2111 2112/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2113 2114/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2115 2116/* values for SAS IO Unit Page 0 DiscoveryStatus */ 2117#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2118#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2119#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2120#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2121#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2122#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2123#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2124#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2125#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2126#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2127#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2128#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2129#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2130#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2131#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2132#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2133#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2134#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2135#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2136#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2137 2138 2139/* SAS IO Unit Page 1 */ 2140 2141typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 2142{ 2143 U8 Port; /* 0x00 */ 2144 U8 PortFlags; /* 0x01 */ 2145 U8 PhyFlags; /* 0x02 */ 2146 U8 MaxMinLinkRate; /* 0x03 */ 2147 U32 ControllerPhyDeviceInfo; /* 0x04 */ 2148 U16 MaxTargetPortConnectTime; /* 0x08 */ 2149 U16 Reserved1; /* 0x0A */ 2150} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2151 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 2152 2153/* 2154 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2155 * one and check the value returned for NumPhys at runtime. 2156 */ 2157#ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2158#define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2159#endif 2160 2161typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 2162{ 2163 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2164 U16 ControlFlags; /* 0x08 */ 2165 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2166 U16 AdditionalControlFlags; /* 0x0C */ 2167 U16 SASWideMaxQueueDepth; /* 0x0E */ 2168 U8 NumPhys; /* 0x10 */ 2169 U8 SATAMaxQDepth; /* 0x11 */ 2170 U8 ReportDeviceMissingDelay; /* 0x12 */ 2171 U8 IODeviceMissingDelay; /* 0x13 */ 2172 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 2173} MPI2_CONFIG_PAGE_SASIOUNIT_1, 2174 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2175 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 2176 2177#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2178 2179/* values for SAS IO Unit Page 1 ControlFlags */ 2180#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2181#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2182#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2183#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2184 2185#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2186#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2187#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2188#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2189#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2190 2191#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2192#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2193#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2194#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2195#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2196#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2197#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2198#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2199 2200/* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2201#define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2202#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2203#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2204#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2205#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2206#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2207#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2208#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2209#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2210 2211/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2212#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2213#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2214 2215/* values for SAS IO Unit Page 1 PortFlags */ 2216#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2217 2218/* values for SAS IO Unit Page 1 PhyFlags */ 2219#define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2220#define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2221#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2222#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2223 2224/* values for SAS IO Unit Page 1 MaxMinLinkRate */ 2225#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2226#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2227#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2228#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2229#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2230#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2231#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2232#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2233#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2234#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2235 2236/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2237 2238 2239/* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2240 2241typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2242{ 2243 U8 MaxTargetSpinup; /* 0x00 */ 2244 U8 SpinupDelay; /* 0x01 */ 2245 U8 SpinupFlags; /* 0x02 */ 2246 U8 Reserved1; /* 0x03 */ 2247} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2248 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2249 2250/* defines for SAS IO Unit Page 4 SpinupFlags */ 2251#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2252 2253 2254/* 2255 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2256 * one and check the value returned for NumPhys at runtime. 2257 */ 2258#ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2259#define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2260#endif 2261 2262typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2263{ 2264 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2265 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2266 U32 Reserved1; /* 0x18 */ 2267 U32 Reserved2; /* 0x1C */ 2268 U32 Reserved3; /* 0x20 */ 2269 U8 BootDeviceWaitTime; /* 0x24 */ 2270 U8 SATADeviceWaitTime; /* 0x25 */ 2271 U16 Reserved5; /* 0x26 */ 2272 U8 NumPhys; /* 0x28 */ 2273 U8 PEInitialSpinupDelay; /* 0x29 */ 2274 U8 PEReplyDelay; /* 0x2A */ 2275 U8 Flags; /* 0x2B */ 2276 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2277} MPI2_CONFIG_PAGE_SASIOUNIT_4, 2278 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2279 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2280 2281#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2282 2283/* defines for Flags field */ 2284#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2285 2286/* defines for PHY field */ 2287#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2288 2289 2290/* SAS IO Unit Page 5 */ 2291 2292typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2293{ 2294 U8 ControlFlags; /* 0x00 */ 2295 U8 PortWidthModGroup; /* 0x01 */ 2296 U16 InactivityTimerExponent; /* 0x02 */ 2297 U8 SATAPartialTimeout; /* 0x04 */ 2298 U8 Reserved2; /* 0x05 */ 2299 U8 SATASlumberTimeout; /* 0x06 */ 2300 U8 Reserved3; /* 0x07 */ 2301 U8 SASPartialTimeout; /* 0x08 */ 2302 U8 Reserved4; /* 0x09 */ 2303 U8 SASSlumberTimeout; /* 0x0A */ 2304 U8 Reserved5; /* 0x0B */ 2305} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2306 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2307 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2308 2309/* defines for ControlFlags field */ 2310#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2311#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2312#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2313#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2314 2315/* defines for PortWidthModeGroup field */ 2316#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2317 2318/* defines for InactivityTimerExponent field */ 2319#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2320#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2321#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2322#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2323#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2324#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2325#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2326#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2327 2328#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2329#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2330#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2331#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2332#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2333#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2334#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2335#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2336 2337/* 2338 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2339 * one and check the value returned for NumPhys at runtime. 2340 */ 2341#ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2342#define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2343#endif 2344 2345typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 2346{ 2347 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2348 U8 NumPhys; /* 0x08 */ 2349 U8 Reserved1; /* 0x09 */ 2350 U16 Reserved2; /* 0x0A */ 2351 U32 Reserved3; /* 0x0C */ 2352 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2353} MPI2_CONFIG_PAGE_SASIOUNIT_5, 2354 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2355 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2356 2357#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2358 2359 2360/* SAS IO Unit Page 6 */ 2361 2362typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2363{ 2364 U8 CurrentStatus; /* 0x00 */ 2365 U8 CurrentModulation; /* 0x01 */ 2366 U8 CurrentUtilization; /* 0x02 */ 2367 U8 Reserved1; /* 0x03 */ 2368 U32 Reserved2; /* 0x04 */ 2369} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2370 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2371 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2372 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2373 2374/* defines for CurrentStatus field */ 2375#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2376#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2377#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2378#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2379#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2380#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2381#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2382#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2383 2384/* defines for CurrentModulation field */ 2385#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2386#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2387#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2388#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2389 2390/* 2391 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2392 * one and check the value returned for NumGroups at runtime. 2393 */ 2394#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2395#define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2396#endif 2397 2398typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2399{ 2400 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2401 U32 Reserved1; /* 0x08 */ 2402 U32 Reserved2; /* 0x0C */ 2403 U8 NumGroups; /* 0x10 */ 2404 U8 Reserved3; /* 0x11 */ 2405 U16 Reserved4; /* 0x12 */ 2406 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2407 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2408} MPI2_CONFIG_PAGE_SASIOUNIT_6, 2409 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2410 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2411 2412#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2413 2414 2415/* SAS IO Unit Page 7 */ 2416 2417typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2418{ 2419 U8 Flags; /* 0x00 */ 2420 U8 Reserved1; /* 0x01 */ 2421 U16 Reserved2; /* 0x02 */ 2422 U8 Threshold75Pct; /* 0x04 */ 2423 U8 Threshold50Pct; /* 0x05 */ 2424 U8 Threshold25Pct; /* 0x06 */ 2425 U8 Reserved3; /* 0x07 */ 2426} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2427 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2428 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2429 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2430 2431/* defines for Flags field */ 2432#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2433 2434 2435/* 2436 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2437 * one and check the value returned for NumGroups at runtime. 2438 */ 2439#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2440#define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2441#endif 2442 2443typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2444{ 2445 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2446 U8 SamplingInterval; /* 0x08 */ 2447 U8 WindowLength; /* 0x09 */ 2448 U16 Reserved1; /* 0x0A */ 2449 U32 Reserved2; /* 0x0C */ 2450 U32 Reserved3; /* 0x10 */ 2451 U8 NumGroups; /* 0x14 */ 2452 U8 Reserved4; /* 0x15 */ 2453 U16 Reserved5; /* 0x16 */ 2454 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2455 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2456} MPI2_CONFIG_PAGE_SASIOUNIT_7, 2457 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2458 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2459 2460#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2461 2462 2463/* SAS IO Unit Page 8 */ 2464 2465typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2466{ 2467 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2468 U32 Reserved1; /* 0x08 */ 2469 U32 PowerManagementCapabilities; /* 0x0C */ 2470 U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */ 2471 U8 Reserved2; /* 0x11 */ 2472 U16 Reserved3; /* 0x12 */ 2473} MPI2_CONFIG_PAGE_SASIOUNIT_8, 2474 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2475 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2476 2477#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2478 2479/* defines for PowerManagementCapabilities field */ 2480#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2481#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2482#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2483#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2484#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2485#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2486#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2487#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2488#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2489#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2490 2491/* defines for TxRxSleepStatus field */ 2492#define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2493#define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2494#define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2495#define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2496 2497 2498 2499/* SAS IO Unit Page 16 */ 2500 2501typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 2502{ 2503 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2504 U64 TimeStamp; /* 0x08 */ 2505 U32 Reserved1; /* 0x10 */ 2506 U32 Reserved2; /* 0x14 */ 2507 U32 FastPathPendedRequests; /* 0x18 */ 2508 U32 FastPathUnPendedRequests; /* 0x1C */ 2509 U32 FastPathHostRequestStarts; /* 0x20 */ 2510 U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2511 U32 FastPathHostCompletions; /* 0x28 */ 2512 U32 FastPathFirmwareCompletions; /* 0x2C */ 2513 U32 NonFastPathRequestStarts; /* 0x30 */ 2514 U32 NonFastPathHostCompletions; /* 0x30 */ 2515} MPI2_CONFIG_PAGE_SASIOUNIT16, 2516 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2517 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2518 2519#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2520 2521 2522/**************************************************************************** 2523* SAS Expander Config Pages 2524****************************************************************************/ 2525 2526/* SAS Expander Page 0 */ 2527 2528typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2529{ 2530 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2531 U8 PhysicalPort; /* 0x08 */ 2532 U8 ReportGenLength; /* 0x09 */ 2533 U16 EnclosureHandle; /* 0x0A */ 2534 U64 SASAddress; /* 0x0C */ 2535 U32 DiscoveryStatus; /* 0x14 */ 2536 U16 DevHandle; /* 0x18 */ 2537 U16 ParentDevHandle; /* 0x1A */ 2538 U16 ExpanderChangeCount; /* 0x1C */ 2539 U16 ExpanderRouteIndexes; /* 0x1E */ 2540 U8 NumPhys; /* 0x20 */ 2541 U8 SASLevel; /* 0x21 */ 2542 U16 Flags; /* 0x22 */ 2543 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2544 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2545 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2546 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2547 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2548 U16 ZoneLockInactivityLimit; /* 0x34 */ 2549 U16 Reserved1; /* 0x36 */ 2550 U8 TimeToReducedFunc; /* 0x38 */ 2551 U8 InitialTimeToReducedFunc; /* 0x39 */ 2552 U8 MaxReducedFuncTime; /* 0x3A */ 2553 U8 Reserved2; /* 0x3B */ 2554} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2555 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2556 2557#define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2558 2559/* values for SAS Expander Page 0 DiscoveryStatus field */ 2560#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2561#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2562#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2563#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2564#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2565#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2566#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2567#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2568#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2569#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2570#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2571#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2572#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2573#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2574#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2575#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2576#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2577#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2578#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2579#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2580 2581/* values for SAS Expander Page 0 Flags field */ 2582#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2583#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2584#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2585#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2586#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2587#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2588#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2589#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2590#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2591#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2592#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2593 2594 2595/* SAS Expander Page 1 */ 2596 2597typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2598{ 2599 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2600 U8 PhysicalPort; /* 0x08 */ 2601 U8 Reserved1; /* 0x09 */ 2602 U16 Reserved2; /* 0x0A */ 2603 U8 NumPhys; /* 0x0C */ 2604 U8 Phy; /* 0x0D */ 2605 U16 NumTableEntriesProgrammed; /* 0x0E */ 2606 U8 ProgrammedLinkRate; /* 0x10 */ 2607 U8 HwLinkRate; /* 0x11 */ 2608 U16 AttachedDevHandle; /* 0x12 */ 2609 U32 PhyInfo; /* 0x14 */ 2610 U32 AttachedDeviceInfo; /* 0x18 */ 2611 U16 ExpanderDevHandle; /* 0x1C */ 2612 U8 ChangeCount; /* 0x1E */ 2613 U8 NegotiatedLinkRate; /* 0x1F */ 2614 U8 PhyIdentifier; /* 0x20 */ 2615 U8 AttachedPhyIdentifier; /* 0x21 */ 2616 U8 Reserved3; /* 0x22 */ 2617 U8 DiscoveryInfo; /* 0x23 */ 2618 U32 AttachedPhyInfo; /* 0x24 */ 2619 U8 ZoneGroup; /* 0x28 */ 2620 U8 SelfConfigStatus; /* 0x29 */ 2621 U16 Reserved4; /* 0x2A */ 2622} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2623 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2624 2625#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2626 2627/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2628 2629/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2630 2631/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2632 2633/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2634 2635/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2636 2637/* values for SAS Expander Page 1 DiscoveryInfo field */ 2638#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2639#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2640#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2641 2642/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2643 2644 2645/**************************************************************************** 2646* SAS Device Config Pages 2647****************************************************************************/ 2648 2649/* SAS Device Page 0 */ 2650 2651typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2652{ 2653 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2654 U16 Slot; /* 0x08 */ 2655 U16 EnclosureHandle; /* 0x0A */ 2656 U64 SASAddress; /* 0x0C */ 2657 U16 ParentDevHandle; /* 0x14 */ 2658 U8 PhyNum; /* 0x16 */ 2659 U8 AccessStatus; /* 0x17 */ 2660 U16 DevHandle; /* 0x18 */ 2661 U8 AttachedPhyIdentifier; /* 0x1A */ 2662 U8 ZoneGroup; /* 0x1B */ 2663 U32 DeviceInfo; /* 0x1C */ 2664 U16 Flags; /* 0x20 */ 2665 U8 PhysicalPort; /* 0x22 */ 2666 U8 MaxPortConnections; /* 0x23 */ 2667 U64 DeviceName; /* 0x24 */ 2668 U8 PortGroups; /* 0x2C */ 2669 U8 DmaGroup; /* 0x2D */ 2670 U8 ControlGroup; /* 0x2E */ 2671 U8 EnclosureLevel; /* 0x2F */ 2672 U8 ConnectorName[4]; /* 0x30 */ 2673 U32 Reserved3; /* 0x34 */ 2674} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2675 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2676 2677#define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2678 2679/* values for SAS Device Page 0 AccessStatus field */ 2680#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2681#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2682#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2683#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2684#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2685#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2686#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2687#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2688/* specific values for SATA Init failures */ 2689#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2690#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2691#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2692#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2693#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2694#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2695#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2696#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2697#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2698#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2699#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2700 2701/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2702 2703/* values for SAS Device Page 0 Flags field */ 2704#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2705#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2706#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2707#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2708#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2709#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2710#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2711#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2712#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2713#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2714#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2715#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2716#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2717#define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2718#define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2719#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2720 2721 2722/* SAS Device Page 1 */ 2723 2724typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2725{ 2726 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2727 U32 Reserved1; /* 0x08 */ 2728 U64 SASAddress; /* 0x0C */ 2729 U32 Reserved2; /* 0x14 */ 2730 U16 DevHandle; /* 0x18 */ 2731 U16 Reserved3; /* 0x1A */ 2732 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2733} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2734 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2735 2736#define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2737 2738 2739/**************************************************************************** 2740* SAS PHY Config Pages 2741****************************************************************************/ 2742 2743/* SAS PHY Page 0 */ 2744 2745typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2746{ 2747 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2748 U16 OwnerDevHandle; /* 0x08 */ 2749 U16 Reserved1; /* 0x0A */ 2750 U16 AttachedDevHandle; /* 0x0C */ 2751 U8 AttachedPhyIdentifier; /* 0x0E */ 2752 U8 Reserved2; /* 0x0F */ 2753 U32 AttachedPhyInfo; /* 0x10 */ 2754 U8 ProgrammedLinkRate; /* 0x14 */ 2755 U8 HwLinkRate; /* 0x15 */ 2756 U8 ChangeCount; /* 0x16 */ 2757 U8 Flags; /* 0x17 */ 2758 U32 PhyInfo; /* 0x18 */ 2759 U8 NegotiatedLinkRate; /* 0x1C */ 2760 U8 Reserved3; /* 0x1D */ 2761 U16 Reserved4; /* 0x1E */ 2762} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2763 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2764 2765#define MPI2_SASPHY0_PAGEVERSION (0x03) 2766 2767/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2768 2769/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2770 2771/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2772 2773/* values for SAS PHY Page 0 Flags field */ 2774#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2775 2776/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2777 2778/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2779 2780 2781/* SAS PHY Page 1 */ 2782 2783typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2784{ 2785 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2786 U32 Reserved1; /* 0x08 */ 2787 U32 InvalidDwordCount; /* 0x0C */ 2788 U32 RunningDisparityErrorCount; /* 0x10 */ 2789 U32 LossDwordSynchCount; /* 0x14 */ 2790 U32 PhyResetProblemCount; /* 0x18 */ 2791} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2792 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2793 2794#define MPI2_SASPHY1_PAGEVERSION (0x01) 2795 2796 2797/* SAS PHY Page 2 */ 2798 2799typedef struct _MPI2_SASPHY2_PHY_EVENT 2800{ 2801 U8 PhyEventCode; /* 0x00 */ 2802 U8 Reserved1; /* 0x01 */ 2803 U16 Reserved2; /* 0x02 */ 2804 U32 PhyEventInfo; /* 0x04 */ 2805} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2806 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2807 2808/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2809 2810 2811/* 2812 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2813 * one and check the value returned for NumPhyEvents at runtime. 2814 */ 2815#ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2816#define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2817#endif 2818 2819typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2820{ 2821 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2822 U32 Reserved1; /* 0x08 */ 2823 U8 NumPhyEvents; /* 0x0C */ 2824 U8 Reserved2; /* 0x0D */ 2825 U16 Reserved3; /* 0x0E */ 2826 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2827} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2828 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2829 2830#define MPI2_SASPHY2_PAGEVERSION (0x00) 2831 2832 2833/* SAS PHY Page 3 */ 2834 2835typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2836{ 2837 U8 PhyEventCode; /* 0x00 */ 2838 U8 Reserved1; /* 0x01 */ 2839 U16 Reserved2; /* 0x02 */ 2840 U8 CounterType; /* 0x04 */ 2841 U8 ThresholdWindow; /* 0x05 */ 2842 U8 TimeUnits; /* 0x06 */ 2843 U8 Reserved3; /* 0x07 */ 2844 U32 EventThreshold; /* 0x08 */ 2845 U16 ThresholdFlags; /* 0x0C */ 2846 U16 Reserved4; /* 0x0E */ 2847} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2848 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2849 2850/* values for PhyEventCode field */ 2851#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2852#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2853#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2854#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2855#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2856#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2857#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2858#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2859#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2860#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2861#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2862#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2863#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2864#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2865#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2866#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2867#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2868#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2869#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2870#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2871#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2872#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2873#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2874#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2875#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2876#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2877#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2878#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2879#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2880#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2881#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2882#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2883#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2884#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2885#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2886#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2887#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2888 2889/* Following codes are product specific and in MPI v2.6 and later */ 2890#define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 2891#define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 2892#define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 2893#define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 2894#define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 2895#define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 2896#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 2897#define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 2898#define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 2899#define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 2900 2901 2902/* values for the CounterType field */ 2903#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2904#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2905#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2906 2907/* values for the TimeUnits field */ 2908#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2909#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2910#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2911#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2912 2913/* values for the ThresholdFlags field */ 2914#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2915#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2916 2917/* 2918 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2919 * one and check the value returned for NumPhyEvents at runtime. 2920 */ 2921#ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2922#define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2923#endif 2924 2925typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2926{ 2927 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2928 U32 Reserved1; /* 0x08 */ 2929 U8 NumPhyEvents; /* 0x0C */ 2930 U8 Reserved2; /* 0x0D */ 2931 U16 Reserved3; /* 0x0E */ 2932 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2933} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2934 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2935 2936#define MPI2_SASPHY3_PAGEVERSION (0x00) 2937 2938 2939/* SAS PHY Page 4 */ 2940 2941typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2942{ 2943 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2944 U16 Reserved1; /* 0x08 */ 2945 U8 Reserved2; /* 0x0A */ 2946 U8 Flags; /* 0x0B */ 2947 U8 InitialFrame[28]; /* 0x0C */ 2948} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2949 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2950 2951#define MPI2_SASPHY4_PAGEVERSION (0x00) 2952 2953/* values for the Flags field */ 2954#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2955#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2956 2957 2958 2959 2960/**************************************************************************** 2961* SAS Port Config Pages 2962****************************************************************************/ 2963 2964/* SAS Port Page 0 */ 2965 2966typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2967{ 2968 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2969 U8 PortNumber; /* 0x08 */ 2970 U8 PhysicalPort; /* 0x09 */ 2971 U8 PortWidth; /* 0x0A */ 2972 U8 PhysicalPortWidth; /* 0x0B */ 2973 U8 ZoneGroup; /* 0x0C */ 2974 U8 Reserved1; /* 0x0D */ 2975 U16 Reserved2; /* 0x0E */ 2976 U64 SASAddress; /* 0x10 */ 2977 U32 DeviceInfo; /* 0x18 */ 2978 U32 Reserved3; /* 0x1C */ 2979 U32 Reserved4; /* 0x20 */ 2980} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2981 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2982 2983#define MPI2_SASPORT0_PAGEVERSION (0x00) 2984 2985/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2986 2987 2988/**************************************************************************** 2989* SAS Enclosure Config Pages 2990****************************************************************************/ 2991 2992/* SAS Enclosure Page 0 */ 2993 2994typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2995{ 2996 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2997 U32 Reserved1; /* 0x08 */ 2998 U64 EnclosureLogicalID; /* 0x0C */ 2999 U16 Flags; /* 0x14 */ 3000 U16 EnclosureHandle; /* 0x16 */ 3001 U16 NumSlots; /* 0x18 */ 3002 U16 StartSlot; /* 0x1A */ 3003 U8 Reserved2; /* 0x1C */ 3004 U8 EnclosureLevel; /* 0x1D */ 3005 U16 SEPDevHandle; /* 0x1E */ 3006 U32 Reserved3; /* 0x20 */ 3007 U32 Reserved4; /* 0x24 */ 3008} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3009 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3010 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 3011 3012#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3013 3014/* values for SAS Enclosure Page 0 Flags field */ 3015#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3016#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3017#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3018#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3019#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3020#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3021#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3022#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3023 3024 3025/**************************************************************************** 3026* Log Config Page 3027****************************************************************************/ 3028 3029/* Log Page 0 */ 3030 3031/* 3032 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3033 * one and check the value returned for NumLogEntries at runtime. 3034 */ 3035#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3036#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3037#endif 3038 3039#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3040 3041typedef struct _MPI2_LOG_0_ENTRY 3042{ 3043 U64 TimeStamp; /* 0x00 */ 3044 U32 Reserved1; /* 0x08 */ 3045 U16 LogSequence; /* 0x0C */ 3046 U16 LogEntryQualifier; /* 0x0E */ 3047 U8 VP_ID; /* 0x10 */ 3048 U8 VF_ID; /* 0x11 */ 3049 U16 Reserved2; /* 0x12 */ 3050 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 3051} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 3052 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 3053 3054/* values for Log Page 0 LogEntry LogEntryQualifier field */ 3055#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3056#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3057#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3058#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3059#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3060 3061typedef struct _MPI2_CONFIG_PAGE_LOG_0 3062{ 3063 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3064 U32 Reserved1; /* 0x08 */ 3065 U32 Reserved2; /* 0x0C */ 3066 U16 NumLogEntries; /* 0x10 */ 3067 U16 Reserved3; /* 0x12 */ 3068 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 3069} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 3070 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 3071 3072#define MPI2_LOG_0_PAGEVERSION (0x02) 3073 3074 3075/**************************************************************************** 3076* RAID Config Page 3077****************************************************************************/ 3078 3079/* RAID Page 0 */ 3080 3081/* 3082 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3083 * one and check the value returned for NumElements at runtime. 3084 */ 3085#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3086#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3087#endif 3088 3089typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3090{ 3091 U16 ElementFlags; /* 0x00 */ 3092 U16 VolDevHandle; /* 0x02 */ 3093 U8 HotSparePool; /* 0x04 */ 3094 U8 PhysDiskNum; /* 0x05 */ 3095 U16 PhysDiskDevHandle; /* 0x06 */ 3096} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3097 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3098 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 3099 3100/* values for the ElementFlags field */ 3101#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3102#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3103#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3104#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3105#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3106 3107 3108typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 3109{ 3110 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3111 U8 NumHotSpares; /* 0x08 */ 3112 U8 NumPhysDisks; /* 0x09 */ 3113 U8 NumVolumes; /* 0x0A */ 3114 U8 ConfigNum; /* 0x0B */ 3115 U32 Flags; /* 0x0C */ 3116 U8 ConfigGUID[24]; /* 0x10 */ 3117 U32 Reserved1; /* 0x28 */ 3118 U8 NumElements; /* 0x2C */ 3119 U8 Reserved2; /* 0x2D */ 3120 U16 Reserved3; /* 0x2E */ 3121 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 3122} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3123 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3124 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 3125 3126#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3127 3128/* values for RAID Configuration Page 0 Flags field */ 3129#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3130 3131 3132/**************************************************************************** 3133* Driver Persistent Mapping Config Pages 3134****************************************************************************/ 3135 3136/* Driver Persistent Mapping Page 0 */ 3137 3138typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 3139{ 3140 U64 PhysicalIdentifier; /* 0x00 */ 3141 U16 MappingInformation; /* 0x08 */ 3142 U16 DeviceIndex; /* 0x0A */ 3143 U32 PhysicalBitsMapping; /* 0x0C */ 3144 U32 Reserved1; /* 0x10 */ 3145} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3146 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3147 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 3148 3149typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 3150{ 3151 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3152 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 3153} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3154 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3155 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 3156 3157#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3158 3159/* values for Driver Persistent Mapping Page 0 MappingInformation field */ 3160#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3161#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3162#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3163 3164 3165/**************************************************************************** 3166* Ethernet Config Pages 3167****************************************************************************/ 3168 3169/* Ethernet Page 0 */ 3170 3171/* IP address (union of IPv4 and IPv6) */ 3172typedef union _MPI2_ETHERNET_IP_ADDR 3173{ 3174 U32 IPv4Addr; 3175 U32 IPv6Addr[4]; 3176} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 3177 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 3178 3179#define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3180 3181typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 3182{ 3183 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3184 U8 NumInterfaces; /* 0x08 */ 3185 U8 Reserved0; /* 0x09 */ 3186 U16 Reserved1; /* 0x0A */ 3187 U32 Status; /* 0x0C */ 3188 U8 MediaState; /* 0x10 */ 3189 U8 Reserved2; /* 0x11 */ 3190 U16 Reserved3; /* 0x12 */ 3191 U8 MacAddress[6]; /* 0x14 */ 3192 U8 Reserved4; /* 0x1A */ 3193 U8 Reserved5; /* 0x1B */ 3194 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 3195 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 3196 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 3197 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 3198 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 3199 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 3200 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3201} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3202 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 3203 3204#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3205 3206/* values for Ethernet Page 0 Status field */ 3207#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3208#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3209#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3210#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3211#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3212#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3213#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3214#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3215#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3216#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3217#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3218#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3219 3220/* values for Ethernet Page 0 MediaState field */ 3221#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3222#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3223#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3224 3225#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3226#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3227#define MPI2_ETHPG0_MS_10MBIT (0x01) 3228#define MPI2_ETHPG0_MS_100MBIT (0x02) 3229#define MPI2_ETHPG0_MS_1GBIT (0x03) 3230 3231 3232/* Ethernet Page 1 */ 3233 3234typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 3235{ 3236 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3237 U32 Reserved0; /* 0x08 */ 3238 U32 Flags; /* 0x0C */ 3239 U8 MediaState; /* 0x10 */ 3240 U8 Reserved1; /* 0x11 */ 3241 U16 Reserved2; /* 0x12 */ 3242 U8 MacAddress[6]; /* 0x14 */ 3243 U8 Reserved3; /* 0x1A */ 3244 U8 Reserved4; /* 0x1B */ 3245 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 3246 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 3247 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 3248 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 3249 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 3250 U32 Reserved5; /* 0x6C */ 3251 U32 Reserved6; /* 0x70 */ 3252 U32 Reserved7; /* 0x74 */ 3253 U32 Reserved8; /* 0x78 */ 3254 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3255} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3256 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 3257 3258#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3259 3260/* values for Ethernet Page 1 Flags field */ 3261#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3262#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3263#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3264#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3265#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3266#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3267#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3268#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3269#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3270 3271/* values for Ethernet Page 1 MediaState field */ 3272#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3273#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3274#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3275 3276#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3277#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3278#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3279#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3280#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3281 3282 3283/**************************************************************************** 3284* Extended Manufacturing Config Pages 3285****************************************************************************/ 3286 3287/* 3288 * Generic structure to use for product-specific extended manufacturing pages 3289 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3290 * Page 60). 3291 */ 3292 3293typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 3294{ 3295 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3296 U32 ProductSpecificInfo; /* 0x08 */ 3297} MPI2_CONFIG_PAGE_EXT_MAN_PS, 3298 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3299 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3300 3301/* PageVersion should be provided by product-specific code */ 3302 3303#endif 3304 3305