if_iwm_pcie_trans.c revision 286441
1286441Srpaulo/* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2286441Srpaulo 3286441Srpaulo/* 4286441Srpaulo * Copyright (c) 2014 genua mbh <info@genua.de> 5286441Srpaulo * Copyright (c) 2014 Fixup Software Ltd. 6286441Srpaulo * 7286441Srpaulo * Permission to use, copy, modify, and distribute this software for any 8286441Srpaulo * purpose with or without fee is hereby granted, provided that the above 9286441Srpaulo * copyright notice and this permission notice appear in all copies. 10286441Srpaulo * 11286441Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12286441Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13286441Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14286441Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15286441Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16286441Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17286441Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18286441Srpaulo */ 19286441Srpaulo 20286441Srpaulo/*- 21286441Srpaulo * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22286441Srpaulo * which were used as the reference documentation for this implementation. 23286441Srpaulo * 24286441Srpaulo * Driver version we are currently based off of is 25286441Srpaulo * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26286441Srpaulo * 27286441Srpaulo *********************************************************************** 28286441Srpaulo * 29286441Srpaulo * This file is provided under a dual BSD/GPLv2 license. When using or 30286441Srpaulo * redistributing this file, you may do so under either license. 31286441Srpaulo * 32286441Srpaulo * GPL LICENSE SUMMARY 33286441Srpaulo * 34286441Srpaulo * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35286441Srpaulo * 36286441Srpaulo * This program is free software; you can redistribute it and/or modify 37286441Srpaulo * it under the terms of version 2 of the GNU General Public License as 38286441Srpaulo * published by the Free Software Foundation. 39286441Srpaulo * 40286441Srpaulo * This program is distributed in the hope that it will be useful, but 41286441Srpaulo * WITHOUT ANY WARRANTY; without even the implied warranty of 42286441Srpaulo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43286441Srpaulo * General Public License for more details. 44286441Srpaulo * 45286441Srpaulo * You should have received a copy of the GNU General Public License 46286441Srpaulo * along with this program; if not, write to the Free Software 47286441Srpaulo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48286441Srpaulo * USA 49286441Srpaulo * 50286441Srpaulo * The full GNU General Public License is included in this distribution 51286441Srpaulo * in the file called COPYING. 52286441Srpaulo * 53286441Srpaulo * Contact Information: 54286441Srpaulo * Intel Linux Wireless <ilw@linux.intel.com> 55286441Srpaulo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56286441Srpaulo * 57286441Srpaulo * 58286441Srpaulo * BSD LICENSE 59286441Srpaulo * 60286441Srpaulo * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61286441Srpaulo * All rights reserved. 62286441Srpaulo * 63286441Srpaulo * Redistribution and use in source and binary forms, with or without 64286441Srpaulo * modification, are permitted provided that the following conditions 65286441Srpaulo * are met: 66286441Srpaulo * 67286441Srpaulo * * Redistributions of source code must retain the above copyright 68286441Srpaulo * notice, this list of conditions and the following disclaimer. 69286441Srpaulo * * Redistributions in binary form must reproduce the above copyright 70286441Srpaulo * notice, this list of conditions and the following disclaimer in 71286441Srpaulo * the documentation and/or other materials provided with the 72286441Srpaulo * distribution. 73286441Srpaulo * * Neither the name Intel Corporation nor the names of its 74286441Srpaulo * contributors may be used to endorse or promote products derived 75286441Srpaulo * from this software without specific prior written permission. 76286441Srpaulo * 77286441Srpaulo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78286441Srpaulo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79286441Srpaulo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80286441Srpaulo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81286441Srpaulo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82286441Srpaulo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83286441Srpaulo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84286441Srpaulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85286441Srpaulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86286441Srpaulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87286441Srpaulo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88286441Srpaulo */ 89286441Srpaulo 90286441Srpaulo/*- 91286441Srpaulo * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92286441Srpaulo * 93286441Srpaulo * Permission to use, copy, modify, and distribute this software for any 94286441Srpaulo * purpose with or without fee is hereby granted, provided that the above 95286441Srpaulo * copyright notice and this permission notice appear in all copies. 96286441Srpaulo * 97286441Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98286441Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99286441Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100286441Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101286441Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102286441Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103286441Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104286441Srpaulo */ 105286441Srpaulo#include <sys/cdefs.h> 106286441Srpaulo__FBSDID("$FreeBSD: head/sys/dev/iwm/if_iwm_pcie_trans.c 286441 2015-08-08 06:06:48Z rpaulo $"); 107286441Srpaulo 108286441Srpaulo#include <sys/param.h> 109286441Srpaulo#include <sys/bus.h> 110286441Srpaulo#include <sys/conf.h> 111286441Srpaulo#include <sys/endian.h> 112286441Srpaulo#include <sys/firmware.h> 113286441Srpaulo#include <sys/kernel.h> 114286441Srpaulo#include <sys/malloc.h> 115286441Srpaulo#include <sys/mbuf.h> 116286441Srpaulo#include <sys/mutex.h> 117286441Srpaulo#include <sys/module.h> 118286441Srpaulo#include <sys/proc.h> 119286441Srpaulo#include <sys/rman.h> 120286441Srpaulo#include <sys/socket.h> 121286441Srpaulo#include <sys/sockio.h> 122286441Srpaulo#include <sys/sysctl.h> 123286441Srpaulo#include <sys/linker.h> 124286441Srpaulo 125286441Srpaulo#include <machine/bus.h> 126286441Srpaulo#include <machine/endian.h> 127286441Srpaulo#include <machine/resource.h> 128286441Srpaulo 129286441Srpaulo#include <dev/pci/pcivar.h> 130286441Srpaulo#include <dev/pci/pcireg.h> 131286441Srpaulo 132286441Srpaulo#include <net/bpf.h> 133286441Srpaulo 134286441Srpaulo#include <net/if.h> 135286441Srpaulo#include <net/if_var.h> 136286441Srpaulo#include <net/if_arp.h> 137286441Srpaulo#include <net/if_dl.h> 138286441Srpaulo#include <net/if_media.h> 139286441Srpaulo#include <net/if_types.h> 140286441Srpaulo 141286441Srpaulo#include <netinet/in.h> 142286441Srpaulo#include <netinet/in_systm.h> 143286441Srpaulo#include <netinet/if_ether.h> 144286441Srpaulo#include <netinet/ip.h> 145286441Srpaulo 146286441Srpaulo#include <net80211/ieee80211_var.h> 147286441Srpaulo#include <net80211/ieee80211_regdomain.h> 148286441Srpaulo#include <net80211/ieee80211_ratectl.h> 149286441Srpaulo#include <net80211/ieee80211_radiotap.h> 150286441Srpaulo 151286441Srpaulo#include <if_iwmreg.h> 152286441Srpaulo#include <if_iwmvar.h> 153286441Srpaulo#include <if_iwm_debug.h> 154286441Srpaulo 155286441Srpaulo#include <if_iwm_pcie_trans.h> 156286441Srpaulo 157286441Srpaulo/* 158286441Srpaulo * This is a subset of what's in linux iwlwifi/pcie/trans.c. 159286441Srpaulo * The rest can be migrated out into here once they're no longer in 160286441Srpaulo * if_iwm.c. 161286441Srpaulo */ 162286441Srpaulo 163286441Srpaulo/* 164286441Srpaulo * basic device access 165286441Srpaulo */ 166286441Srpaulo 167286441Srpaulouint32_t 168286441Srpauloiwm_read_prph(struct iwm_softc *sc, uint32_t addr) 169286441Srpaulo{ 170286441Srpaulo IWM_WRITE(sc, 171286441Srpaulo IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 172286441Srpaulo IWM_BARRIER_READ_WRITE(sc); 173286441Srpaulo return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 174286441Srpaulo} 175286441Srpaulo 176286441Srpaulovoid 177286441Srpauloiwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 178286441Srpaulo{ 179286441Srpaulo IWM_WRITE(sc, 180286441Srpaulo IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 181286441Srpaulo IWM_BARRIER_WRITE(sc); 182286441Srpaulo IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 183286441Srpaulo} 184286441Srpaulo 185286441Srpaulo#ifdef IWM_DEBUG 186286441Srpaulo/* iwlwifi: pcie/trans.c */ 187286441Srpauloint 188286441Srpauloiwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 189286441Srpaulo{ 190286441Srpaulo int offs, ret = 0; 191286441Srpaulo uint32_t *vals = buf; 192286441Srpaulo 193286441Srpaulo if (iwm_nic_lock(sc)) { 194286441Srpaulo IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 195286441Srpaulo for (offs = 0; offs < dwords; offs++) 196286441Srpaulo vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 197286441Srpaulo iwm_nic_unlock(sc); 198286441Srpaulo } else { 199286441Srpaulo ret = EBUSY; 200286441Srpaulo } 201286441Srpaulo return ret; 202286441Srpaulo} 203286441Srpaulo#endif 204286441Srpaulo 205286441Srpaulo/* iwlwifi: pcie/trans.c */ 206286441Srpauloint 207286441Srpauloiwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 208286441Srpaulo{ 209286441Srpaulo int offs; 210286441Srpaulo const uint32_t *vals = buf; 211286441Srpaulo 212286441Srpaulo if (iwm_nic_lock(sc)) { 213286441Srpaulo IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 214286441Srpaulo /* WADDR auto-increments */ 215286441Srpaulo for (offs = 0; offs < dwords; offs++) { 216286441Srpaulo uint32_t val = vals ? vals[offs] : 0; 217286441Srpaulo IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 218286441Srpaulo } 219286441Srpaulo iwm_nic_unlock(sc); 220286441Srpaulo } else { 221286441Srpaulo IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 222286441Srpaulo "%s: write_mem failed\n", __func__); 223286441Srpaulo return EBUSY; 224286441Srpaulo } 225286441Srpaulo return 0; 226286441Srpaulo} 227286441Srpaulo 228286441Srpauloint 229286441Srpauloiwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 230286441Srpaulo{ 231286441Srpaulo return iwm_write_mem(sc, addr, &val, 1); 232286441Srpaulo} 233286441Srpaulo 234286441Srpauloint 235286441Srpauloiwm_poll_bit(struct iwm_softc *sc, int reg, 236286441Srpaulo uint32_t bits, uint32_t mask, int timo) 237286441Srpaulo{ 238286441Srpaulo for (;;) { 239286441Srpaulo if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 240286441Srpaulo return 1; 241286441Srpaulo } 242286441Srpaulo if (timo < 10) { 243286441Srpaulo return 0; 244286441Srpaulo } 245286441Srpaulo timo -= 10; 246286441Srpaulo DELAY(10); 247286441Srpaulo } 248286441Srpaulo} 249286441Srpaulo 250286441Srpauloint 251286441Srpauloiwm_nic_lock(struct iwm_softc *sc) 252286441Srpaulo{ 253286441Srpaulo int rv = 0; 254286441Srpaulo 255286441Srpaulo IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 256286441Srpaulo IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 257286441Srpaulo 258286441Srpaulo if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 259286441Srpaulo IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 260286441Srpaulo IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 261286441Srpaulo | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 262286441Srpaulo rv = 1; 263286441Srpaulo } else { 264286441Srpaulo /* jolt */ 265286441Srpaulo IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 266286441Srpaulo } 267286441Srpaulo 268286441Srpaulo return rv; 269286441Srpaulo} 270286441Srpaulo 271286441Srpaulovoid 272286441Srpauloiwm_nic_unlock(struct iwm_softc *sc) 273286441Srpaulo{ 274286441Srpaulo IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 275286441Srpaulo IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 276286441Srpaulo} 277286441Srpaulo 278286441Srpaulovoid 279286441Srpauloiwm_set_bits_mask_prph(struct iwm_softc *sc, 280286441Srpaulo uint32_t reg, uint32_t bits, uint32_t mask) 281286441Srpaulo{ 282286441Srpaulo uint32_t val; 283286441Srpaulo 284286441Srpaulo /* XXX: no error path? */ 285286441Srpaulo if (iwm_nic_lock(sc)) { 286286441Srpaulo val = iwm_read_prph(sc, reg) & mask; 287286441Srpaulo val |= bits; 288286441Srpaulo iwm_write_prph(sc, reg, val); 289286441Srpaulo iwm_nic_unlock(sc); 290286441Srpaulo } 291286441Srpaulo} 292286441Srpaulo 293286441Srpaulovoid 294286441Srpauloiwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 295286441Srpaulo{ 296286441Srpaulo iwm_set_bits_mask_prph(sc, reg, bits, ~0); 297286441Srpaulo} 298286441Srpaulo 299286441Srpaulovoid 300286441Srpauloiwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 301286441Srpaulo{ 302286441Srpaulo iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 303286441Srpaulo} 304286441Srpaulo 305286441Srpaulo/* 306286441Srpaulo * High-level hardware frobbing routines 307286441Srpaulo */ 308286441Srpaulo 309286441Srpaulovoid 310286441Srpauloiwm_enable_rfkill_int(struct iwm_softc *sc) 311286441Srpaulo{ 312286441Srpaulo sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 313286441Srpaulo IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 314286441Srpaulo} 315286441Srpaulo 316286441Srpauloint 317286441Srpauloiwm_check_rfkill(struct iwm_softc *sc) 318286441Srpaulo{ 319286441Srpaulo uint32_t v; 320286441Srpaulo int rv; 321286441Srpaulo 322286441Srpaulo /* 323286441Srpaulo * "documentation" is not really helpful here: 324286441Srpaulo * 27: HW_RF_KILL_SW 325286441Srpaulo * Indicates state of (platform's) hardware RF-Kill switch 326286441Srpaulo * 327286441Srpaulo * But apparently when it's off, it's on ... 328286441Srpaulo */ 329286441Srpaulo v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 330286441Srpaulo rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 331286441Srpaulo if (rv) { 332286441Srpaulo sc->sc_flags |= IWM_FLAG_RFKILL; 333286441Srpaulo } else { 334286441Srpaulo sc->sc_flags &= ~IWM_FLAG_RFKILL; 335286441Srpaulo } 336286441Srpaulo 337286441Srpaulo return rv; 338286441Srpaulo} 339286441Srpaulo 340286441Srpaulo 341286441Srpaulo#define IWM_HW_READY_TIMEOUT 50 342286441Srpauloint 343286441Srpauloiwm_set_hw_ready(struct iwm_softc *sc) 344286441Srpaulo{ 345286441Srpaulo IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 346286441Srpaulo IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 347286441Srpaulo 348286441Srpaulo return iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 349286441Srpaulo IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 350286441Srpaulo IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 351286441Srpaulo IWM_HW_READY_TIMEOUT); 352286441Srpaulo} 353286441Srpaulo#undef IWM_HW_READY_TIMEOUT 354286441Srpaulo 355286441Srpauloint 356286441Srpauloiwm_prepare_card_hw(struct iwm_softc *sc) 357286441Srpaulo{ 358286441Srpaulo int rv = 0; 359286441Srpaulo int t = 0; 360286441Srpaulo 361286441Srpaulo IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 362286441Srpaulo if (iwm_set_hw_ready(sc)) 363286441Srpaulo goto out; 364286441Srpaulo 365286441Srpaulo /* If HW is not ready, prepare the conditions to check again */ 366286441Srpaulo IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 367286441Srpaulo IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 368286441Srpaulo 369286441Srpaulo do { 370286441Srpaulo if (iwm_set_hw_ready(sc)) 371286441Srpaulo goto out; 372286441Srpaulo DELAY(200); 373286441Srpaulo t += 200; 374286441Srpaulo } while (t < 150000); 375286441Srpaulo 376286441Srpaulo rv = ETIMEDOUT; 377286441Srpaulo 378286441Srpaulo out: 379286441Srpaulo IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 380286441Srpaulo return rv; 381286441Srpaulo} 382286441Srpaulo 383286441Srpaulovoid 384286441Srpauloiwm_apm_config(struct iwm_softc *sc) 385286441Srpaulo{ 386286441Srpaulo uint16_t reg; 387286441Srpaulo 388286441Srpaulo reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg)); 389286441Srpaulo if (reg & PCIEM_LINK_CTL_ASPMC_L1) { 390286441Srpaulo /* Um the Linux driver prints "Disabling L0S for this one ... */ 391286441Srpaulo IWM_SETBITS(sc, IWM_CSR_GIO_REG, 392286441Srpaulo IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 393286441Srpaulo } else { 394286441Srpaulo /* ... and "Enabling" here */ 395286441Srpaulo IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 396286441Srpaulo IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 397286441Srpaulo } 398286441Srpaulo} 399286441Srpaulo 400286441Srpaulo/* 401286441Srpaulo * Start up NIC's basic functionality after it has been reset 402286441Srpaulo * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 403286441Srpaulo * NOTE: This does not load uCode nor start the embedded processor 404286441Srpaulo */ 405286441Srpauloint 406286441Srpauloiwm_apm_init(struct iwm_softc *sc) 407286441Srpaulo{ 408286441Srpaulo int error = 0; 409286441Srpaulo 410286441Srpaulo IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 411286441Srpaulo 412286441Srpaulo /* Disable L0S exit timer (platform NMI Work/Around) */ 413286441Srpaulo IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 414286441Srpaulo IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 415286441Srpaulo 416286441Srpaulo /* 417286441Srpaulo * Disable L0s without affecting L1; 418286441Srpaulo * don't wait for ICH L0s (ICH bug W/A) 419286441Srpaulo */ 420286441Srpaulo IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 421286441Srpaulo IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 422286441Srpaulo 423286441Srpaulo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 424286441Srpaulo IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 425286441Srpaulo 426286441Srpaulo /* 427286441Srpaulo * Enable HAP INTA (interrupt from management bus) to 428286441Srpaulo * wake device's PCI Express link L1a -> L0s 429286441Srpaulo */ 430286441Srpaulo IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 431286441Srpaulo IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 432286441Srpaulo 433286441Srpaulo iwm_apm_config(sc); 434286441Srpaulo 435286441Srpaulo#if 0 /* not for 7k */ 436286441Srpaulo /* Configure analog phase-lock-loop before activating to D0A */ 437286441Srpaulo if (trans->cfg->base_params->pll_cfg_val) 438286441Srpaulo IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 439286441Srpaulo trans->cfg->base_params->pll_cfg_val); 440286441Srpaulo#endif 441286441Srpaulo 442286441Srpaulo /* 443286441Srpaulo * Set "initialization complete" bit to move adapter from 444286441Srpaulo * D0U* --> D0A* (powered-up active) state. 445286441Srpaulo */ 446286441Srpaulo IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 447286441Srpaulo 448286441Srpaulo /* 449286441Srpaulo * Wait for clock stabilization; once stabilized, access to 450286441Srpaulo * device-internal resources is supported, e.g. iwm_write_prph() 451286441Srpaulo * and accesses to uCode SRAM. 452286441Srpaulo */ 453286441Srpaulo if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 454286441Srpaulo IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 455286441Srpaulo IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 456286441Srpaulo device_printf(sc->sc_dev, 457286441Srpaulo "timeout waiting for clock stabilization\n"); 458286441Srpaulo 459286441Srpaulo goto out; 460286441Srpaulo } 461286441Srpaulo 462286441Srpaulo if (sc->host_interrupt_operation_mode) { 463286441Srpaulo /* 464286441Srpaulo * This is a bit of an abuse - This is needed for 7260 / 3160 465286441Srpaulo * only check host_interrupt_operation_mode even if this is 466286441Srpaulo * not related to host_interrupt_operation_mode. 467286441Srpaulo * 468286441Srpaulo * Enable the oscillator to count wake up time for L1 exit. This 469286441Srpaulo * consumes slightly more power (100uA) - but allows to be sure 470286441Srpaulo * that we wake up from L1 on time. 471286441Srpaulo * 472286441Srpaulo * This looks weird: read twice the same register, discard the 473286441Srpaulo * value, set a bit, and yet again, read that same register 474286441Srpaulo * just to discard the value. But that's the way the hardware 475286441Srpaulo * seems to like it. 476286441Srpaulo */ 477286441Srpaulo iwm_read_prph(sc, IWM_OSC_CLK); 478286441Srpaulo iwm_read_prph(sc, IWM_OSC_CLK); 479286441Srpaulo iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 480286441Srpaulo iwm_read_prph(sc, IWM_OSC_CLK); 481286441Srpaulo iwm_read_prph(sc, IWM_OSC_CLK); 482286441Srpaulo } 483286441Srpaulo 484286441Srpaulo /* 485286441Srpaulo * Enable DMA clock and wait for it to stabilize. 486286441Srpaulo * 487286441Srpaulo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 488286441Srpaulo * do not disable clocks. This preserves any hardware bits already 489286441Srpaulo * set by default in "CLK_CTRL_REG" after reset. 490286441Srpaulo */ 491286441Srpaulo iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, IWM_APMG_CLK_VAL_DMA_CLK_RQT); 492286441Srpaulo //kpause("iwmapm", 0, mstohz(20), NULL); 493286441Srpaulo DELAY(20); 494286441Srpaulo 495286441Srpaulo /* Disable L1-Active */ 496286441Srpaulo iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 497286441Srpaulo IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 498286441Srpaulo 499286441Srpaulo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 500286441Srpaulo iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 501286441Srpaulo IWM_APMG_RTC_INT_STT_RFKILL); 502286441Srpaulo 503286441Srpaulo out: 504286441Srpaulo if (error) 505286441Srpaulo device_printf(sc->sc_dev, "apm init error %d\n", error); 506286441Srpaulo return error; 507286441Srpaulo} 508286441Srpaulo 509286441Srpaulo/* iwlwifi/pcie/trans.c */ 510286441Srpaulovoid 511286441Srpauloiwm_apm_stop(struct iwm_softc *sc) 512286441Srpaulo{ 513286441Srpaulo /* stop device's busmaster DMA activity */ 514286441Srpaulo IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 515286441Srpaulo 516286441Srpaulo if (!iwm_poll_bit(sc, IWM_CSR_RESET, 517286441Srpaulo IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 518286441Srpaulo IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 519286441Srpaulo device_printf(sc->sc_dev, "timeout waiting for master\n"); 520286441Srpaulo IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 521286441Srpaulo} 522286441Srpaulo 523286441Srpaulo/* iwlwifi pcie/trans.c */ 524286441Srpauloint 525286441Srpauloiwm_start_hw(struct iwm_softc *sc) 526286441Srpaulo{ 527286441Srpaulo int error; 528286441Srpaulo 529286441Srpaulo if ((error = iwm_prepare_card_hw(sc)) != 0) 530286441Srpaulo return error; 531286441Srpaulo 532286441Srpaulo /* Reset the entire device */ 533286441Srpaulo IWM_WRITE(sc, IWM_CSR_RESET, 534286441Srpaulo IWM_CSR_RESET_REG_FLAG_SW_RESET | 535286441Srpaulo IWM_CSR_RESET_REG_FLAG_NEVO_RESET); 536286441Srpaulo DELAY(10); 537286441Srpaulo 538286441Srpaulo if ((error = iwm_apm_init(sc)) != 0) 539286441Srpaulo return error; 540286441Srpaulo 541286441Srpaulo iwm_enable_rfkill_int(sc); 542286441Srpaulo iwm_check_rfkill(sc); 543286441Srpaulo 544286441Srpaulo return 0; 545286441Srpaulo} 546286441Srpaulo 547286441Srpaulo/* iwlwifi pcie/trans.c (always main power) */ 548286441Srpaulovoid 549286441Srpauloiwm_set_pwr(struct iwm_softc *sc) 550286441Srpaulo{ 551286441Srpaulo iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 552286441Srpaulo IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 553286441Srpaulo} 554286441Srpaulo 555286441Srpaulo/* iwlwifi pcie/rx.c */ 556286441Srpauloint 557286441Srpauloiwm_pcie_rx_stop(struct iwm_softc *sc) 558286441Srpaulo{ 559286441Srpaulo 560286441Srpaulo IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 561286441Srpaulo return (iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 562286441Srpaulo IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 563286441Srpaulo IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 564286441Srpaulo 1000)); 565286441Srpaulo} 566