1/* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3/* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90/*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105#include <sys/cdefs.h> 106__FBSDID("$FreeBSD: releng/11.0/sys/dev/iwm/if_iwm_pcie_trans.c 303628 2016-08-01 17:51:35Z sbruno $"); 107 108#include "opt_wlan.h" 109 110#include <sys/param.h> 111#include <sys/bus.h> 112#include <sys/conf.h> 113#include <sys/endian.h> 114#include <sys/firmware.h> 115#include <sys/kernel.h> 116#include <sys/malloc.h> 117#include <sys/mbuf.h> 118#include <sys/mutex.h> 119#include <sys/module.h> 120#include <sys/proc.h> 121#include <sys/rman.h> 122#include <sys/socket.h> 123#include <sys/sockio.h> 124#include <sys/sysctl.h> 125#include <sys/linker.h> 126 127#include <machine/bus.h> 128#include <machine/endian.h> 129#include <machine/resource.h> 130 131#include <dev/pci/pcivar.h> 132#include <dev/pci/pcireg.h> 133 134#include <net/bpf.h> 135 136#include <net/if.h> 137#include <net/if_var.h> 138#include <net/if_arp.h> 139#include <net/if_dl.h> 140#include <net/if_media.h> 141#include <net/if_types.h> 142 143#include <netinet/in.h> 144#include <netinet/in_systm.h> 145#include <netinet/if_ether.h> 146#include <netinet/ip.h> 147 148#include <net80211/ieee80211_var.h> 149#include <net80211/ieee80211_regdomain.h> 150#include <net80211/ieee80211_ratectl.h> 151#include <net80211/ieee80211_radiotap.h> 152 153#include <dev/iwm/if_iwmreg.h> 154#include <dev/iwm/if_iwmvar.h> 155#include <dev/iwm/if_iwm_debug.h> 156#include <dev/iwm/if_iwm_pcie_trans.h> 157 158/* 159 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 160 * The rest can be migrated out into here once they're no longer in 161 * if_iwm.c. 162 */ 163 164/* 165 * basic device access 166 */ 167 168uint32_t 169iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 170{ 171 IWM_WRITE(sc, 172 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 173 IWM_BARRIER_READ_WRITE(sc); 174 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 175} 176 177void 178iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 179{ 180 IWM_WRITE(sc, 181 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 182 IWM_BARRIER_WRITE(sc); 183 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 184} 185 186#ifdef IWM_DEBUG 187/* iwlwifi: pcie/trans.c */ 188int 189iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 190{ 191 int offs, ret = 0; 192 uint32_t *vals = buf; 193 194 if (iwm_nic_lock(sc)) { 195 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 196 for (offs = 0; offs < dwords; offs++) 197 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 198 iwm_nic_unlock(sc); 199 } else { 200 ret = EBUSY; 201 } 202 return ret; 203} 204#endif 205 206/* iwlwifi: pcie/trans.c */ 207int 208iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 209{ 210 int offs; 211 const uint32_t *vals = buf; 212 213 if (iwm_nic_lock(sc)) { 214 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 215 /* WADDR auto-increments */ 216 for (offs = 0; offs < dwords; offs++) { 217 uint32_t val = vals ? vals[offs] : 0; 218 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 219 } 220 iwm_nic_unlock(sc); 221 } else { 222 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 223 "%s: write_mem failed\n", __func__); 224 return EBUSY; 225 } 226 return 0; 227} 228 229int 230iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 231{ 232 return iwm_write_mem(sc, addr, &val, 1); 233} 234 235int 236iwm_poll_bit(struct iwm_softc *sc, int reg, 237 uint32_t bits, uint32_t mask, int timo) 238{ 239 for (;;) { 240 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 241 return 1; 242 } 243 if (timo < 10) { 244 return 0; 245 } 246 timo -= 10; 247 DELAY(10); 248 } 249} 250 251int 252iwm_nic_lock(struct iwm_softc *sc) 253{ 254 int rv = 0; 255 256 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 257 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 258 259 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) 260 DELAY(2); 261 262 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 263 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 264 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 265 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 266 rv = 1; 267 } else { 268 /* jolt */ 269 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 270 "%s: resetting device via NMI\n", __func__); 271 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 272 } 273 274 return rv; 275} 276 277void 278iwm_nic_unlock(struct iwm_softc *sc) 279{ 280 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 281 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 282} 283 284void 285iwm_set_bits_mask_prph(struct iwm_softc *sc, 286 uint32_t reg, uint32_t bits, uint32_t mask) 287{ 288 uint32_t val; 289 290 /* XXX: no error path? */ 291 if (iwm_nic_lock(sc)) { 292 val = iwm_read_prph(sc, reg) & mask; 293 val |= bits; 294 iwm_write_prph(sc, reg, val); 295 iwm_nic_unlock(sc); 296 } 297} 298 299void 300iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 301{ 302 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 303} 304 305void 306iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 307{ 308 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 309} 310 311/* 312 * High-level hardware frobbing routines 313 */ 314 315void 316iwm_enable_rfkill_int(struct iwm_softc *sc) 317{ 318 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 319 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 320} 321 322int 323iwm_check_rfkill(struct iwm_softc *sc) 324{ 325 uint32_t v; 326 int rv; 327 328 /* 329 * "documentation" is not really helpful here: 330 * 27: HW_RF_KILL_SW 331 * Indicates state of (platform's) hardware RF-Kill switch 332 * 333 * But apparently when it's off, it's on ... 334 */ 335 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 336 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 337 if (rv) { 338 sc->sc_flags |= IWM_FLAG_RFKILL; 339 } else { 340 sc->sc_flags &= ~IWM_FLAG_RFKILL; 341 } 342 343 return rv; 344} 345 346 347#define IWM_HW_READY_TIMEOUT 50 348int 349iwm_set_hw_ready(struct iwm_softc *sc) 350{ 351 int ready; 352 353 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 354 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 355 356 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 357 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 358 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 359 IWM_HW_READY_TIMEOUT); 360 if (ready) { 361 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG, 362 IWM_CSR_MBOX_SET_REG_OS_ALIVE); 363 } 364 return ready; 365} 366#undef IWM_HW_READY_TIMEOUT 367 368int 369iwm_prepare_card_hw(struct iwm_softc *sc) 370{ 371 int rv = 0; 372 int t = 0; 373 374 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 375 if (iwm_set_hw_ready(sc)) 376 goto out; 377 378 DELAY(100); 379 380 /* If HW is not ready, prepare the conditions to check again */ 381 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 382 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 383 384 do { 385 if (iwm_set_hw_ready(sc)) 386 goto out; 387 DELAY(200); 388 t += 200; 389 } while (t < 150000); 390 391 rv = ETIMEDOUT; 392 393 out: 394 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 395 return rv; 396} 397 398void 399iwm_apm_config(struct iwm_softc *sc) 400{ 401 uint16_t reg; 402 403 reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg)); 404 if (reg & PCIEM_LINK_CTL_ASPMC_L1) { 405 /* Um the Linux driver prints "Disabling L0S for this one ... */ 406 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 407 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 408 } else { 409 /* ... and "Enabling" here */ 410 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 411 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 412 } 413} 414 415/* 416 * Start up NIC's basic functionality after it has been reset 417 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 418 * NOTE: This does not load uCode nor start the embedded processor 419 */ 420int 421iwm_apm_init(struct iwm_softc *sc) 422{ 423 int error = 0; 424 425 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 426 427 /* Disable L0S exit timer (platform NMI Work/Around) */ 428 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) { 429 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 430 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 431 } 432 433 /* 434 * Disable L0s without affecting L1; 435 * don't wait for ICH L0s (ICH bug W/A) 436 */ 437 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 438 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 439 440 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 441 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 442 443 /* 444 * Enable HAP INTA (interrupt from management bus) to 445 * wake device's PCI Express link L1a -> L0s 446 */ 447 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 448 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 449 450 iwm_apm_config(sc); 451 452#if 0 /* not for 7k/8k */ 453 /* Configure analog phase-lock-loop before activating to D0A */ 454 if (trans->cfg->base_params->pll_cfg_val) 455 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 456 trans->cfg->base_params->pll_cfg_val); 457#endif 458 459 /* 460 * Set "initialization complete" bit to move adapter from 461 * D0U* --> D0A* (powered-up active) state. 462 */ 463 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 464 465 /* 466 * Wait for clock stabilization; once stabilized, access to 467 * device-internal resources is supported, e.g. iwm_write_prph() 468 * and accesses to uCode SRAM. 469 */ 470 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 471 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 472 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 473 device_printf(sc->sc_dev, 474 "timeout waiting for clock stabilization\n"); 475 error = ETIMEDOUT; 476 goto out; 477 } 478 479 if (sc->host_interrupt_operation_mode) { 480 /* 481 * This is a bit of an abuse - This is needed for 7260 / 3160 482 * only check host_interrupt_operation_mode even if this is 483 * not related to host_interrupt_operation_mode. 484 * 485 * Enable the oscillator to count wake up time for L1 exit. This 486 * consumes slightly more power (100uA) - but allows to be sure 487 * that we wake up from L1 on time. 488 * 489 * This looks weird: read twice the same register, discard the 490 * value, set a bit, and yet again, read that same register 491 * just to discard the value. But that's the way the hardware 492 * seems to like it. 493 */ 494 iwm_read_prph(sc, IWM_OSC_CLK); 495 iwm_read_prph(sc, IWM_OSC_CLK); 496 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 497 iwm_read_prph(sc, IWM_OSC_CLK); 498 iwm_read_prph(sc, IWM_OSC_CLK); 499 } 500 501 /* 502 * Enable DMA clock and wait for it to stabilize. 503 * 504 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 505 * do not disable clocks. This preserves any hardware bits already 506 * set by default in "CLK_CTRL_REG" after reset. 507 */ 508 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 509 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, 510 IWM_APMG_CLK_VAL_DMA_CLK_RQT); 511 DELAY(20); 512 513 /* Disable L1-Active */ 514 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 515 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 516 517 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 518 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 519 IWM_APMG_RTC_INT_STT_RFKILL); 520 } 521 out: 522 if (error) 523 device_printf(sc->sc_dev, "apm init error %d\n", error); 524 return error; 525} 526 527/* iwlwifi/pcie/trans.c */ 528void 529iwm_apm_stop(struct iwm_softc *sc) 530{ 531 /* stop device's busmaster DMA activity */ 532 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 533 534 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 535 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 536 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 537 device_printf(sc->sc_dev, "timeout waiting for master\n"); 538 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 539} 540 541/* iwlwifi pcie/trans.c */ 542int 543iwm_start_hw(struct iwm_softc *sc) 544{ 545 int error; 546 547 if ((error = iwm_prepare_card_hw(sc)) != 0) 548 return error; 549 550 /* Reset the entire device */ 551 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 552 DELAY(10); 553 554 if ((error = iwm_apm_init(sc)) != 0) 555 return error; 556 557 iwm_enable_rfkill_int(sc); 558 iwm_check_rfkill(sc); 559 560 return 0; 561} 562 563/* iwlwifi pcie/trans.c (always main power) */ 564void 565iwm_set_pwr(struct iwm_softc *sc) 566{ 567 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 568 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 569} 570 571/* iwlwifi pcie/rx.c */ 572int 573iwm_pcie_rx_stop(struct iwm_softc *sc) 574{ 575 576 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 577 return (iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 578 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 579 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 580 1000)); 581} 582