1/*- 2 * Copyright (c) 2005, Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/11.0/sys/dev/hwpmc/hwpmc_amd.h 184802 2008-11-09 17:37:54Z jkoshy $ 27 */ 28 29/* Machine dependent interfaces */ 30 31#ifndef _DEV_HWPMC_AMD_H_ 32#define _DEV_HWPMC_AMD_H_ 1 33 34/* AMD K7 and K8 PMCs */ 35 36#define AMD_PMC_EVSEL_0 0xC0010000 37#define AMD_PMC_EVSEL_1 0xC0010001 38#define AMD_PMC_EVSEL_2 0xC0010002 39#define AMD_PMC_EVSEL_3 0xC0010003 40 41#define AMD_PMC_PERFCTR_0 0xC0010004 42#define AMD_PMC_PERFCTR_1 0xC0010005 43#define AMD_PMC_PERFCTR_2 0xC0010006 44#define AMD_PMC_PERFCTR_3 0xC0010007 45 46 47#define AMD_NPMCS 4 48 49#define AMD_PMC_COUNTERMASK 0xFF000000 50#define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 51#define AMD_PMC_INVERT (1 << 23) 52#define AMD_PMC_ENABLE (1 << 22) 53#define AMD_PMC_INT (1 << 20) 54#define AMD_PMC_PC (1 << 19) 55#define AMD_PMC_EDGE (1 << 18) 56#define AMD_PMC_OS (1 << 17) 57#define AMD_PMC_USR (1 << 16) 58 59#define AMD_PMC_UNITMASK_M 0x10 60#define AMD_PMC_UNITMASK_O 0x08 61#define AMD_PMC_UNITMASK_E 0x04 62#define AMD_PMC_UNITMASK_S 0x02 63#define AMD_PMC_UNITMASK_I 0x01 64#define AMD_PMC_UNITMASK_MOESI 0x1F 65 66#define AMD_PMC_UNITMASK 0xFF00 67#define AMD_PMC_EVENTMASK 0x00FF 68 69#define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 70#define AMD_PMC_TO_EVENTMASK(x) ((x) & 0xFF) 71#define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 72 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 73 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 74 75#define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 76 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 77 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 78 79#define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 80#define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 81 82#define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 83#define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 84 85struct pmc_md_amd_op_pmcallocate { 86 uint32_t pm_amd_config; 87}; 88 89#ifdef _KERNEL 90 91/* MD extension for 'struct pmc' */ 92struct pmc_md_amd_pmc { 93 uint32_t pm_amd_evsel; 94}; 95 96#endif /* _KERNEL */ 97#endif /* _DEV_HWPMC_AMD_H_ */ 98