if_gemreg.h revision 170273
1139749Simp/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 391398Stmm * All rights reserved. 491398Stmm * 591398Stmm * 691398Stmm * Redistribution and use in source and binary forms, with or without 791398Stmm * modification, are permitted provided that the following conditions 891398Stmm * are met: 991398Stmm * 1. Redistributions of source code must retain the above copyright 1091398Stmm * notice, this list of conditions and the following disclaimer. 1191398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1291398Stmm * notice, this list of conditions and the following disclaimer in the 1391398Stmm * documentation and/or other materials provided with the distribution. 1491398Stmm * 1591398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1691398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1791398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1891398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1991398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2091398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2191398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2291398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2391398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2491398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2591398Stmm * SUCH DAMAGE. 2691398Stmm * 2799726Sbenno * from: NetBSD: gemreg.h,v 1.15 2002/05/11 00:36:02 matt Exp 2891398Stmm * 2991398Stmm * $FreeBSD: head/sys/dev/gem/if_gemreg.h 170273 2007-06-04 06:01:04Z yongari $ 3091398Stmm */ 3191398Stmm 3291398Stmm#ifndef _IF_GEMREG_H 3391398Stmm#define _IF_GEMREG_H 3491398Stmm 3591398Stmm/* Register definitions for Sun GEM gigabit ethernet */ 3691398Stmm 3791398Stmm#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 3891398Stmm#define GEM_CONFIG 0x0004 /* config reg */ 3991398Stmm#define GEM_STATUS 0x000c /* status reg */ 4091398Stmm/* Note: Reading the status reg clears bits 0-6 */ 4191398Stmm#define GEM_INTMASK 0x0010 4291398Stmm#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 4391398Stmm#define GEM_STATUS_ALIAS 0x001c 4491398Stmm/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 4591398Stmm#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 4691398Stmm#define GEM_ERROR_MASK 0x1004 4791398Stmm#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 4891398Stmm#define GEM_BIF_DIAG 0x100c 4991398Stmm#define GEM_RESET 0x1010 /* Software reset register */ 5091398Stmm 5191398Stmm 5291398Stmm/* Bits in GEM_SEB register */ 5391398Stmm#define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 5491398Stmm#define GEM_SEB_RXWON 0x000000004 5591398Stmm 5691398Stmm 5791398Stmm/* Bits in GEM_CONFIG register */ 5891398Stmm#define GEM_CONFIG_BURST_64 0x000000000 /* 0->infininte, 1->64KB */ 5991398Stmm#define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infininte, 1->64KB */ 6091398Stmm#define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 6191398Stmm#define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 6291398Stmm 6391398Stmm#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 6491398Stmm#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 6591398Stmm 6691398Stmm 6791398Stmm/* Top part of GEM_STATUS has TX completion information */ 6891398Stmm#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 6991398Stmm 7091398Stmm 7191398Stmm/* Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. */ 7291398Stmm#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 7391398Stmm#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 7491398Stmm#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 7591398Stmm#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 7691398Stmm#define GEM_INTR_RX_NOBUF 0x000000020 7791398Stmm#define GEM_INTR_RX_TAG_ERR 0x000000040 7891398Stmm#define GEM_INTR_PCS 0x000002000 7991398Stmm#define GEM_INTR_TX_MAC 0x000004000 8091398Stmm#define GEM_INTR_RX_MAC 0x000008000 8191398Stmm#define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 8291398Stmm#define GEM_INTR_MIF 0x000020000 8391398Stmm#define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 8491398Stmm#define GEM_INTR_BITS "\177\020" \ 8591398Stmm "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 8691398Stmm "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 8791398Stmm "b\15PCS\0b\16TXMAC\0b\17RXMAC\0" \ 8891398Stmm "b\20MAC_CONTROL\0b\21MIF\0b\22BERR\0\0" \ 8991398Stmm 9091398Stmm 9191398Stmm 9291398Stmm/* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */ 9391398Stmm#define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 9491398Stmm#define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 9591398Stmm#define GEM_ERROR_STAT_OTHERS 0x000000004 9691398Stmm 9791398Stmm 9891398Stmm/* GEM_BIF_CONFIG register bits */ 9991398Stmm#define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 10091398Stmm#define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 10191398Stmm#define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 10291398Stmm#define GEM_BIF_CONFIG_M66EN 0x000000008 10391398Stmm 10491398Stmm 10591398Stmm/* GEM_RESET register bits -- TX and RX self clear when complete. */ 10691398Stmm#define GEM_RESET_TX 0x000000001 /* Reset TX half */ 10791398Stmm#define GEM_RESET_RX 0x000000002 /* Reset RX half */ 10891398Stmm#define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 10991398Stmm 11091398Stmm 11191398Stmm/* GEM TX DMA registers */ 11291398Stmm#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 11391398Stmm#define GEM_TX_CONFIG 0x2004 11491398Stmm#define GEM_TX_RING_PTR_LO 0x2008 11591398Stmm#define GEM_TX_RING_PTR_HI 0x200c 11691398Stmm 11791398Stmm#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 11891398Stmm#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 11991398Stmm#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 12091398Stmm#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 12191398Stmm#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 12291398Stmm 12391398Stmm#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 12491398Stmm#define GEM_TX_DATA_PTR_LO 0x2030 12591398Stmm#define GEM_TX_DATA_PTR_HI 0x2034 12691398Stmm 12791398Stmm#define GEM_TX_COMPLETION 0x2100 12891398Stmm#define GEM_TX_FIFO_ADDRESS 0x2104 12991398Stmm#define GEM_TX_FIFO_TAG 0x2108 13091398Stmm#define GEM_TX_FIFO_DATA_LO 0x210c 13191398Stmm#define GEM_TX_FIFO_DATA_HI_T1 0x2110 13291398Stmm#define GEM_TX_FIFO_DATA_HI_T0 0x2114 13391398Stmm#define GEM_TX_FIFO_SIZE 0x2118 13491398Stmm#define GEM_TX_DEBUG 0x3028 13591398Stmm 13691398Stmm 13791398Stmm/* GEM_TX_CONFIG register bits. */ 13891398Stmm#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 13991398Stmm#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 14091398Stmm#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 14191398Stmm#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 14291398Stmm 14391398Stmm#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 14491398Stmm#define GEM_RING_SZ_64 (1<<1) 14591398Stmm#define GEM_RING_SZ_128 (2<<1) 14691398Stmm#define GEM_RING_SZ_256 (3<<1) 14791398Stmm#define GEM_RING_SZ_512 (4<<1) 14891398Stmm#define GEM_RING_SZ_1024 (5<<1) 14991398Stmm#define GEM_RING_SZ_2048 (6<<1) 15091398Stmm#define GEM_RING_SZ_4096 (7<<1) 15191398Stmm#define GEM_RING_SZ_8192 (8<<1) 15291398Stmm 15391398Stmm 15491398Stmm/* GEM_TX_COMPLETION register bits */ 15591398Stmm#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 15691398Stmm 15791398Stmm 15891398Stmm/* GEM RX DMA registers */ 15991398Stmm#define GEM_RX_CONFIG 0x4000 16091398Stmm#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 16191398Stmm#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 16291398Stmm 16391398Stmm#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 16491398Stmm#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 16591398Stmm#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 16691398Stmm#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 16791398Stmm 16891398Stmm#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 16991398Stmm#define GEM_RX_PAUSE_THRESH 0x4020 17091398Stmm 17191398Stmm#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 17291398Stmm#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 17391398Stmm 17491398Stmm#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 17591398Stmm#define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 17691398Stmm#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 17791398Stmm 17891398Stmm#define GEM_RX_FIFO_ADDRESS 0x410c 17991398Stmm#define GEM_RX_FIFO_TAG 0x4110 18091398Stmm#define GEM_RX_FIFO_DATA_LO 0x4114 18191398Stmm#define GEM_RX_FIFO_DATA_HI_T1 0x4118 18291398Stmm#define GEM_RX_FIFO_DATA_HI_T0 0x411c 18391398Stmm#define GEM_RX_FIFO_SIZE 0x4120 18491398Stmm 18591398Stmm 18691398Stmm/* GEM_RX_CONFIG register bits. */ 18791398Stmm#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 18891398Stmm#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 18991398Stmm#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 19091398Stmm#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 19191398Stmm#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* checksum start offset */ 19291398Stmm#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 19391398Stmm 19491398Stmm#define GEM_THRSH_64 0 19591398Stmm#define GEM_THRSH_128 1 19691398Stmm#define GEM_THRSH_256 2 19791398Stmm#define GEM_THRSH_512 3 19891398Stmm#define GEM_THRSH_1024 4 19991398Stmm#define GEM_THRSH_2048 5 20091398Stmm 20191398Stmm#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 20291398Stmm#define GEM_RX_CONFIG_FBOFF_SHFT 10 20391398Stmm#define GEM_RX_CONFIG_CXM_START_SHFT 13 20491398Stmm 20591398Stmm 20691398Stmm/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 20791398Stmm#define GEM_RX_PTH_XOFF_THRESH 0x000001ff 20899726Sbenno#define GEM_RX_PTH_XON_THRESH 0x001ff000 20991398Stmm 21091398Stmm 21191398Stmm/* GEM_RX_BLANKING register bits */ 21291398Stmm#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 21399726Sbenno#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 21499726Sbenno#define GEM_RX_BLANKING_TIME_SHIFT 12 21599726Sbenno/* One tick is 2048 PCI clocks, or 16us at 66MHz */ 21691398Stmm 21791398Stmm 21891398Stmm/* GEM_MAC registers */ 21991398Stmm#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 22091398Stmm#define GEM_MAC_RXRESET 0x6004 /* ditto */ 22191398Stmm#define GEM_MAC_SEND_PAUSE_CMD 0x6008 22291398Stmm#define GEM_MAC_TX_STATUS 0x6010 22391398Stmm#define GEM_MAC_RX_STATUS 0x6014 22491398Stmm#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 22591398Stmm#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 22691398Stmm#define GEM_MAC_RX_MASK 0x6024 22791398Stmm#define GEM_MAC_CONTROL_MASK 0x6028 22891398Stmm#define GEM_MAC_TX_CONFIG 0x6030 22991398Stmm#define GEM_MAC_RX_CONFIG 0x6034 23091398Stmm#define GEM_MAC_CONTROL_CONFIG 0x6038 23191398Stmm#define GEM_MAC_XIF_CONFIG 0x603c 23291398Stmm#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 23391398Stmm#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 23491398Stmm#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 23591398Stmm#define GEM_MAC_SLOT_TIME 0x604c 23691398Stmm#define GEM_MAC_MAC_MIN_FRAME 0x6050 23791398Stmm#define GEM_MAC_MAC_MAX_FRAME 0x6054 23891398Stmm#define GEM_MAC_PREAMBLE_LEN 0x6058 23991398Stmm#define GEM_MAC_JAM_SIZE 0x605c 24091398Stmm#define GEM_MAC_ATTEMPT_LIMIT 0x6060 24191398Stmm#define GEM_MAC_CONTROL_TYPE 0x6064 24291398Stmm 24391398Stmm#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 24491398Stmm#define GEM_MAC_ADDR1 0x6084 24591398Stmm#define GEM_MAC_ADDR2 0x6088 24691398Stmm#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 24791398Stmm#define GEM_MAC_ADDR4 0x6090 24891398Stmm#define GEM_MAC_ADDR5 0x6094 24991398Stmm#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 25091398Stmm#define GEM_MAC_ADDR7 0x609c 25191398Stmm#define GEM_MAC_ADDR8 0x60a0 25291398Stmm 25391398Stmm#define GEM_MAC_ADDR_FILTER0 0x60a4 25491398Stmm#define GEM_MAC_ADDR_FILTER1 0x60a8 25591398Stmm#define GEM_MAC_ADDR_FILTER2 0x60ac 25691398Stmm#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 25791398Stmm#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 25891398Stmm 25991398Stmm#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 26091398Stmm#define GEM_MAC_HASH1 0x60c4 26191398Stmm#define GEM_MAC_HASH2 0x60c8 26291398Stmm#define GEM_MAC_HASH3 0x60cc 26391398Stmm#define GEM_MAC_HASH4 0x60d0 26491398Stmm#define GEM_MAC_HASH5 0x60d4 26591398Stmm#define GEM_MAC_HASH6 0x60d8 26691398Stmm#define GEM_MAC_HASH7 0x60dc 26791398Stmm#define GEM_MAC_HASH8 0x60e0 26891398Stmm#define GEM_MAC_HASH9 0x60e4 26991398Stmm#define GEM_MAC_HASH10 0x60e8 27091398Stmm#define GEM_MAC_HASH11 0x60ec 27191398Stmm#define GEM_MAC_HASH12 0x60f0 27291398Stmm#define GEM_MAC_HASH13 0x60f4 27391398Stmm#define GEM_MAC_HASH14 0x60f8 27491398Stmm#define GEM_MAC_HASH15 0x60fc 27591398Stmm 27691398Stmm#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 27791398Stmm#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 27891398Stmm#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 27991398Stmm#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 28091398Stmm#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 28191398Stmm#define GEM_MAC_PEAK_ATTEMPTS 0x6114 28291398Stmm#define GEM_MAC_RX_FRAME_COUNT 0x6118 28391398Stmm#define GEM_MAC_RX_LEN_ERR_CNT 0x611c 28491398Stmm#define GEM_MAC_RX_ALIGN_ERR 0x6120 28591398Stmm#define GEM_MAC_RX_CRC_ERR_CNT 0x6124 28691398Stmm#define GEM_MAC_RX_CODE_VIOL 0x6128 28791398Stmm#define GEM_MAC_RANDOM_SEED 0x6130 28891398Stmm#define GEM_MAC_MAC_STATE 0x6134 /* MAC sstate machine reg */ 28991398Stmm 29091398Stmm 29191398Stmm/* GEM_MAC_SEND_PAUSE_CMD register bits */ 29291398Stmm#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 29391398Stmm#define GEM_MAC_PAUSE_CMD_SEND 0x00010000 29491398Stmm 29591398Stmm 29691398Stmm/* GEM_MAC_TX_STATUS and _MASK register bits */ 29791398Stmm#define GEM_MAC_TX_XMIT_DONE 0x00000001 29891398Stmm#define GEM_MAC_TX_UNDERRUN 0x00000002 29991398Stmm#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 30091398Stmm#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 30191398Stmm#define GEM_MAC_TX_ECC_EXP 0x00000010 30291398Stmm#define GEM_MAC_TX_LCC_EXP 0x00000020 30391398Stmm#define GEM_MAC_TX_FCC_EXP 0x00000040 30491398Stmm#define GEM_MAC_TX_DEFER_EXP 0x00000080 30591398Stmm#define GEM_MAC_TX_PEAK_EXP 0x00000100 30691398Stmm 30791398Stmm 30891398Stmm/* GEM_MAC_RX_STATUS and _MASK register bits */ 30991398Stmm#define GEM_MAC_RX_DONE 0x00000001 31091398Stmm#define GEM_MAC_RX_OVERFLOW 0x00000002 31191398Stmm#define GEM_MAC_RX_FRAME_CNT 0x00000004 31291398Stmm#define GEM_MAC_RX_ALIGN_EXP 0x00000008 31391398Stmm#define GEM_MAC_RX_CRC_EXP 0x00000010 31491398Stmm#define GEM_MAC_RX_LEN_EXP 0x00000020 31591398Stmm#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 31691398Stmm 31791398Stmm 31891398Stmm/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 31991398Stmm#define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 32091398Stmm#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 32191398Stmm#define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 32291398Stmm#define GEM_MAC_PAUSE_TIME 0xffff0000 32391398Stmm 32491398Stmm/* GEM_MAC_XIF_CONFIG register bits */ 32591398Stmm#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 32691398Stmm#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 32791398Stmm#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 32899726Sbenno#define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 32991398Stmm#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 33091398Stmm#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 33191398Stmm#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 33291398Stmm 33391398Stmm/* GEM_MAC_TX_CONFIG register bits */ 33491398Stmm#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 33591398Stmm#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 33691398Stmm#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collitions */ 33791398Stmm#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 33891398Stmm#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 33991398Stmm#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 34091398Stmm#define GEM_MAC_TX_NO_BACKOFF 0x00000040 34191398Stmm#define GEM_MAC_TX_SLOWDOWN 0x00000080 34291398Stmm#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 34391398Stmm#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 34491398Stmm/* Carrier Extension is required for half duplex Gbps operation */ 34591398Stmm 34691398Stmm 34791398Stmm/* GEM_MAC_RX_CONFIG register bits */ 34891398Stmm#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 34991398Stmm#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 35091398Stmm#define GEM_MAC_RX_STRIP_CRC 0x00000004 35191398Stmm#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 35291398Stmm#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 35391398Stmm#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 35491398Stmm#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 35591398Stmm#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 35691398Stmm#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 35791398Stmm/* 35891398Stmm * Carrier Extension enables reception of packet bursts generated by 35991398Stmm * senders with carrier extension enabled. 36091398Stmm */ 36191398Stmm 36291398Stmm 36391398Stmm/* GEM_MAC_CONTROL_CONFIG bits */ 36491398Stmm#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 36591398Stmm#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 36691398Stmm#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 36791398Stmm 36891398Stmm 36991398Stmm/* GEM MIF registers */ 37091398Stmm/* Bit bang registers use low bit only */ 37191398Stmm#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 37291398Stmm#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 37391398Stmm#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 37491398Stmm#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 37591398Stmm#define GEM_MIF_CONFIG 0x6210 37691398Stmm#define GEM_MIF_INTERRUPT_MASK 0x6214 37791398Stmm#define GEM_MIF_BASIC_STATUS 0x6218 37891398Stmm#define GEM_MIF_STATE_MACHINE 0x621c 37991398Stmm 38091398Stmm 38191398Stmm/* GEM_MIF_FRAME bits */ 38291398Stmm#define GEM_MIF_FRAME_DATA 0x0000ffff 38391398Stmm#define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 38491398Stmm#define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 38591398Stmm#define GEM_MIF_FRAME_REG_ADDR 0x007c0000 38691398Stmm#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */ 38791398Stmm#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 38891398Stmm#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 38991398Stmm 39091398Stmm#define GEM_MIF_FRAME_READ 0x60020000 39191398Stmm#define GEM_MIF_FRAME_WRITE 0x50020000 39291398Stmm 39391398Stmm#define GEM_MIF_REG_SHIFT 18 39491398Stmm#define GEM_MIF_PHY_SHIFT 23 39591398Stmm 39691398Stmm 39791398Stmm/* GEM_MIF_CONFIG register bits */ 39891398Stmm#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select */ 39991398Stmm#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 40091398Stmm#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 40191398Stmm#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 40291398Stmm#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 40391398Stmm#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 40491398Stmm#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 40591398Stmm/* MDI0 is onboard tranciever MID1 is external, PHYAD for both is 0 */ 40691398Stmm 40791398Stmm 40891398Stmm/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 40991398Stmm#define GEM_MIF_STATUS 0x0000ffff 41091398Stmm#define GEM_MIF_BASIC 0xffff0000 41191398Stmm/* 41291398Stmm * The Basic part is the last value read in the POLL field of the config 41391398Stmm * register. 41491398Stmm * 41591398Stmm * The status part indicates the bits that have changed. 41691398Stmm */ 41791398Stmm 41891398Stmm 41991398Stmm/* The GEM PCS/Serial link register. */ 42091398Stmm#define GEM_MII_CONTROL 0x9000 42191398Stmm#define GEM_MII_STATUS 0x9004 42291398Stmm#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 42391398Stmm#define GEM_MII_ANLPAR 0x900c /* LP ability reg */ 42491398Stmm#define GEM_MII_CONFIG 0x9010 42591398Stmm#define GEM_MII_STATE_MACHINE 0x9014 42691398Stmm#define GEM_MII_INTERRUP_STATUS 0x9018 42791398Stmm#define GEM_MII_DATAPATH_MODE 0x9050 42891398Stmm#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 42991398Stmm#define GEM_MII_OUTPUT_SELECT 0x9058 43091398Stmm#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */ 43191398Stmm 43291398Stmm 43391398Stmm/* GEM_MII_CONTROL bits */ 43491398Stmm/* 43591398Stmm * DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS. 43691398Stmm */ 43791398Stmm#define GEM_MII_CONTROL_RESET 0x00008000 43891398Stmm#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 43991398Stmm#define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */ 44091398Stmm#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 44191398Stmm#define GEM_MII_CONTROL_POWERDN 0x00000800 44291398Stmm#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */ 44391398Stmm#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotioation */ 44491398Stmm#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 44591398Stmm#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 44691398Stmm 44791398Stmm 44891398Stmm/* GEM_MII_STATUS reg */ 44991398Stmm#define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 45091398Stmm#define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 45191398Stmm#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ 45291398Stmm#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 45391398Stmm#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ 45491398Stmm#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 45591398Stmm#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 45691398Stmm#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ 45791398Stmm 45891398Stmm 45991398Stmm/* GEM_MII_ANAR and GEM_MII_ANLAR reg bits */ 46091398Stmm#define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ 46191398Stmm#define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ 46291398Stmm /* Link Partner Capability */ 46391398Stmm#define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */ 46491398Stmm#define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */ 46591398Stmm#define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ 46691398Stmm#define GEM_MII_ANEG_HLF_DUPLX 0x00000040 46791398Stmm#define GEM_MII_ANEG_FUL_DUPLX 0x00000020 46891398Stmm 46991398Stmm 47091398Stmm/* GEM_MII_CONFIG reg */ 47191398Stmm#define GEM_MII_CONFIG_TIMER 0x0000001c /* link monitor timer values */ 47291398Stmm#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 47391398Stmm 47491398Stmm 47591398Stmm/* GEM_MII_DATAPATH_MODE reg */ 47691398Stmm#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ 47791398Stmm#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 47891398Stmm#define GEM_MII_DATAPATH_MII 0x00000004 /* Use MII, not PCS */ 47991398Stmm#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ 48091398Stmm 48191398Stmm 48291398Stmm/* GEM_MII_SLINK_CONTROL reg */ 48391398Stmm#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl */ 48491398Stmm#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 48591398Stmm#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 48691398Stmm#define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ 48791398Stmm#define GEM_MII_SLINK_SELFTEST 0x000001c0 48891398Stmm#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ 48991398Stmm 49091398Stmm 49191398Stmm/* GEM_MII_SLINK_STATUS reg */ 49291398Stmm#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 49391398Stmm#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 49491398Stmm#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 49591398Stmm#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 49691398Stmm 49791398Stmm 49891398Stmm/* Wired GEM PHY addresses */ 49991398Stmm#define GEM_PHYAD_INTERNAL 1 50091398Stmm#define GEM_PHYAD_EXTERNAL 0 50191398Stmm 50291398Stmm/* 50391398Stmm * GEM descriptor table structures. 50491398Stmm */ 50591398Stmmstruct gem_desc { 50691398Stmm uint64_t gd_flags; 50791398Stmm uint64_t gd_addr; 50891398Stmm}; 50991398Stmm 51091398Stmm/* Transmit flags */ 51191398Stmm#define GEM_TD_BUFSIZE 0x0000000000007fffLL 51291398Stmm#define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 513170273Syongari#define GEM_TD_CXSUM_STARTSHFT 15 51491398Stmm#define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 515170273Syongari#define GEM_TD_CXSUM_STUFFSHFT 21 51691398Stmm#define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 51791398Stmm#define GEM_TD_END_OF_PACKET 0x0000000040000000LL 51891398Stmm#define GEM_TD_START_OF_PACKET 0x0000000080000000LL 51991398Stmm#define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 52091398Stmm#define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 52191398Stmm/* 52291398Stmm * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 52391398Stmm * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 52491398Stmm */ 52591398Stmm 52691398Stmm/* Receive flags */ 52791398Stmm#define GEM_RD_CHECKSUM 0x000000000000ffffLL 52891398Stmm#define GEM_RD_BUFSIZE 0x000000007fff0000LL 52991398Stmm#define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 53091398Stmm#define GEM_RD_HASHVAL 0x0ffff00000000000LL 53191398Stmm#define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 53291398Stmm#define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 53391398Stmm#define GEM_RD_BAD_CRC 0x4000000000000000LL 53491398Stmm 53591398Stmm#define GEM_RD_BUFSHIFT 16 53691398Stmm#define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 53791398Stmm 53891398Stmm/* PCI support */ 53991398Stmm#define PCI_GEM_BASEADDR 0x10 54091398Stmm 54191398Stmm#endif 542