if_gemreg.h revision 170273
1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.15 2002/05/11 00:36:02 matt Exp 28 * 29 * $FreeBSD: head/sys/dev/gem/if_gemreg.h 170273 2007-06-04 06:01:04Z yongari $ 30 */ 31 32#ifndef _IF_GEMREG_H 33#define _IF_GEMREG_H 34 35/* Register definitions for Sun GEM gigabit ethernet */ 36 37#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 38#define GEM_CONFIG 0x0004 /* config reg */ 39#define GEM_STATUS 0x000c /* status reg */ 40/* Note: Reading the status reg clears bits 0-6 */ 41#define GEM_INTMASK 0x0010 42#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 43#define GEM_STATUS_ALIAS 0x001c 44/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 45#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 46#define GEM_ERROR_MASK 0x1004 47#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 48#define GEM_BIF_DIAG 0x100c 49#define GEM_RESET 0x1010 /* Software reset register */ 50 51 52/* Bits in GEM_SEB register */ 53#define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 54#define GEM_SEB_RXWON 0x000000004 55 56 57/* Bits in GEM_CONFIG register */ 58#define GEM_CONFIG_BURST_64 0x000000000 /* 0->infininte, 1->64KB */ 59#define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infininte, 1->64KB */ 60#define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 61#define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 62 63#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 64#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 65 66 67/* Top part of GEM_STATUS has TX completion information */ 68#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 69 70 71/* Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. */ 72#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 73#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 74#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 75#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 76#define GEM_INTR_RX_NOBUF 0x000000020 77#define GEM_INTR_RX_TAG_ERR 0x000000040 78#define GEM_INTR_PCS 0x000002000 79#define GEM_INTR_TX_MAC 0x000004000 80#define GEM_INTR_RX_MAC 0x000008000 81#define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 82#define GEM_INTR_MIF 0x000020000 83#define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 84#define GEM_INTR_BITS "\177\020" \ 85 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 86 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 87 "b\15PCS\0b\16TXMAC\0b\17RXMAC\0" \ 88 "b\20MAC_CONTROL\0b\21MIF\0b\22BERR\0\0" \ 89 90 91 92/* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */ 93#define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 94#define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 95#define GEM_ERROR_STAT_OTHERS 0x000000004 96 97 98/* GEM_BIF_CONFIG register bits */ 99#define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 100#define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 101#define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 102#define GEM_BIF_CONFIG_M66EN 0x000000008 103 104 105/* GEM_RESET register bits -- TX and RX self clear when complete. */ 106#define GEM_RESET_TX 0x000000001 /* Reset TX half */ 107#define GEM_RESET_RX 0x000000002 /* Reset RX half */ 108#define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 109 110 111/* GEM TX DMA registers */ 112#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 113#define GEM_TX_CONFIG 0x2004 114#define GEM_TX_RING_PTR_LO 0x2008 115#define GEM_TX_RING_PTR_HI 0x200c 116 117#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 118#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 119#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 120#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 121#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 122 123#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 124#define GEM_TX_DATA_PTR_LO 0x2030 125#define GEM_TX_DATA_PTR_HI 0x2034 126 127#define GEM_TX_COMPLETION 0x2100 128#define GEM_TX_FIFO_ADDRESS 0x2104 129#define GEM_TX_FIFO_TAG 0x2108 130#define GEM_TX_FIFO_DATA_LO 0x210c 131#define GEM_TX_FIFO_DATA_HI_T1 0x2110 132#define GEM_TX_FIFO_DATA_HI_T0 0x2114 133#define GEM_TX_FIFO_SIZE 0x2118 134#define GEM_TX_DEBUG 0x3028 135 136 137/* GEM_TX_CONFIG register bits. */ 138#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 139#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 140#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 141#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 142 143#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 144#define GEM_RING_SZ_64 (1<<1) 145#define GEM_RING_SZ_128 (2<<1) 146#define GEM_RING_SZ_256 (3<<1) 147#define GEM_RING_SZ_512 (4<<1) 148#define GEM_RING_SZ_1024 (5<<1) 149#define GEM_RING_SZ_2048 (6<<1) 150#define GEM_RING_SZ_4096 (7<<1) 151#define GEM_RING_SZ_8192 (8<<1) 152 153 154/* GEM_TX_COMPLETION register bits */ 155#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 156 157 158/* GEM RX DMA registers */ 159#define GEM_RX_CONFIG 0x4000 160#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 161#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 162 163#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 164#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 165#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 166#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 167 168#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 169#define GEM_RX_PAUSE_THRESH 0x4020 170 171#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 172#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 173 174#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 175#define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 176#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 177 178#define GEM_RX_FIFO_ADDRESS 0x410c 179#define GEM_RX_FIFO_TAG 0x4110 180#define GEM_RX_FIFO_DATA_LO 0x4114 181#define GEM_RX_FIFO_DATA_HI_T1 0x4118 182#define GEM_RX_FIFO_DATA_HI_T0 0x411c 183#define GEM_RX_FIFO_SIZE 0x4120 184 185 186/* GEM_RX_CONFIG register bits. */ 187#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 188#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 189#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 190#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 191#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* checksum start offset */ 192#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 193 194#define GEM_THRSH_64 0 195#define GEM_THRSH_128 1 196#define GEM_THRSH_256 2 197#define GEM_THRSH_512 3 198#define GEM_THRSH_1024 4 199#define GEM_THRSH_2048 5 200 201#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 202#define GEM_RX_CONFIG_FBOFF_SHFT 10 203#define GEM_RX_CONFIG_CXM_START_SHFT 13 204 205 206/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 207#define GEM_RX_PTH_XOFF_THRESH 0x000001ff 208#define GEM_RX_PTH_XON_THRESH 0x001ff000 209 210 211/* GEM_RX_BLANKING register bits */ 212#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 213#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 214#define GEM_RX_BLANKING_TIME_SHIFT 12 215/* One tick is 2048 PCI clocks, or 16us at 66MHz */ 216 217 218/* GEM_MAC registers */ 219#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 220#define GEM_MAC_RXRESET 0x6004 /* ditto */ 221#define GEM_MAC_SEND_PAUSE_CMD 0x6008 222#define GEM_MAC_TX_STATUS 0x6010 223#define GEM_MAC_RX_STATUS 0x6014 224#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 225#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 226#define GEM_MAC_RX_MASK 0x6024 227#define GEM_MAC_CONTROL_MASK 0x6028 228#define GEM_MAC_TX_CONFIG 0x6030 229#define GEM_MAC_RX_CONFIG 0x6034 230#define GEM_MAC_CONTROL_CONFIG 0x6038 231#define GEM_MAC_XIF_CONFIG 0x603c 232#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 233#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 234#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 235#define GEM_MAC_SLOT_TIME 0x604c 236#define GEM_MAC_MAC_MIN_FRAME 0x6050 237#define GEM_MAC_MAC_MAX_FRAME 0x6054 238#define GEM_MAC_PREAMBLE_LEN 0x6058 239#define GEM_MAC_JAM_SIZE 0x605c 240#define GEM_MAC_ATTEMPT_LIMIT 0x6060 241#define GEM_MAC_CONTROL_TYPE 0x6064 242 243#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 244#define GEM_MAC_ADDR1 0x6084 245#define GEM_MAC_ADDR2 0x6088 246#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 247#define GEM_MAC_ADDR4 0x6090 248#define GEM_MAC_ADDR5 0x6094 249#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 250#define GEM_MAC_ADDR7 0x609c 251#define GEM_MAC_ADDR8 0x60a0 252 253#define GEM_MAC_ADDR_FILTER0 0x60a4 254#define GEM_MAC_ADDR_FILTER1 0x60a8 255#define GEM_MAC_ADDR_FILTER2 0x60ac 256#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 257#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 258 259#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 260#define GEM_MAC_HASH1 0x60c4 261#define GEM_MAC_HASH2 0x60c8 262#define GEM_MAC_HASH3 0x60cc 263#define GEM_MAC_HASH4 0x60d0 264#define GEM_MAC_HASH5 0x60d4 265#define GEM_MAC_HASH6 0x60d8 266#define GEM_MAC_HASH7 0x60dc 267#define GEM_MAC_HASH8 0x60e0 268#define GEM_MAC_HASH9 0x60e4 269#define GEM_MAC_HASH10 0x60e8 270#define GEM_MAC_HASH11 0x60ec 271#define GEM_MAC_HASH12 0x60f0 272#define GEM_MAC_HASH13 0x60f4 273#define GEM_MAC_HASH14 0x60f8 274#define GEM_MAC_HASH15 0x60fc 275 276#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 277#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 278#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 279#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 280#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 281#define GEM_MAC_PEAK_ATTEMPTS 0x6114 282#define GEM_MAC_RX_FRAME_COUNT 0x6118 283#define GEM_MAC_RX_LEN_ERR_CNT 0x611c 284#define GEM_MAC_RX_ALIGN_ERR 0x6120 285#define GEM_MAC_RX_CRC_ERR_CNT 0x6124 286#define GEM_MAC_RX_CODE_VIOL 0x6128 287#define GEM_MAC_RANDOM_SEED 0x6130 288#define GEM_MAC_MAC_STATE 0x6134 /* MAC sstate machine reg */ 289 290 291/* GEM_MAC_SEND_PAUSE_CMD register bits */ 292#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 293#define GEM_MAC_PAUSE_CMD_SEND 0x00010000 294 295 296/* GEM_MAC_TX_STATUS and _MASK register bits */ 297#define GEM_MAC_TX_XMIT_DONE 0x00000001 298#define GEM_MAC_TX_UNDERRUN 0x00000002 299#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 300#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 301#define GEM_MAC_TX_ECC_EXP 0x00000010 302#define GEM_MAC_TX_LCC_EXP 0x00000020 303#define GEM_MAC_TX_FCC_EXP 0x00000040 304#define GEM_MAC_TX_DEFER_EXP 0x00000080 305#define GEM_MAC_TX_PEAK_EXP 0x00000100 306 307 308/* GEM_MAC_RX_STATUS and _MASK register bits */ 309#define GEM_MAC_RX_DONE 0x00000001 310#define GEM_MAC_RX_OVERFLOW 0x00000002 311#define GEM_MAC_RX_FRAME_CNT 0x00000004 312#define GEM_MAC_RX_ALIGN_EXP 0x00000008 313#define GEM_MAC_RX_CRC_EXP 0x00000010 314#define GEM_MAC_RX_LEN_EXP 0x00000020 315#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 316 317 318/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 319#define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 320#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 321#define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 322#define GEM_MAC_PAUSE_TIME 0xffff0000 323 324/* GEM_MAC_XIF_CONFIG register bits */ 325#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 326#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 327#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 328#define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 329#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 330#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 331#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 332 333/* GEM_MAC_TX_CONFIG register bits */ 334#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 335#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 336#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collitions */ 337#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 338#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 339#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 340#define GEM_MAC_TX_NO_BACKOFF 0x00000040 341#define GEM_MAC_TX_SLOWDOWN 0x00000080 342#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 343#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 344/* Carrier Extension is required for half duplex Gbps operation */ 345 346 347/* GEM_MAC_RX_CONFIG register bits */ 348#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 349#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 350#define GEM_MAC_RX_STRIP_CRC 0x00000004 351#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 352#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 353#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 354#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 355#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 356#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 357/* 358 * Carrier Extension enables reception of packet bursts generated by 359 * senders with carrier extension enabled. 360 */ 361 362 363/* GEM_MAC_CONTROL_CONFIG bits */ 364#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 365#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 366#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 367 368 369/* GEM MIF registers */ 370/* Bit bang registers use low bit only */ 371#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 372#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 373#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 374#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 375#define GEM_MIF_CONFIG 0x6210 376#define GEM_MIF_INTERRUPT_MASK 0x6214 377#define GEM_MIF_BASIC_STATUS 0x6218 378#define GEM_MIF_STATE_MACHINE 0x621c 379 380 381/* GEM_MIF_FRAME bits */ 382#define GEM_MIF_FRAME_DATA 0x0000ffff 383#define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 384#define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 385#define GEM_MIF_FRAME_REG_ADDR 0x007c0000 386#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */ 387#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 388#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 389 390#define GEM_MIF_FRAME_READ 0x60020000 391#define GEM_MIF_FRAME_WRITE 0x50020000 392 393#define GEM_MIF_REG_SHIFT 18 394#define GEM_MIF_PHY_SHIFT 23 395 396 397/* GEM_MIF_CONFIG register bits */ 398#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select */ 399#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 400#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 401#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 402#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 403#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 404#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 405/* MDI0 is onboard tranciever MID1 is external, PHYAD for both is 0 */ 406 407 408/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 409#define GEM_MIF_STATUS 0x0000ffff 410#define GEM_MIF_BASIC 0xffff0000 411/* 412 * The Basic part is the last value read in the POLL field of the config 413 * register. 414 * 415 * The status part indicates the bits that have changed. 416 */ 417 418 419/* The GEM PCS/Serial link register. */ 420#define GEM_MII_CONTROL 0x9000 421#define GEM_MII_STATUS 0x9004 422#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 423#define GEM_MII_ANLPAR 0x900c /* LP ability reg */ 424#define GEM_MII_CONFIG 0x9010 425#define GEM_MII_STATE_MACHINE 0x9014 426#define GEM_MII_INTERRUP_STATUS 0x9018 427#define GEM_MII_DATAPATH_MODE 0x9050 428#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 429#define GEM_MII_OUTPUT_SELECT 0x9058 430#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */ 431 432 433/* GEM_MII_CONTROL bits */ 434/* 435 * DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS. 436 */ 437#define GEM_MII_CONTROL_RESET 0x00008000 438#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 439#define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */ 440#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 441#define GEM_MII_CONTROL_POWERDN 0x00000800 442#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */ 443#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotioation */ 444#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 445#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 446 447 448/* GEM_MII_STATUS reg */ 449#define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 450#define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 451#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ 452#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 453#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ 454#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 455#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 456#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ 457 458 459/* GEM_MII_ANAR and GEM_MII_ANLAR reg bits */ 460#define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ 461#define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ 462 /* Link Partner Capability */ 463#define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */ 464#define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */ 465#define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ 466#define GEM_MII_ANEG_HLF_DUPLX 0x00000040 467#define GEM_MII_ANEG_FUL_DUPLX 0x00000020 468 469 470/* GEM_MII_CONFIG reg */ 471#define GEM_MII_CONFIG_TIMER 0x0000001c /* link monitor timer values */ 472#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 473 474 475/* GEM_MII_DATAPATH_MODE reg */ 476#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ 477#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 478#define GEM_MII_DATAPATH_MII 0x00000004 /* Use MII, not PCS */ 479#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ 480 481 482/* GEM_MII_SLINK_CONTROL reg */ 483#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl */ 484#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 485#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 486#define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ 487#define GEM_MII_SLINK_SELFTEST 0x000001c0 488#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ 489 490 491/* GEM_MII_SLINK_STATUS reg */ 492#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 493#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 494#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 495#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 496 497 498/* Wired GEM PHY addresses */ 499#define GEM_PHYAD_INTERNAL 1 500#define GEM_PHYAD_EXTERNAL 0 501 502/* 503 * GEM descriptor table structures. 504 */ 505struct gem_desc { 506 uint64_t gd_flags; 507 uint64_t gd_addr; 508}; 509 510/* Transmit flags */ 511#define GEM_TD_BUFSIZE 0x0000000000007fffLL 512#define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 513#define GEM_TD_CXSUM_STARTSHFT 15 514#define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 515#define GEM_TD_CXSUM_STUFFSHFT 21 516#define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 517#define GEM_TD_END_OF_PACKET 0x0000000040000000LL 518#define GEM_TD_START_OF_PACKET 0x0000000080000000LL 519#define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 520#define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 521/* 522 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 523 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 524 */ 525 526/* Receive flags */ 527#define GEM_RD_CHECKSUM 0x000000000000ffffLL 528#define GEM_RD_BUFSIZE 0x000000007fff0000LL 529#define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 530#define GEM_RD_HASHVAL 0x0ffff00000000000LL 531#define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 532#define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 533#define GEM_RD_BAD_CRC 0x4000000000000000LL 534 535#define GEM_RD_BUFSHIFT 16 536#define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 537 538/* PCI support */ 539#define PCI_GEM_BASEADDR 0x10 540 541#endif 542