if_fxpvar.h revision 185354
150477Speter/*- 2139749Simp * Copyright (c) 1995, David Greenman 335388Smjacob * All rights reserved. 435388Smjacob * 5154704Smjacob * Redistribution and use in source and binary forms, with or without 635388Smjacob * modification, are permitted provided that the following conditions 752347Smjacob * are met: 835388Smjacob * 1. Redistributions of source code must retain the above copyright 935388Smjacob * notice unmodified, this list of conditions, and the following 1035388Smjacob * disclaimer. 1135388Smjacob * 2. Redistributions in binary form must reproduce the above copyright 1235388Smjacob * notice, this list of conditions and the following disclaimer in the 1335388Smjacob * documentation and/or other materials provided with the distribution. 1466189Smjacob * 1535388Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1635388Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1735388Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1835388Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1935388Smjacob * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2035388Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2135388Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2235388Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2335388Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2435388Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2535388Smjacob * SUCH DAMAGE. 2635388Smjacob * 2735388Smjacob * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 185354 2008-11-27 01:57:23Z yongari $ 2835388Smjacob */ 2935388Smjacob 3035388Smjacob/* 3135388Smjacob * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 3235388Smjacob * Ethernet driver 3344819Smjacob */ 3435388Smjacob 3535388Smjacob/* 3635388Smjacob * Number of transmit control blocks. This determines the number 3735388Smjacob * of transmit buffers that can be chained in the CB list. 3835388Smjacob * This must be a power of two. 3935388Smjacob */ 4042131Smjacob#define FXP_NTXCB 128 4135388Smjacob#define FXP_NTXCB_HIWAT ((FXP_NTXCB * 7) / 10) 42155704Smjacob 43155704Smjacob/* 4453487Smjacob * Maximum size of a DMA segment. 4535388Smjacob */ 4664087Smjacob#define FXP_TSO_SEGSIZE 4096 47155704Smjacob 4839235Sgibbs/* 4935388Smjacob * Size of the TxCB list. 5043420Smjacob */ 5135388Smjacob#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx)) 52155704Smjacob 5335388Smjacob/* 5482689Smjacob * Macro to obtain the DMA address of a virtual address in the 55155704Smjacob * TxCB list based on the base DMA address of the TxCB list. 56155704Smjacob */ 57155704Smjacob#define FXP_TXCB_DMA_ADDR(sc, addr) \ 58155704Smjacob (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \ 59155704Smjacob (uintptr_t)sc->fxp_desc.cbl_list) 60155704Smjacob 61155704Smjacob/* 62155704Smjacob * Number of completed TX commands at which point an interrupt 63155704Smjacob * will be generated to garbage collect the attached buffers. 64155704Smjacob * Must be at least one less than FXP_NTXCB, and should be 65155704Smjacob * enough less so that the transmitter doesn't becomes idle 66155704Smjacob * during the buffer rundown (which would reduce performance). 67155704Smjacob */ 6835388Smjacob#define FXP_CXINT_THRESH 120 6935388Smjacob 7064087Smjacob/* 7164087Smjacob * TxCB list index mask. This is used to do list wrap-around. 7264087Smjacob */ 7382689Smjacob#define FXP_TXCB_MASK (FXP_NTXCB - 1) 7482689Smjacob 7549909Smjacob/* 7661772Smjacob * Number of receive frame area buffers. These are large so chose 7749909Smjacob * wisely. 7882689Smjacob */ 7964087Smjacob#ifdef DEVICE_POLLING 8064087Smjacob#define FXP_NRFABUFS 192 8153487Smjacob#else 8282689Smjacob#define FXP_NRFABUFS 64 8382689Smjacob#endif 8453487Smjacob 8553487Smjacob/* 8653487Smjacob * Maximum number of seconds that the receiver can be idle before we 8753487Smjacob * assume it's dead and attempt to reset it by reprogramming the 8853487Smjacob * multicast filter. This is part of a work-around for a bug in the 8953487Smjacob * NIC. See fxp_stats_update(). 9053487Smjacob */ 9153487Smjacob#define FXP_MAX_RX_IDLE 15 9253487Smjacob 9353487Smjacob/* 9453487Smjacob * Default maximum time, in microseconds, that an interrupt may be delayed 9553487Smjacob * in an attempt to coalesce interrupts. This is only effective if the Intel 9653487Smjacob * microcode is loaded, and may be changed via either loader tunables or 97155704Smjacob * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 98155704Smjacob */ 9953487Smjacob#define TUNABLE_INT_DELAY 1000 10053487Smjacob 10153487Smjacob/* 10253487Smjacob * Default number of packets that will be bundled, before an interrupt is 10353487Smjacob * generated. This is only effective if the Intel microcode is loaded, and 10453487Smjacob * may be changed via either loader tunables or sysctl. This may not be 10564087Smjacob * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 10664087Smjacob * entry in rcvbundl.h. 10753487Smjacob */ 10853487Smjacob#define TUNABLE_BUNDLE_MAX 6 10953487Smjacob 11053487Smjacob#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 11153487Smjacob#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 11253487Smjacob#define FXP_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 11353487Smjacob 11464087Smjacob/* 11564087Smjacob * Structures to handle TX and RX descriptors. 11664087Smjacob */ 11764087Smjacobstruct fxp_rx { 11864087Smjacob struct fxp_rx *rx_next; 11964087Smjacob struct mbuf *rx_mbuf; 12064087Smjacob bus_dmamap_t rx_map; 12164087Smjacob uint32_t rx_addr; 12264087Smjacob}; 12364087Smjacob 12464087Smjacobstruct fxp_tx { 12564087Smjacob struct fxp_tx *tx_next; 12664087Smjacob struct fxp_cb_tx *tx_cb; 12764087Smjacob struct mbuf *tx_mbuf; 12864087Smjacob bus_dmamap_t tx_map; 12964087Smjacob}; 13064087Smjacob 13139235Sgibbsstruct fxp_desc_list { 13264087Smjacob struct fxp_rx rx_list[FXP_NRFABUFS]; 13364087Smjacob struct fxp_tx tx_list[FXP_NTXCB]; 13493706Smjacob struct fxp_tx mcs_tx; 13593706Smjacob struct fxp_rx *rx_head; 13693706Smjacob struct fxp_rx *rx_tail; 13764087Smjacob struct fxp_tx *tx_first; 13864087Smjacob struct fxp_tx *tx_last; 13993706Smjacob struct fxp_rfa *rfa_list; 140155704Smjacob struct fxp_cb_tx *cbl_list; 14139235Sgibbs uint32_t cbl_addr; 14239235Sgibbs bus_dma_tag_t rx_tag; 14365140Smjacob}; 14439235Sgibbs 14552347Smjacob/* 14665140Smjacob * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 14765140Smjacob * for functional grouping. 14853487Smjacob */ 14987635Smjacobstruct fxp_softc { 15087635Smjacob struct ifnet *ifp; /* per-interface network data */ 15187635Smjacob struct resource *fxp_res[2]; /* I/O and IRQ resources */ 15287635Smjacob struct resource_spec *fxp_spec; /* the resource spec we used */ 15353487Smjacob void *ih; /* interrupt handler cookie */ 15435388Smjacob struct mtx sc_mtx; 15546968Smjacob bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */ 15635388Smjacob bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ 15735388Smjacob bus_dmamap_t fxp_smap; /* bus DMA map for stats */ 158155704Smjacob bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ 15952347Smjacob bus_dmamap_t cbl_map; /* DMA map for the TxCB list */ 16052347Smjacob bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */ 16135388Smjacob bus_dmamap_t mcs_map; /* DMA map for the multicast setup */ 16235388Smjacob bus_dmamap_t spare_map; /* spare DMA map */ 16342461Smjacob struct fxp_desc_list fxp_desc; /* descriptors management struct */ 16443420Smjacob int maxtxseg; /* maximum # of TX segments */ 16535388Smjacob int maxsegsize; /* maximum size of a TX segment */ 16645040Smjacob int tx_queued; /* # of active TxCB's */ 16765140Smjacob int need_mcsetup; /* multicast filter needs programming */ 16835388Smjacob struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 16952347Smjacob uint32_t stats_addr; /* DMA address of the stats structure */ 170155704Smjacob int rx_idle_secs; /* # of seconds RX has been idle */ 171155704Smjacob struct callout stat_ch; /* stat callout */ 172155704Smjacob int watchdog_timer; /* seconds until chip reset */ 173155704Smjacob struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 174155704Smjacob uint32_t mcs_addr; /* DMA address of the multicast cmd */ 175155704Smjacob struct ifmedia sc_media; /* media information */ 17635388Smjacob device_t miibus; 177155704Smjacob device_t dev; 17880582Smjacob int tunable_int_delay; /* interrupt delay value for ucode */ 17946968Smjacob int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 18080582Smjacob int tunable_noflow; /* flow control disabled */ 18143420Smjacob int rnr; /* RNR events */ 18243420Smjacob int eeprom_size; /* size of serial EEPROM */ 18380582Smjacob int suspended; /* 0 = normal 1 = suspended or dead */ 18480582Smjacob int cu_resume_bug; 18580582Smjacob int revision; 186155704Smjacob int flags; 187155704Smjacob uint8_t rfa_size; 188155704Smjacob uint32_t tx_cmd; 189155704Smjacob}; 190155704Smjacob 191155704Smjacob#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 19235388Smjacob#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 19346968Smjacob#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 19435388Smjacob#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 19535388Smjacob#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 19635388Smjacob#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 19735388Smjacob#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ 19839235Sgibbs#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 19939235Sgibbs#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 20039235Sgibbs#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ 20139235Sgibbs#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ 20239235Sgibbs#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */ 20339235Sgibbs#define FXP_FLAG_82559_RXCSUM 0x1000 /* 82559 compatible RX checksum */ 20439235Sgibbs#define FXP_FLAG_WOLCAP 0x2000 /* WOL capability */ 20539235Sgibbs#define FXP_FLAG_WOL 0x4000 /* WOL active */ 20665140Smjacob 20765140Smjacob/* Macros to ease CSR access. */ 20865140Smjacob#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) 20943793Smjacob#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) 21039235Sgibbs#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg) 21135388Smjacob#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) 21245040Smjacob#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) 21365140Smjacob#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val) 21465140Smjacob