if_fxpvar.h revision 185354
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 185354 2008-11-27 01:57:23Z yongari $ 28 */ 29 30/* 31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 32 * Ethernet driver 33 */ 34 35/* 36 * Number of transmit control blocks. This determines the number 37 * of transmit buffers that can be chained in the CB list. 38 * This must be a power of two. 39 */ 40#define FXP_NTXCB 128 41#define FXP_NTXCB_HIWAT ((FXP_NTXCB * 7) / 10) 42 43/* 44 * Maximum size of a DMA segment. 45 */ 46#define FXP_TSO_SEGSIZE 4096 47 48/* 49 * Size of the TxCB list. 50 */ 51#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx)) 52 53/* 54 * Macro to obtain the DMA address of a virtual address in the 55 * TxCB list based on the base DMA address of the TxCB list. 56 */ 57#define FXP_TXCB_DMA_ADDR(sc, addr) \ 58 (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \ 59 (uintptr_t)sc->fxp_desc.cbl_list) 60 61/* 62 * Number of completed TX commands at which point an interrupt 63 * will be generated to garbage collect the attached buffers. 64 * Must be at least one less than FXP_NTXCB, and should be 65 * enough less so that the transmitter doesn't becomes idle 66 * during the buffer rundown (which would reduce performance). 67 */ 68#define FXP_CXINT_THRESH 120 69 70/* 71 * TxCB list index mask. This is used to do list wrap-around. 72 */ 73#define FXP_TXCB_MASK (FXP_NTXCB - 1) 74 75/* 76 * Number of receive frame area buffers. These are large so chose 77 * wisely. 78 */ 79#ifdef DEVICE_POLLING 80#define FXP_NRFABUFS 192 81#else 82#define FXP_NRFABUFS 64 83#endif 84 85/* 86 * Maximum number of seconds that the receiver can be idle before we 87 * assume it's dead and attempt to reset it by reprogramming the 88 * multicast filter. This is part of a work-around for a bug in the 89 * NIC. See fxp_stats_update(). 90 */ 91#define FXP_MAX_RX_IDLE 15 92 93/* 94 * Default maximum time, in microseconds, that an interrupt may be delayed 95 * in an attempt to coalesce interrupts. This is only effective if the Intel 96 * microcode is loaded, and may be changed via either loader tunables or 97 * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 98 */ 99#define TUNABLE_INT_DELAY 1000 100 101/* 102 * Default number of packets that will be bundled, before an interrupt is 103 * generated. This is only effective if the Intel microcode is loaded, and 104 * may be changed via either loader tunables or sysctl. This may not be 105 * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 106 * entry in rcvbundl.h. 107 */ 108#define TUNABLE_BUNDLE_MAX 6 109 110#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 111#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 112#define FXP_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 113 114/* 115 * Structures to handle TX and RX descriptors. 116 */ 117struct fxp_rx { 118 struct fxp_rx *rx_next; 119 struct mbuf *rx_mbuf; 120 bus_dmamap_t rx_map; 121 uint32_t rx_addr; 122}; 123 124struct fxp_tx { 125 struct fxp_tx *tx_next; 126 struct fxp_cb_tx *tx_cb; 127 struct mbuf *tx_mbuf; 128 bus_dmamap_t tx_map; 129}; 130 131struct fxp_desc_list { 132 struct fxp_rx rx_list[FXP_NRFABUFS]; 133 struct fxp_tx tx_list[FXP_NTXCB]; 134 struct fxp_tx mcs_tx; 135 struct fxp_rx *rx_head; 136 struct fxp_rx *rx_tail; 137 struct fxp_tx *tx_first; 138 struct fxp_tx *tx_last; 139 struct fxp_rfa *rfa_list; 140 struct fxp_cb_tx *cbl_list; 141 uint32_t cbl_addr; 142 bus_dma_tag_t rx_tag; 143}; 144 145/* 146 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 147 * for functional grouping. 148 */ 149struct fxp_softc { 150 struct ifnet *ifp; /* per-interface network data */ 151 struct resource *fxp_res[2]; /* I/O and IRQ resources */ 152 struct resource_spec *fxp_spec; /* the resource spec we used */ 153 void *ih; /* interrupt handler cookie */ 154 struct mtx sc_mtx; 155 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */ 156 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ 157 bus_dmamap_t fxp_smap; /* bus DMA map for stats */ 158 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ 159 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */ 160 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */ 161 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */ 162 bus_dmamap_t spare_map; /* spare DMA map */ 163 struct fxp_desc_list fxp_desc; /* descriptors management struct */ 164 int maxtxseg; /* maximum # of TX segments */ 165 int maxsegsize; /* maximum size of a TX segment */ 166 int tx_queued; /* # of active TxCB's */ 167 int need_mcsetup; /* multicast filter needs programming */ 168 struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 169 uint32_t stats_addr; /* DMA address of the stats structure */ 170 int rx_idle_secs; /* # of seconds RX has been idle */ 171 struct callout stat_ch; /* stat callout */ 172 int watchdog_timer; /* seconds until chip reset */ 173 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 174 uint32_t mcs_addr; /* DMA address of the multicast cmd */ 175 struct ifmedia sc_media; /* media information */ 176 device_t miibus; 177 device_t dev; 178 int tunable_int_delay; /* interrupt delay value for ucode */ 179 int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 180 int tunable_noflow; /* flow control disabled */ 181 int rnr; /* RNR events */ 182 int eeprom_size; /* size of serial EEPROM */ 183 int suspended; /* 0 = normal 1 = suspended or dead */ 184 int cu_resume_bug; 185 int revision; 186 int flags; 187 uint8_t rfa_size; 188 uint32_t tx_cmd; 189}; 190 191#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 192#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 193#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 194#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 195#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 196#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 197#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ 198#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 199#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 200#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ 201#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ 202#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */ 203#define FXP_FLAG_82559_RXCSUM 0x1000 /* 82559 compatible RX checksum */ 204#define FXP_FLAG_WOLCAP 0x2000 /* WOL capability */ 205#define FXP_FLAG_WOL 0x4000 /* WOL active */ 206 207/* Macros to ease CSR access. */ 208#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) 209#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) 210#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg) 211#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) 212#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) 213#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val) 214