if_fxpvar.h revision 129718
129138Sdg/*
229138Sdg * Copyright (c) 1995, David Greenman
329138Sdg * All rights reserved.
429138Sdg *
529138Sdg * Redistribution and use in source and binary forms, with or without
629138Sdg * modification, are permitted provided that the following conditions
729138Sdg * are met:
829138Sdg * 1. Redistributions of source code must retain the above copyright
929138Sdg *    notice unmodified, this list of conditions, and the following
1029138Sdg *    disclaimer.
1129138Sdg * 2. Redistributions in binary form must reproduce the above copyright
1229138Sdg *    notice, this list of conditions and the following disclaimer in the
1329138Sdg *    documentation and/or other materials provided with the distribution.
1429138Sdg *
1529138Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1629138Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1729138Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1829138Sdg * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1929138Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2029138Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2129138Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2229138Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2329138Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2429138Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2529138Sdg * SUCH DAMAGE.
2629138Sdg *
2750477Speter * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 129718 2004-05-25 14:49:46Z yar $
2829138Sdg */
2929138Sdg
3029138Sdg/*
3129138Sdg * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
3229138Sdg * Ethernet driver
3329138Sdg */
3474178Sjlemon
3538006Sdg/*
3674178Sjlemon * Number of transmit control blocks. This determines the number
3774178Sjlemon * of transmit buffers that can be chained in the CB list.
3874178Sjlemon * This must be a power of two.
3974178Sjlemon */
4074178Sjlemon#define FXP_NTXCB       128
4174178Sjlemon
4274178Sjlemon/*
43112982Smux * Size of the TxCB list.
44112982Smux */
45112982Smux#define FXP_TXCB_SZ	(FXP_NTXCB * sizeof(struct fxp_cb_tx))
46112982Smux
47112982Smux/*
48112982Smux * Macro to obtain the DMA address of a virtual address in the
49112982Smux * TxCB list based on the base DMA address of the TxCB list.
50112982Smux */
51112982Smux#define FXP_TXCB_DMA_ADDR(sc, addr)					\
52112982Smux	(sc->fxp_desc.cbl_addr + (uintptr_t)addr -			\
53112982Smux	(uintptr_t)sc->fxp_desc.cbl_list)
54112982Smux
55112982Smux/*
5674178Sjlemon * Number of completed TX commands at which point an interrupt
5774178Sjlemon * will be generated to garbage collect the attached buffers.
5874178Sjlemon * Must be at least one less than FXP_NTXCB, and should be
5974178Sjlemon * enough less so that the transmitter doesn't becomes idle
6074178Sjlemon * during the buffer rundown (which would reduce performance).
6174178Sjlemon */
6274178Sjlemon#define FXP_CXINT_THRESH 120
6374178Sjlemon
6474178Sjlemon/*
6574178Sjlemon * TxCB list index mask. This is used to do list wrap-around.
6674178Sjlemon */
6774178Sjlemon#define FXP_TXCB_MASK   (FXP_NTXCB - 1)
6874178Sjlemon
6974178Sjlemon/*
7074178Sjlemon * Number of receive frame area buffers. These are large so chose
7174178Sjlemon * wisely.
7274178Sjlemon */
7387902Sluigi#ifdef DEVICE_POLLING
7487902Sluigi#define FXP_NRFABUFS	192
7587902Sluigi#else
7674178Sjlemon#define FXP_NRFABUFS    64
7787902Sluigi#endif
7874178Sjlemon
7974178Sjlemon/*
8074178Sjlemon * Maximum number of seconds that the receiver can be idle before we
8174178Sjlemon * assume it's dead and attempt to reset it by reprogramming the
8274178Sjlemon * multicast filter. This is part of a work-around for a bug in the
8374178Sjlemon * NIC. See fxp_stats_update().
8474178Sjlemon */
8574178Sjlemon#define FXP_MAX_RX_IDLE 15
8674178Sjlemon
8785461Sjlemon/*
8885461Sjlemon * Default maximum time, in microseconds, that an interrupt may be delayed
8985461Sjlemon * in an attempt to coalesce interrupts.  This is only effective if the Intel
9085461Sjlemon * microcode is loaded, and may be changed via either loader tunables or
9185461Sjlemon * sysctl.  See also the CPUSAVER_DWORD entry in rcvbundl.h.
9285461Sjlemon */
9385461Sjlemon#define TUNABLE_INT_DELAY 1000
9485461Sjlemon
9585461Sjlemon/*
9685461Sjlemon * Default number of packets that will be bundled, before an interrupt is
9785461Sjlemon * generated.  This is only effective if the Intel microcode is loaded, and
9885461Sjlemon * may be changed via either loader tunables or sysctl.  This may not be
9985461Sjlemon * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD
10085461Sjlemon * entry in rcvbundl.h.
10185461Sjlemon */
10285461Sjlemon#define TUNABLE_BUNDLE_MAX 6
10385461Sjlemon
10474178Sjlemon#if __FreeBSD_version < 500000
10574178Sjlemon#define	FXP_LOCK(_sc)
10674178Sjlemon#define	FXP_UNLOCK(_sc)
107114006Snjl#define	INTR_MPSAFE		0
108114006Snjl#define mtx_owned(a)		0
109114006Snjl#define mtx_assert(a, b)
11093818Sjhb#define mtx_init(a, b, c, d)
11174178Sjlemon#define mtx_destroy(a)
11274178Sjlemonstruct mtx { int dummy; };
11374178Sjlemon#else
11474178Sjlemon#define	FXP_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
11574178Sjlemon#define	FXP_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
11674178Sjlemon#endif
11774178Sjlemon
118112982Smux/*
119112982Smux * Structures to handle TX and RX descriptors.
120112982Smux */
121112982Smuxstruct fxp_rx {
122112982Smux	struct fxp_rx *rx_next;
123112982Smux	struct mbuf *rx_mbuf;
124112982Smux	bus_dmamap_t rx_map;
125112982Smux	u_int32_t rx_addr;
126112982Smux};
12774178Sjlemon
128112982Smuxstruct fxp_tx {
129112982Smux	struct fxp_tx *tx_next;
130112982Smux	struct fxp_cb_tx *tx_cb;
131112982Smux	struct mbuf *tx_mbuf;
132112982Smux	bus_dmamap_t tx_map;
133112982Smux};
134112982Smux
135112982Smuxstruct fxp_desc_list {
136112982Smux	struct fxp_rx rx_list[FXP_NRFABUFS];
137112982Smux	struct fxp_tx tx_list[FXP_NTXCB];
138112982Smux	struct fxp_tx mcs_tx;
139112982Smux	struct fxp_rx *rx_head;
140112982Smux	struct fxp_rx *rx_tail;
141112982Smux	struct fxp_tx *tx_first;
142112982Smux	struct fxp_tx *tx_last;
143112982Smux	struct fxp_rfa *rfa_list;
144112982Smux	struct fxp_cb_tx *cbl_list;
145112982Smux	u_int32_t cbl_addr;
146112982Smux	bus_dma_tag_t rx_tag;
147112982Smux};
148112982Smux
14974178Sjlemon/*
15038006Sdg * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
15138006Sdg *	 for functional grouping.
15238006Sdg */
15329138Sdgstruct fxp_softc {
15429138Sdg	struct arpcom arpcom;		/* per-interface network data */
15545720Speter	struct resource *mem;		/* resource descriptor for registers */
15671485Smjacob	int rtp;			/* register resource type */
15771485Smjacob	int rgd;			/* register descriptor in use */
15845720Speter	struct resource *irq;		/* resource descriptor for interrupt */
15945720Speter	void *ih;			/* interrupt handler cookie */
16065983Scp	struct mtx sc_mtx;
16151821Sgallatin	bus_space_tag_t sc_st;		/* bus space tag */
16251821Sgallatin	bus_space_handle_t sc_sh;	/* bus space handle */
163112982Smux	bus_dma_tag_t fxp_mtag;		/* bus DMA tag for mbufs */
164112982Smux	bus_dma_tag_t fxp_stag;		/* bus DMA tag for stats */
165112982Smux	bus_dmamap_t fxp_smap;		/* bus DMA map for stats */
166112982Smux	bus_dma_tag_t cbl_tag;		/* DMA tag for the TxCB list */
167112982Smux	bus_dmamap_t cbl_map;		/* DMA map for the TxCB list */
168112982Smux	bus_dma_tag_t mcs_tag;		/* DMA tag for the multicast setup */
169112982Smux	bus_dmamap_t mcs_map;		/* DMA map for the multicast setup */
170112982Smux	bus_dmamap_t spare_map;		/* spare DMA map */
171112982Smux	struct fxp_desc_list fxp_desc;	/* descriptors management struct */
17231447Sdg	int tx_queued;			/* # of active TxCB's */
17331447Sdg	int need_mcsetup;		/* multicast filter needs programming */
17429138Sdg	struct fxp_stats *fxp_stats;	/* Pointer to interface stats */
175112982Smux	u_int32_t stats_addr;		/* DMA address of the stats structure */
17631447Sdg	int rx_idle_secs;		/* # of seconds RX has been idle */
177119786Ssam	struct callout stat_ch;		/* stat callout */
17831447Sdg	struct fxp_cb_mcs *mcsp;	/* Pointer to mcast setup descriptor */
179112982Smux	u_int32_t mcs_addr;		/* DMA address of the multicast cmd */
18038006Sdg	struct ifmedia sc_media;	/* media information */
18174178Sjlemon	device_t miibus;
18274178Sjlemon	device_t dev;
18385461Sjlemon	struct sysctl_ctx_list sysctl_ctx;
18485461Sjlemon	struct sysctl_oid *sysctl_tree;
18585461Sjlemon	int tunable_int_delay;		/* interrupt delay value for ucode */
18685461Sjlemon	int tunable_bundle_max;		/* max # frames per interrupt (ucode) */
18758715Sdg	int eeprom_size;		/* size of serial EEPROM */
188114269Simp	int suspended;			/* 0 = normal  1 = suspended or dead */
18976777Sjlemon	int cu_resume_bug;
19085461Sjlemon	int revision;
19174178Sjlemon	int flags;
19266007Sdg	u_int32_t saved_maps[5];	/* pci data */
19366007Sdg	u_int32_t saved_biosaddr;
19466007Sdg	u_int8_t saved_intline;
19566007Sdg	u_int8_t saved_cachelnsz;
19666007Sdg	u_int8_t saved_lattimer;
197111578Swpaul	u_int8_t rfa_size;
198111578Swpaul        u_int32_t tx_cmd;
19929138Sdg};
20029138Sdg
20174178Sjlemon#define FXP_FLAG_MWI_ENABLE	0x0001	/* MWI enable */
20274178Sjlemon#define FXP_FLAG_READ_ALIGN	0x0002	/* align read access with cacheline */
20374178Sjlemon#define FXP_FLAG_WRITE_ALIGN	0x0004	/* end write on cacheline */
20474178Sjlemon#define FXP_FLAG_EXT_TXCB	0x0008	/* enable use of extended TXCB */
20574178Sjlemon#define FXP_FLAG_SERIAL_MEDIA	0x0010	/* 10Mbps serial interface */
20674178Sjlemon#define FXP_FLAG_LONG_PKT_EN	0x0020	/* enable long packet reception */
20774178Sjlemon#define FXP_FLAG_ALL_MCAST	0x0040	/* accept all multicast frames */
20876777Sjlemon#define FXP_FLAG_CU_RESUME_BUG	0x0080	/* requires workaround for CU_RESUME */
20985461Sjlemon#define FXP_FLAG_UCODE		0x0100	/* ucode is loaded */
210106554Siedowse#define FXP_FLAG_DEFERRED_RNR	0x0200	/* DEVICE_POLLING deferred RNR */
211111578Swpaul#define FXP_FLAG_EXT_RFA	0x0400	/* extended RFDs for csum offload */
212129718Syar#define FXP_FLAG_SAVE_BAD	0x0800	/* save bad pkts: bad size, CRC, etc */
21374178Sjlemon
21429138Sdg/* Macros to ease CSR access. */
21529138Sdg#define	CSR_READ_1(sc, reg)						\
21629138Sdg	bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
21729138Sdg#define	CSR_READ_2(sc, reg)						\
21829138Sdg	bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
21929138Sdg#define	CSR_READ_4(sc, reg)						\
22029138Sdg	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
22129138Sdg#define	CSR_WRITE_1(sc, reg, val)					\
22229138Sdg	bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
22329138Sdg#define	CSR_WRITE_2(sc, reg, val)					\
22429138Sdg	bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
22529138Sdg#define	CSR_WRITE_4(sc, reg, val)					\
22629138Sdg	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
22729138Sdg
22829138Sdg#define	sc_if			arpcom.ac_if
229