if_fxpvar.h revision 129718
11573Srgrimes/* 21573Srgrimes * Copyright (c) 1995, David Greenman 31573Srgrimes * All rights reserved. 41573Srgrimes * 51573Srgrimes * Redistribution and use in source and binary forms, with or without 61573Srgrimes * modification, are permitted provided that the following conditions 71573Srgrimes * are met: 81573Srgrimes * 1. Redistributions of source code must retain the above copyright 91573Srgrimes * notice unmodified, this list of conditions, and the following 101573Srgrimes * disclaimer. 111573Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121573Srgrimes * notice, this list of conditions and the following disclaimer in the 131573Srgrimes * documentation and/or other materials provided with the distribution. 141573Srgrimes * 151573Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16148834Sstefanf * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 171573Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 181573Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 191573Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 201573Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 211573Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 221573Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 231573Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 241573Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 251573Srgrimes * SUCH DAMAGE. 261573Srgrimes * 271573Srgrimes * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 129718 2004-05-25 14:49:46Z yar $ 281573Srgrimes */ 291573Srgrimes 301573Srgrimes/* 311573Srgrimes * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 321573Srgrimes * Ethernet driver 33148834Sstefanf */ 3484260Sobrien 351573Srgrimes/* 361573Srgrimes * Number of transmit control blocks. This determines the number 371573Srgrimes * of transmit buffers that can be chained in the CB list. 381573Srgrimes * This must be a power of two. 391573Srgrimes */ 401573Srgrimes#define FXP_NTXCB 128 4184260Sobrien 421573Srgrimes/* 431573Srgrimes * Size of the TxCB list. 441573Srgrimes */ 4584260Sobrien#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx)) 4684260Sobrien 4784260Sobrien/* 481573Srgrimes * Macro to obtain the DMA address of a virtual address in the 491573Srgrimes * TxCB list based on the base DMA address of the TxCB list. 501573Srgrimes */ 511573Srgrimes#define FXP_TXCB_DMA_ADDR(sc, addr) \ 5284260Sobrien (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \ 531573Srgrimes (uintptr_t)sc->fxp_desc.cbl_list) 54148834Sstefanf 55148834Sstefanf/* 56148834Sstefanf * Number of completed TX commands at which point an interrupt 57148834Sstefanf * will be generated to garbage collect the attached buffers. 581573Srgrimes * Must be at least one less than FXP_NTXCB, and should be 591573Srgrimes * enough less so that the transmitter doesn't becomes idle 601573Srgrimes * during the buffer rundown (which would reduce performance). 611573Srgrimes */ 621573Srgrimes#define FXP_CXINT_THRESH 120 631573Srgrimes 6484260Sobrien/* 6584260Sobrien * TxCB list index mask. This is used to do list wrap-around. 661573Srgrimes */ 671573Srgrimes#define FXP_TXCB_MASK (FXP_NTXCB - 1) 681573Srgrimes 6984260Sobrien/* 7084260Sobrien * Number of receive frame area buffers. These are large so chose 7184260Sobrien * wisely. 72148834Sstefanf */ 731573Srgrimes#ifdef DEVICE_POLLING 741573Srgrimes#define FXP_NRFABUFS 192 751573Srgrimes#else 761573Srgrimes#define FXP_NRFABUFS 64 771573Srgrimes#endif 781573Srgrimes 7984260Sobrien/* 8084260Sobrien * Maximum number of seconds that the receiver can be idle before we 8184260Sobrien * assume it's dead and attempt to reset it by reprogramming the 8284260Sobrien * multicast filter. This is part of a work-around for a bug in the 8384260Sobrien * NIC. See fxp_stats_update(). 84148834Sstefanf */ 85148834Sstefanf#define FXP_MAX_RX_IDLE 15 861573Srgrimes 871573Srgrimes/* 881573Srgrimes * Default maximum time, in microseconds, that an interrupt may be delayed 891573Srgrimes * in an attempt to coalesce interrupts. This is only effective if the Intel 901573Srgrimes * microcode is loaded, and may be changed via either loader tunables or 91148834Sstefanf * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 9284260Sobrien */ 9384260Sobrien#define TUNABLE_INT_DELAY 1000 9484260Sobrien 951573Srgrimes/* 961573Srgrimes * Default number of packets that will be bundled, before an interrupt is 971573Srgrimes * generated. This is only effective if the Intel microcode is loaded, and 981573Srgrimes * may be changed via either loader tunables or sysctl. This may not be 991573Srgrimes * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 1001573Srgrimes * entry in rcvbundl.h. 1011573Srgrimes */ 1021573Srgrimes#define TUNABLE_BUNDLE_MAX 6 1031573Srgrimes 1041573Srgrimes#if __FreeBSD_version < 500000 1051573Srgrimes#define FXP_LOCK(_sc) 1061573Srgrimes#define FXP_UNLOCK(_sc) 1071573Srgrimes#define INTR_MPSAFE 0 1081573Srgrimes#define mtx_owned(a) 0 109148834Sstefanf#define mtx_assert(a, b) 1101573Srgrimes#define mtx_init(a, b, c, d) 1111573Srgrimes#define mtx_destroy(a) 11284260Sobrienstruct mtx { int dummy; }; 11384260Sobrien#else 11484260Sobrien#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 11584260Sobrien#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 11684260Sobrien#endif 11784260Sobrien 11884260Sobrien/* 11984260Sobrien * Structures to handle TX and RX descriptors. 120148834Sstefanf */ 12184260Sobrienstruct fxp_rx { 12284260Sobrien struct fxp_rx *rx_next; 12384260Sobrien struct mbuf *rx_mbuf; 12484260Sobrien bus_dmamap_t rx_map; 12584260Sobrien u_int32_t rx_addr; 12684260Sobrien}; 12784260Sobrien 12884260Sobrienstruct fxp_tx { 12984260Sobrien struct fxp_tx *tx_next; 13084260Sobrien struct fxp_cb_tx *tx_cb; 13184260Sobrien struct mbuf *tx_mbuf; 13284260Sobrien bus_dmamap_t tx_map; 13384260Sobrien}; 134148834Sstefanf 1351573Srgrimesstruct fxp_desc_list { 1361573Srgrimes struct fxp_rx rx_list[FXP_NRFABUFS]; 137148834Sstefanf struct fxp_tx tx_list[FXP_NTXCB]; 13884260Sobrien struct fxp_tx mcs_tx; 13984260Sobrien struct fxp_rx *rx_head; 140148834Sstefanf struct fxp_rx *rx_tail; 141148834Sstefanf struct fxp_tx *tx_first; 142148834Sstefanf struct fxp_tx *tx_last; 143148834Sstefanf struct fxp_rfa *rfa_list; 144148834Sstefanf struct fxp_cb_tx *cbl_list; 145148834Sstefanf u_int32_t cbl_addr; 14684260Sobrien bus_dma_tag_t rx_tag; 14784260Sobrien}; 14884260Sobrien 1491573Srgrimes/* 150 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 151 * for functional grouping. 152 */ 153struct fxp_softc { 154 struct arpcom arpcom; /* per-interface network data */ 155 struct resource *mem; /* resource descriptor for registers */ 156 int rtp; /* register resource type */ 157 int rgd; /* register descriptor in use */ 158 struct resource *irq; /* resource descriptor for interrupt */ 159 void *ih; /* interrupt handler cookie */ 160 struct mtx sc_mtx; 161 bus_space_tag_t sc_st; /* bus space tag */ 162 bus_space_handle_t sc_sh; /* bus space handle */ 163 bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */ 164 bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ 165 bus_dmamap_t fxp_smap; /* bus DMA map for stats */ 166 bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ 167 bus_dmamap_t cbl_map; /* DMA map for the TxCB list */ 168 bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */ 169 bus_dmamap_t mcs_map; /* DMA map for the multicast setup */ 170 bus_dmamap_t spare_map; /* spare DMA map */ 171 struct fxp_desc_list fxp_desc; /* descriptors management struct */ 172 int tx_queued; /* # of active TxCB's */ 173 int need_mcsetup; /* multicast filter needs programming */ 174 struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 175 u_int32_t stats_addr; /* DMA address of the stats structure */ 176 int rx_idle_secs; /* # of seconds RX has been idle */ 177 struct callout stat_ch; /* stat callout */ 178 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 179 u_int32_t mcs_addr; /* DMA address of the multicast cmd */ 180 struct ifmedia sc_media; /* media information */ 181 device_t miibus; 182 device_t dev; 183 struct sysctl_ctx_list sysctl_ctx; 184 struct sysctl_oid *sysctl_tree; 185 int tunable_int_delay; /* interrupt delay value for ucode */ 186 int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 187 int eeprom_size; /* size of serial EEPROM */ 188 int suspended; /* 0 = normal 1 = suspended or dead */ 189 int cu_resume_bug; 190 int revision; 191 int flags; 192 u_int32_t saved_maps[5]; /* pci data */ 193 u_int32_t saved_biosaddr; 194 u_int8_t saved_intline; 195 u_int8_t saved_cachelnsz; 196 u_int8_t saved_lattimer; 197 u_int8_t rfa_size; 198 u_int32_t tx_cmd; 199}; 200 201#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 202#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 203#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 204#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 205#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 206#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 207#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ 208#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 209#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 210#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ 211#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ 212#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */ 213 214/* Macros to ease CSR access. */ 215#define CSR_READ_1(sc, reg) \ 216 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 217#define CSR_READ_2(sc, reg) \ 218 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 219#define CSR_READ_4(sc, reg) \ 220 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 221#define CSR_WRITE_1(sc, reg, val) \ 222 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 223#define CSR_WRITE_2(sc, reg, val) \ 224 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 225#define CSR_WRITE_4(sc, reg, val) \ 226 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 227 228#define sc_if arpcom.ac_if 229