if_fxpreg.h revision 51821
112510Sdg/* 212510Sdg * Copyright (c) 1995, David Greenman 312510Sdg * All rights reserved. 412510Sdg * 512510Sdg * Redistribution and use in source and binary forms, with or without 612510Sdg * modification, are permitted provided that the following conditions 712510Sdg * are met: 812510Sdg * 1. Redistributions of source code must retain the above copyright 912510Sdg * notice unmodified, this list of conditions, and the following 1012510Sdg * disclaimer. 1112510Sdg * 2. Redistributions in binary form must reproduce the above copyright 1212510Sdg * notice, this list of conditions and the following disclaimer in the 1312510Sdg * documentation and/or other materials provided with the distribution. 1412510Sdg * 1512510Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1612510Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1712510Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1812510Sdg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1912510Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2012510Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2112510Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2212510Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2312510Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2412510Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2512510Sdg * SUCH DAMAGE. 2612510Sdg * 2750477Speter * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 51821 1999-09-30 19:03:12Z gallatin $ 2812510Sdg */ 2912510Sdg 3012510Sdg#define FXP_VENDORID_INTEL 0x8086 3150987Speter#define FXP_DEVICEID_i82557 0x1229 /* 82557 - 82559 "classic" */ 3250987Speter#define FXP_DEVICEID_i82559 0x1030 /* New 82559 device id.. */ 3312510Sdg 3412510Sdg#define FXP_PCI_MMBA 0x10 3512510Sdg#define FXP_PCI_IOBA 0x14 3612510Sdg 3729138Sdg/* 3829138Sdg * Control/status registers. 3929138Sdg */ 4029138Sdg#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 4129138Sdg#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 4229138Sdg#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 4329138Sdg#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 4429138Sdg#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 4529138Sdg#define FXP_CSR_PORT 8 /* port (4 bytes) */ 4629138Sdg#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 4729138Sdg#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 4829138Sdg#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 4912510Sdg 5029138Sdg/* 5129138Sdg * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 5229138Sdg * 5329138Sdg * volatile u_int8_t :2, 5429138Sdg * scb_rus:4, 5529138Sdg * scb_cus:2; 5629138Sdg */ 5729138Sdg 5822255Sdg#define FXP_PORT_SOFTWARE_RESET 0 5922255Sdg#define FXP_PORT_SELFTEST 1 6022255Sdg#define FXP_PORT_SELECTIVE_RESET 2 6122255Sdg#define FXP_PORT_DUMP 3 6222255Sdg 6312510Sdg#define FXP_SCB_RUS_IDLE 0 6412510Sdg#define FXP_SCB_RUS_SUSPENDED 1 6512510Sdg#define FXP_SCB_RUS_NORESOURCES 2 6612510Sdg#define FXP_SCB_RUS_READY 4 6712510Sdg#define FXP_SCB_RUS_SUSP_NORBDS 9 6812510Sdg#define FXP_SCB_RUS_NORES_NORBDS 10 6912510Sdg#define FXP_SCB_RUS_READY_NORBDS 12 7012510Sdg 7112510Sdg#define FXP_SCB_CUS_IDLE 0 7212510Sdg#define FXP_SCB_CUS_SUSPENDED 1 7312510Sdg#define FXP_SCB_CUS_ACTIVE 2 7412510Sdg 7512510Sdg#define FXP_SCB_STATACK_SWI 0x04 7612510Sdg#define FXP_SCB_STATACK_MDI 0x08 7712510Sdg#define FXP_SCB_STATACK_RNR 0x10 7812510Sdg#define FXP_SCB_STATACK_CNA 0x20 7912510Sdg#define FXP_SCB_STATACK_FR 0x40 8012510Sdg#define FXP_SCB_STATACK_CXTNO 0x80 8112510Sdg 8212510Sdg#define FXP_SCB_COMMAND_CU_NOP 0x00 8312510Sdg#define FXP_SCB_COMMAND_CU_START 0x10 8412510Sdg#define FXP_SCB_COMMAND_CU_RESUME 0x20 8512510Sdg#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 8612510Sdg#define FXP_SCB_COMMAND_CU_DUMP 0x50 8712510Sdg#define FXP_SCB_COMMAND_CU_BASE 0x60 8812510Sdg#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 8912510Sdg 9012510Sdg#define FXP_SCB_COMMAND_RU_NOP 0 9112510Sdg#define FXP_SCB_COMMAND_RU_START 1 9212510Sdg#define FXP_SCB_COMMAND_RU_RESUME 2 9312510Sdg#define FXP_SCB_COMMAND_RU_ABORT 4 9412510Sdg#define FXP_SCB_COMMAND_RU_LOADHDS 5 9512510Sdg#define FXP_SCB_COMMAND_RU_BASE 6 9612510Sdg#define FXP_SCB_COMMAND_RU_RBDRESUME 7 9712510Sdg 9812510Sdg/* 9912510Sdg * Command block definitions 10012510Sdg */ 10112510Sdgstruct fxp_cb_nop { 10229974Sdg void *fill[2]; 10312510Sdg volatile u_int16_t cb_status; 10412510Sdg volatile u_int16_t cb_command; 10512510Sdg volatile u_int32_t link_addr; 10612510Sdg}; 10712510Sdgstruct fxp_cb_ias { 10829974Sdg void *fill[2]; 10912510Sdg volatile u_int16_t cb_status; 11012510Sdg volatile u_int16_t cb_command; 11112510Sdg volatile u_int32_t link_addr; 11212510Sdg volatile u_int8_t macaddr[6]; 11312510Sdg}; 11412510Sdg/* I hate bit-fields :-( */ 11512510Sdgstruct fxp_cb_config { 11629974Sdg void *fill[2]; 11712510Sdg volatile u_int16_t cb_status; 11812510Sdg volatile u_int16_t cb_command; 11912510Sdg volatile u_int32_t link_addr; 12036767Sbde volatile u_int byte_count:6, 12112510Sdg :2; 12236767Sbde volatile u_int rx_fifo_limit:4, 12312510Sdg tx_fifo_limit:3, 12412510Sdg :1; 12512510Sdg volatile u_int8_t adaptive_ifs; 12636767Sbde volatile u_int :8; 12736767Sbde volatile u_int rx_dma_bytecount:7, 12812510Sdg :1; 12936767Sbde volatile u_int tx_dma_bytecount:7, 13012510Sdg dma_bce:1; 13136767Sbde volatile u_int late_scb:1, 13212510Sdg :1, 13312510Sdg tno_int:1, 13412510Sdg ci_int:1, 13512510Sdg :3, 13612510Sdg save_bf:1; 13736767Sbde volatile u_int disc_short_rx:1, 13812510Sdg underrun_retry:2, 13912510Sdg :5; 14036767Sbde volatile u_int mediatype:1, 14112510Sdg :7; 14236767Sbde volatile u_int :8; 14336767Sbde volatile u_int :3, 14412510Sdg nsai:1, 14512510Sdg preamble_length:2, 14612510Sdg loopback:2; 14736767Sbde volatile u_int linear_priority:3, 14812510Sdg :5; 14936767Sbde volatile u_int linear_pri_mode:1, 15012510Sdg :3, 15112510Sdg interfrm_spacing:4; 15236767Sbde volatile u_int :8; 15336767Sbde volatile u_int :8; 15436767Sbde volatile u_int promiscuous:1, 15512510Sdg bcast_disable:1, 15612510Sdg :5, 15712510Sdg crscdt:1; 15836767Sbde volatile u_int :8; 15936767Sbde volatile u_int :8; 16036767Sbde volatile u_int stripping:1, 16112510Sdg padding:1, 16212510Sdg rcv_crc_xfer:1, 16312510Sdg :5; 16436767Sbde volatile u_int :6, 16512510Sdg force_fdx:1, 16612510Sdg fdx_pin_en:1; 16736767Sbde volatile u_int :6, 16812510Sdg multi_ia:1, 16912510Sdg :1; 17036767Sbde volatile u_int :3, 17112510Sdg mc_all:1, 17212510Sdg :4; 17312510Sdg}; 17429974Sdg 17529974Sdg#define MAXMCADDR 80 17629974Sdgstruct fxp_cb_mcs { 17729974Sdg struct fxp_cb_tx *next; 17829974Sdg struct mbuf *mb_head; 17929974Sdg volatile u_int16_t cb_status; 18029974Sdg volatile u_int16_t cb_command; 18129974Sdg volatile u_int32_t link_addr; 18229974Sdg volatile u_int16_t mc_cnt; 18329974Sdg volatile u_int8_t mc_addr[MAXMCADDR][6]; 18429974Sdg}; 18529974Sdg 18629974Sdg/* 18729974Sdg * Number of DMA segments in a TxCB. Note that this is carefully 18829974Sdg * chosen to make the total struct size an even power of two. It's 18929974Sdg * critical that no TxCB be split across a page boundry since 19029974Sdg * no attempt is made to allocate physically contiguous memory. 19129974Sdg * 19229974Sdg */ 19329974Sdg#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 19429974Sdg#define FXP_NTXSEG 28 19529974Sdg#else 19629974Sdg#define FXP_NTXSEG 29 19729974Sdg#endif 19829974Sdg 19912510Sdgstruct fxp_tbd { 20012510Sdg volatile u_int32_t tb_addr; 20112510Sdg volatile u_int32_t tb_size; 20212510Sdg}; 20312510Sdgstruct fxp_cb_tx { 20429974Sdg struct fxp_cb_tx *next; 20529974Sdg struct mbuf *mb_head; 20612510Sdg volatile u_int16_t cb_status; 20712510Sdg volatile u_int16_t cb_command; 20812510Sdg volatile u_int32_t link_addr; 20912510Sdg volatile u_int32_t tbd_array_addr; 21012510Sdg volatile u_int16_t byte_count; 21112510Sdg volatile u_int8_t tx_threshold; 21212510Sdg volatile u_int8_t tbd_number; 21312510Sdg /* 21412510Sdg * The following isn't actually part of the TxCB. 21512510Sdg */ 21629974Sdg volatile struct fxp_tbd tbd[FXP_NTXSEG]; 21712510Sdg}; 21812510Sdg 21912510Sdg/* 22012510Sdg * Control Block (CB) definitions 22112510Sdg */ 22212510Sdg 22312510Sdg/* status */ 22412510Sdg#define FXP_CB_STATUS_OK 0x2000 22512510Sdg#define FXP_CB_STATUS_C 0x8000 22612510Sdg/* commands */ 22712510Sdg#define FXP_CB_COMMAND_NOP 0x0 22812510Sdg#define FXP_CB_COMMAND_IAS 0x1 22912510Sdg#define FXP_CB_COMMAND_CONFIG 0x2 23029974Sdg#define FXP_CB_COMMAND_MCAS 0x3 23112510Sdg#define FXP_CB_COMMAND_XMIT 0x4 23212510Sdg#define FXP_CB_COMMAND_RESRV 0x5 23312510Sdg#define FXP_CB_COMMAND_DUMP 0x6 23412510Sdg#define FXP_CB_COMMAND_DIAG 0x7 23512510Sdg/* command flags */ 23612510Sdg#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 23712510Sdg#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 23812510Sdg#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 23912510Sdg#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 24012510Sdg 24112510Sdg/* 24212510Sdg * RFA definitions 24312510Sdg */ 24412510Sdg 24512510Sdgstruct fxp_rfa { 24612510Sdg volatile u_int16_t rfa_status; 24712510Sdg volatile u_int16_t rfa_control; 24851821Sgallatin volatile u_int8_t link_addr[4]; 24951821Sgallatin volatile u_int8_t rbd_addr[4]; 25012510Sdg volatile u_int16_t actual_size; 25112510Sdg volatile u_int16_t size; 25212510Sdg}; 25312510Sdg#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 25412510Sdg#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 25512510Sdg#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 25612510Sdg#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 25712510Sdg#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 25812510Sdg#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 25912510Sdg#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 26012510Sdg#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 26112510Sdg#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 26212510Sdg#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 26312510Sdg#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 26412510Sdg#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 26512510Sdg#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 26612510Sdg#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 26712510Sdg#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 26812510Sdg 26912510Sdg/* 27012510Sdg * Statistics dump area definitions 27112510Sdg */ 27212510Sdgstruct fxp_stats { 27312510Sdg volatile u_int32_t tx_good; 27412510Sdg volatile u_int32_t tx_maxcols; 27512510Sdg volatile u_int32_t tx_latecols; 27612510Sdg volatile u_int32_t tx_underruns; 27712510Sdg volatile u_int32_t tx_lostcrs; 27812510Sdg volatile u_int32_t tx_deffered; 27912510Sdg volatile u_int32_t tx_single_collisions; 28012510Sdg volatile u_int32_t tx_multiple_collisions; 28112510Sdg volatile u_int32_t tx_total_collisions; 28212510Sdg volatile u_int32_t rx_good; 28312510Sdg volatile u_int32_t rx_crc_errors; 28412510Sdg volatile u_int32_t rx_alignment_errors; 28512510Sdg volatile u_int32_t rx_rnr_errors; 28612510Sdg volatile u_int32_t rx_overrun_errors; 28712510Sdg volatile u_int32_t rx_cdt_errors; 28812510Sdg volatile u_int32_t rx_shortframes; 28912510Sdg volatile u_int32_t completion_status; 29012510Sdg}; 29112510Sdg#define FXP_STATS_DUMP_COMPLETE 0xa005 29212510Sdg#define FXP_STATS_DR_COMPLETE 0xa007 29312510Sdg 29412510Sdg/* 29512510Sdg * Serial EEPROM control register bits 29612510Sdg */ 29712510Sdg/* shift clock */ 29812510Sdg#define FXP_EEPROM_EESK 0x01 29912510Sdg/* chip select */ 30012510Sdg#define FXP_EEPROM_EECS 0x02 30112510Sdg/* data in */ 30212510Sdg#define FXP_EEPROM_EEDI 0x04 30312510Sdg/* data out */ 30412510Sdg#define FXP_EEPROM_EEDO 0x08 30512510Sdg 30612510Sdg/* 30712510Sdg * Serial EEPROM opcodes, including start bit 30812510Sdg */ 30912510Sdg#define FXP_EEPROM_OPC_ERASE 0x4 31012510Sdg#define FXP_EEPROM_OPC_WRITE 0x5 31112510Sdg#define FXP_EEPROM_OPC_READ 0x6 31223964Sdg 31323964Sdg/* 31423964Sdg * Management Data Interface opcodes 31523964Sdg */ 31623964Sdg#define FXP_MDI_WRITE 0x1 31723964Sdg#define FXP_MDI_READ 0x2 31823964Sdg 31923964Sdg/* 32023964Sdg * PHY device types 32123964Sdg */ 32223964Sdg#define FXP_PHY_NONE 0 32323964Sdg#define FXP_PHY_82553A 1 32423964Sdg#define FXP_PHY_82553C 2 32523964Sdg#define FXP_PHY_82503 3 32623964Sdg#define FXP_PHY_DP83840 4 32723964Sdg#define FXP_PHY_80C240 5 32823964Sdg#define FXP_PHY_80C24 6 32926623Sdg#define FXP_PHY_82555 7 33024079Sdg#define FXP_PHY_DP83840A 10 33134014Sdg#define FXP_PHY_82555B 11 33223964Sdg 33323964Sdg/* 33426623Sdg * PHY BMCR Basic Mode Control Register 33543915Sjulian * Should probably be in i82555.h or dp83840.h (Intel/National names). 33643912Sjulian * (Called "Management Data Interface Control Reg" in some Intel data books). 33743912Sjulian * (*) indicates bit ignored in auto negotiation mode. 33824079Sdg */ 33943912Sjulian#define FXP_PHY_BMCR 0x0 34043915Sjulian#define FXP_PHY_BMCR_COLTEST 0x0080 /* not on Intel parts */ 34143912Sjulian#define FXP_PHY_BMCR_FULLDUPLEX 0x0100 /* 1 = Fullduplex (*) */ 34243912Sjulian#define FXP_PHY_BMCR_RESTART_NEG 0x0200 /* ==> 1 to restart autoneg */ 34343915Sjulian#define FXP_PHY_BMCR_ISOLATE 0x0400 /* not on Intel parts */ 34443912Sjulian#define FXP_PHY_BMCR_POWERDOWN 0x0800 /* 1 = low power mode */ 34543912Sjulian#define FXP_PHY_BMCR_AUTOEN 0x1000 /* 1 = for auto mode */ 34643912Sjulian#define FXP_PHY_BMCR_SPEED_100M 0x2000 /* 1 = for 100Mb/sec (*) */ 34743912Sjulian#define FXP_PHY_BMCR_LOOPBACK 0x4000 /* 1 = loopback at the PHY */ 34843912Sjulian#define FXP_PHY_BMCR_RESET 0x8000 /* ==> 1 sets to defaults */ 34924079Sdg 35024079Sdg/* 35143915Sjulian * Basic Mode Status Register (National name) 35243915Sjulian * Management Data Interface Status reg. (Intel name) 35343915Sjulian * in both Intel and National parts. 35443912Sjulian */ 35543912Sjulian#define FXP_PHY_STS 0x1 35643912Sjulian#define FXP_PHY_STS_EXND 0x0001 /* Extended regs enabled */ 35743912Sjulian#define FXP_PHY_STS_JABR 0x0002 /* Jabber detected */ 35843912Sjulian#define FXP_PHY_STS_LINK_STS 0x0004 /* Link valid */ 35943912Sjulian#define FXP_PHY_STS_CAN_AUTO 0x0008 /* Auto detection available */ 36043912Sjulian#define FXP_PHY_STS_REMT_FAULT 0x0010 /* remote fault detected */ 36143912Sjulian#define FXP_PHY_STS_AUTO_DONE 0x0020 /* auto negotiation completed */ 36243912Sjulian#define FXP_PHY_STS_MGMT_PREAMBLE 0x0040 /* real complicated */ 36343915Sjulian#define FXP_PHY_STS_10HDX_OK 0x0800 /* can do 10Mb HDX */ 36443915Sjulian#define FXP_PHY_STS_10FDX_OK 0x1000 /* can do 10Mb FDX */ 36543915Sjulian#define FXP_PHY_STS_100HDX_OK 0x2000 /* can do 100Mb HDX */ 36643915Sjulian#define FXP_PHY_STS_100FDX_OK 0x4000 /* can do 100Mb FDX */ 36743915Sjulian#define FXP_PHY_STS_100T4_OK 0x8000 /* can do 100bT4 -not Intel */ 36843912Sjulian 36943912Sjulian/* 37043912Sjulian * More Phy regs 37143912Sjulian */ 37243912Sjulian#define FXP_PHY_ID1 0x2 37343912Sjulian#define FXP_PHY_ID2 0x3 37443912Sjulian 37543912Sjulian/* 37643912Sjulian * MDI Auto negotiation advertisement register. 37743912Sjulian * What we advertise we can do.. 37843912Sjulian * The same bits are used to indicate the response too. 37943912Sjulian */ 38043912Sjulian#define FXP_PHY_ADVRT 0x4 38143912Sjulian#define FXP_PHY_RMT_ADVRT 0x5 /* what the other end said */ 38243912Sjulian#define FXP_PHY_ADVRT_SELECT 0x001F /* real complicated */ 38343912Sjulian#define FXP_PHY_ADVRT_TECH_AVAIL 0x1FE0 /* can do 10Mb HDX */ 38443912Sjulian#define FXP_PHY_ADVRT_RMT_FAULT 0x2000 /* can do 10Mb FDX */ 38543912Sjulian#define FXP_PHY_ADVRT_ACK 0x4000 /* Acked */ 38643912Sjulian#define FXP_PHY_ADVRT_NXT_PAGE 0x8000 /* can do 100Mb FDX */ 38743912Sjulian 38843912Sjulian/* 38943912Sjulian * Phy Unit Status and Control Register (another one) 39043915Sjulian * This is not in the National part! 39143912Sjulian */ 39243912Sjulian#define FXP_PHY_USC 0x10 39343912Sjulian#define FXP_PHY_USC_DUPLEX 0x0001 /* in FDX mode */ 39443912Sjulian#define FXP_PHY_USC_SPEED 0x0002 /* 1 = in 100Mb mode */ 39543912Sjulian#define FXP_PHY_USC_POLARITY 0x0100 /* 1 = reverse polarity */ 39643912Sjulian#define FXP_PHY_USC_10_PWRDOWN 0x0200 /* 10Mb PHY powered down */ 39743912Sjulian#define FXP_PHY_USC_100_PWRDOWN 0x0400 /* 100Mb PHY powered down */ 39843912Sjulian#define FXP_PHY_USC_INSYNC 0x0800 /* 100Mb PHY is in sync */ 39943912Sjulian#define FXP_PHY_USC_TX_FLOWCNTRL 0x1000 /* TX FC mode in use */ 40043912Sjulian#define FXP_PHY_USC_PHY_FLOWCNTRL 0x8000 /* PHY FC mode in use */ 40143912Sjulian 40243912Sjulian 40343912Sjulian/* 40443915Sjulian * DP83830 PHY, PCS Configuration Register 40543915Sjulian * NOT compatible with Intel parts, 40643915Sjulian * (where it is the 100BTX premature eof counter). 40723964Sdg */ 40823964Sdg#define FXP_DP83840_PCR 0x17 40943915Sjulian#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always = FDX */ 41043915Sjulian#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = link disconnect bypass */ 41123964Sdg#define FXP_DP83840_PCR_BIT8 0x0100 41223964Sdg#define FXP_DP83840_PCR_BIT10 0x0400 41343915Sjulian 41443915Sjulian/* 41543915Sjulian * DP83830 PHY, Address/status Register 41643915Sjulian * NOT compatible with Intel parts, 41743915Sjulian * (where it is the 10BT jabber detect counter). 41843915Sjulian */ 41943915Sjulian#define FXP_DP83840_PAR 0x19 42043915Sjulian#define FXP_DP83840_PAR_PHYADDR 0x1F 42143915Sjulian#define FXP_DP83840_PAR_CON_STATUS 0x20 42243915Sjulian#define FXP_DP83840_PAR_SPEED_10 0x40 /* 1 == running at 10 Mb/Sec */ 42343915Sjulian 424