if_fxpreg.h revision 51821
1219820Sjeff/* 2219820Sjeff * Copyright (c) 1995, David Greenman 3219820Sjeff * All rights reserved. 4219820Sjeff * 5272027Shselasky * Redistribution and use in source and binary forms, with or without 6219820Sjeff * modification, are permitted provided that the following conditions 7219820Sjeff * are met: 8219820Sjeff * 1. Redistributions of source code must retain the above copyright 9219820Sjeff * notice unmodified, this list of conditions, and the following 10219820Sjeff * disclaimer. 11219820Sjeff * 2. Redistributions in binary form must reproduce the above copyright 12219820Sjeff * notice, this list of conditions and the following disclaimer in the 13219820Sjeff * documentation and/or other materials provided with the distribution. 14219820Sjeff * 15219820Sjeff * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16219820Sjeff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17219820Sjeff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18219820Sjeff * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19219820Sjeff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20219820Sjeff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21219820Sjeff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22219820Sjeff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23219820Sjeff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24219820Sjeff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25219820Sjeff * SUCH DAMAGE. 26219820Sjeff * 27219820Sjeff * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 51821 1999-09-30 19:03:12Z gallatin $ 28219820Sjeff */ 29219820Sjeff 30219820Sjeff#define FXP_VENDORID_INTEL 0x8086 31219820Sjeff#define FXP_DEVICEID_i82557 0x1229 /* 82557 - 82559 "classic" */ 32219820Sjeff#define FXP_DEVICEID_i82559 0x1030 /* New 82559 device id.. */ 33219820Sjeff 34219820Sjeff#define FXP_PCI_MMBA 0x10 35219820Sjeff#define FXP_PCI_IOBA 0x14 36219820Sjeff 37219820Sjeff/* 38219820Sjeff * Control/status registers. 39219820Sjeff */ 40219820Sjeff#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 41219820Sjeff#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 42255932Salfred#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 43219820Sjeff#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 44255932Salfred#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 45219820Sjeff#define FXP_CSR_PORT 8 /* port (4 bytes) */ 46272027Shselasky#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 47329159Shselasky#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 48306486Shselasky#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 49306486Shselasky 50306486Shselasky/* 51306486Shselasky * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 52329159Shselasky * 53219820Sjeff * volatile u_int8_t :2, 54219820Sjeff * scb_rus:4, 55219820Sjeff * scb_cus:2; 56369102Shselasky */ 57369102Shselasky 58369102Shselasky#define FXP_PORT_SOFTWARE_RESET 0 59369102Shselasky#define FXP_PORT_SELFTEST 1 60219820Sjeff#define FXP_PORT_SELECTIVE_RESET 2 61255932Salfred#define FXP_PORT_DUMP 3 62255932Salfred 63255932Salfred#define FXP_SCB_RUS_IDLE 0 64255932Salfred#define FXP_SCB_RUS_SUSPENDED 1 65255932Salfred#define FXP_SCB_RUS_NORESOURCES 2 66255932Salfred#define FXP_SCB_RUS_READY 4 67329159Shselasky#define FXP_SCB_RUS_SUSP_NORBDS 9 68255932Salfred#define FXP_SCB_RUS_NORES_NORBDS 10 69329159Shselasky#define FXP_SCB_RUS_READY_NORBDS 12 70255932Salfred 71219820Sjeff#define FXP_SCB_CUS_IDLE 0 72219820Sjeff#define FXP_SCB_CUS_SUSPENDED 1 73219820Sjeff#define FXP_SCB_CUS_ACTIVE 2 74255932Salfred 75255932Salfred#define FXP_SCB_STATACK_SWI 0x04 76255932Salfred#define FXP_SCB_STATACK_MDI 0x08 77329159Shselasky#define FXP_SCB_STATACK_RNR 0x10 78329159Shselasky#define FXP_SCB_STATACK_CNA 0x20 79329159Shselasky#define FXP_SCB_STATACK_FR 0x40 80219820Sjeff#define FXP_SCB_STATACK_CXTNO 0x80 81219820Sjeff 82219820Sjeff#define FXP_SCB_COMMAND_CU_NOP 0x00 83255932Salfred#define FXP_SCB_COMMAND_CU_START 0x10 84255932Salfred#define FXP_SCB_COMMAND_CU_RESUME 0x20 85255932Salfred#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 86329159Shselasky#define FXP_SCB_COMMAND_CU_DUMP 0x50 87329159Shselasky#define FXP_SCB_COMMAND_CU_BASE 0x60 88219820Sjeff#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 89219820Sjeff 90219820Sjeff#define FXP_SCB_COMMAND_RU_NOP 0 91219820Sjeff#define FXP_SCB_COMMAND_RU_START 1 92219820Sjeff#define FXP_SCB_COMMAND_RU_RESUME 2 93219820Sjeff#define FXP_SCB_COMMAND_RU_ABORT 4 94219820Sjeff#define FXP_SCB_COMMAND_RU_LOADHDS 5 95219820Sjeff#define FXP_SCB_COMMAND_RU_BASE 6 96219820Sjeff#define FXP_SCB_COMMAND_RU_RBDRESUME 7 97219820Sjeff 98219820Sjeff/* 99219820Sjeff * Command block definitions 100219820Sjeff */ 101219820Sjeffstruct fxp_cb_nop { 102219820Sjeff void *fill[2]; 103219820Sjeff volatile u_int16_t cb_status; 104219820Sjeff volatile u_int16_t cb_command; 105219820Sjeff volatile u_int32_t link_addr; 106219820Sjeff}; 107272027Shselaskystruct fxp_cb_ias { 108272027Shselasky void *fill[2]; 109272027Shselasky volatile u_int16_t cb_status; 110272027Shselasky volatile u_int16_t cb_command; 111255932Salfred volatile u_int32_t link_addr; 112255932Salfred volatile u_int8_t macaddr[6]; 113255932Salfred}; 114329159Shselasky/* I hate bit-fields :-( */ 115329159Shselaskystruct fxp_cb_config { 116329159Shselasky void *fill[2]; 117329159Shselasky volatile u_int16_t cb_status; 118255932Salfred volatile u_int16_t cb_command; 119255932Salfred volatile u_int32_t link_addr; 120255932Salfred volatile u_int byte_count:6, 121255932Salfred :2; 122255932Salfred volatile u_int rx_fifo_limit:4, 123255932Salfred tx_fifo_limit:3, 124255932Salfred :1; 125255932Salfred volatile u_int8_t adaptive_ifs; 126255932Salfred volatile u_int :8; 127255932Salfred volatile u_int rx_dma_bytecount:7, 128329159Shselasky :1; 129329159Shselasky volatile u_int tx_dma_bytecount:7, 130329159Shselasky dma_bce:1; 131329159Shselasky volatile u_int late_scb:1, 132329159Shselasky :1, 133255932Salfred tno_int:1, 134255932Salfred ci_int:1, 135255932Salfred :3, 136255932Salfred save_bf:1; 137255932Salfred volatile u_int disc_short_rx:1, 138255932Salfred underrun_retry:2, 139255932Salfred :5; 140255932Salfred volatile u_int mediatype:1, 141255932Salfred :7; 142255932Salfred volatile u_int :8; 143255932Salfred volatile u_int :3, 144255932Salfred nsai:1, 145255932Salfred preamble_length:2, 146255932Salfred loopback:2; 147272027Shselasky volatile u_int linear_priority:3, 148255932Salfred :5; 149255932Salfred volatile u_int linear_pri_mode:1, 150272027Shselasky :3, 151255932Salfred interfrm_spacing:4; 152255932Salfred volatile u_int :8; 153255932Salfred volatile u_int :8; 154255932Salfred volatile u_int promiscuous:1, 155255932Salfred bcast_disable:1, 156255932Salfred :5, 157255932Salfred crscdt:1; 158255932Salfred volatile u_int :8; 159255932Salfred volatile u_int :8; 160255932Salfred volatile u_int stripping:1, 161255932Salfred padding:1, 162255932Salfred rcv_crc_xfer:1, 163255932Salfred :5; 164255932Salfred volatile u_int :6, 165255932Salfred force_fdx:1, 166255932Salfred fdx_pin_en:1; 167255932Salfred volatile u_int :6, 168299179Spfg multi_ia:1, 169255932Salfred :1; 170255932Salfred volatile u_int :3, 171255932Salfred mc_all:1, 172255932Salfred :4; 173255932Salfred}; 174255932Salfred 175255932Salfred#define MAXMCADDR 80 176255932Salfredstruct fxp_cb_mcs { 177255932Salfred struct fxp_cb_tx *next; 178255932Salfred struct mbuf *mb_head; 179255932Salfred volatile u_int16_t cb_status; 180255932Salfred volatile u_int16_t cb_command; 181255932Salfred volatile u_int32_t link_addr; 182255932Salfred volatile u_int16_t mc_cnt; 183255932Salfred volatile u_int8_t mc_addr[MAXMCADDR][6]; 184255932Salfred}; 185255932Salfred 186255932Salfred/* 187255932Salfred * Number of DMA segments in a TxCB. Note that this is carefully 188255932Salfred * chosen to make the total struct size an even power of two. It's 189272027Shselasky * critical that no TxCB be split across a page boundry since 190255932Salfred * no attempt is made to allocate physically contiguous memory. 191255932Salfred * 192255932Salfred */ 193255932Salfred#ifdef __alpha__ /* XXX - should be conditional on pointer size */ 194255932Salfred#define FXP_NTXSEG 28 195255932Salfred#else 196329159Shselasky#define FXP_NTXSEG 29 197255932Salfred#endif 198255932Salfred 199255932Salfredstruct fxp_tbd { 200255932Salfred volatile u_int32_t tb_addr; 201255932Salfred volatile u_int32_t tb_size; 202255932Salfred}; 203255932Salfredstruct fxp_cb_tx { 204255932Salfred struct fxp_cb_tx *next; 205255932Salfred struct mbuf *mb_head; 206255932Salfred volatile u_int16_t cb_status; 207255932Salfred volatile u_int16_t cb_command; 208255932Salfred volatile u_int32_t link_addr; 209255932Salfred volatile u_int32_t tbd_array_addr; 210255932Salfred volatile u_int16_t byte_count; 211255932Salfred volatile u_int8_t tx_threshold; 212219820Sjeff volatile u_int8_t tbd_number; 213219820Sjeff /* 214219820Sjeff * The following isn't actually part of the TxCB. 215219820Sjeff */ 216219820Sjeff volatile struct fxp_tbd tbd[FXP_NTXSEG]; 217219820Sjeff}; 218329159Shselasky 219255932Salfred/* 220255932Salfred * Control Block (CB) definitions 221329159Shselasky */ 222329159Shselasky 223329159Shselasky/* status */ 224255932Salfred#define FXP_CB_STATUS_OK 0x2000 225219820Sjeff#define FXP_CB_STATUS_C 0x8000 226329159Shselasky/* commands */ 227329159Shselasky#define FXP_CB_COMMAND_NOP 0x0 228329159Shselasky#define FXP_CB_COMMAND_IAS 0x1 229329159Shselasky#define FXP_CB_COMMAND_CONFIG 0x2 230329159Shselasky#define FXP_CB_COMMAND_MCAS 0x3 231329159Shselasky#define FXP_CB_COMMAND_XMIT 0x4 232219820Sjeff#define FXP_CB_COMMAND_RESRV 0x5 233255932Salfred#define FXP_CB_COMMAND_DUMP 0x6 234255932Salfred#define FXP_CB_COMMAND_DIAG 0x7 235329159Shselasky/* command flags */ 236219820Sjeff#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 237329159Shselasky#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 238329159Shselasky#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 239255932Salfred#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 240255932Salfred 241219820Sjeff/* 242219820Sjeff * RFA definitions 243219820Sjeff */ 244219820Sjeff 245219820Sjeffstruct fxp_rfa { 246219820Sjeff volatile u_int16_t rfa_status; 247219820Sjeff volatile u_int16_t rfa_control; 248329159Shselasky volatile u_int8_t link_addr[4]; 249219820Sjeff volatile u_int8_t rbd_addr[4]; 250219820Sjeff volatile u_int16_t actual_size; 251219820Sjeff volatile u_int16_t size; 252219820Sjeff}; 253219820Sjeff#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 254219820Sjeff#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 255219820Sjeff#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 256255932Salfred#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 257219820Sjeff#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 258219820Sjeff#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 259219820Sjeff#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 260219820Sjeff#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 261219820Sjeff#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 262219820Sjeff#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 263219820Sjeff#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 264219820Sjeff#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 265255932Salfred#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 266219820Sjeff#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 267219820Sjeff#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 268219820Sjeff 269219820Sjeff/* 270219820Sjeff * Statistics dump area definitions 271219820Sjeff */ 272219820Sjeffstruct fxp_stats { 273272027Shselasky volatile u_int32_t tx_good; 274272027Shselasky volatile u_int32_t tx_maxcols; 275272027Shselasky volatile u_int32_t tx_latecols; 276272027Shselasky volatile u_int32_t tx_underruns; 277272027Shselasky volatile u_int32_t tx_lostcrs; 278272027Shselasky volatile u_int32_t tx_deffered; 279272027Shselasky volatile u_int32_t tx_single_collisions; 280329159Shselasky volatile u_int32_t tx_multiple_collisions; 281329159Shselasky volatile u_int32_t tx_total_collisions; 282272027Shselasky volatile u_int32_t rx_good; 283272027Shselasky volatile u_int32_t rx_crc_errors; 284272027Shselasky volatile u_int32_t rx_alignment_errors; 285272027Shselasky volatile u_int32_t rx_rnr_errors; 286272027Shselasky volatile u_int32_t rx_overrun_errors; 287272027Shselasky volatile u_int32_t rx_cdt_errors; 288272027Shselasky volatile u_int32_t rx_shortframes; 289272027Shselasky volatile u_int32_t completion_status; 290272027Shselasky}; 291329159Shselasky#define FXP_STATS_DUMP_COMPLETE 0xa005 292329159Shselasky#define FXP_STATS_DR_COMPLETE 0xa007 293329159Shselasky 294329159Shselasky/* 295329159Shselasky * Serial EEPROM control register bits 296329159Shselasky */ 297329159Shselasky/* shift clock */ 298329159Shselasky#define FXP_EEPROM_EESK 0x01 299329159Shselasky/* chip select */ 300255932Salfred#define FXP_EEPROM_EECS 0x02 301255932Salfred/* data in */ 302255932Salfred#define FXP_EEPROM_EEDI 0x04 303255932Salfred/* data out */ 304255932Salfred#define FXP_EEPROM_EEDO 0x08 305255932Salfred 306255932Salfred/* 307255932Salfred * Serial EEPROM opcodes, including start bit 308255932Salfred */ 309255932Salfred#define FXP_EEPROM_OPC_ERASE 0x4 310255932Salfred#define FXP_EEPROM_OPC_WRITE 0x5 311255932Salfred#define FXP_EEPROM_OPC_READ 0x6 312255932Salfred 313255932Salfred/* 314255932Salfred * Management Data Interface opcodes 315255932Salfred */ 316255932Salfred#define FXP_MDI_WRITE 0x1 317255932Salfred#define FXP_MDI_READ 0x2 318255932Salfred 319255932Salfred/* 320255932Salfred * PHY device types 321255932Salfred */ 322255932Salfred#define FXP_PHY_NONE 0 323255932Salfred#define FXP_PHY_82553A 1 324255932Salfred#define FXP_PHY_82553C 2 325255932Salfred#define FXP_PHY_82503 3 326255932Salfred#define FXP_PHY_DP83840 4 327255932Salfred#define FXP_PHY_80C240 5 328255932Salfred#define FXP_PHY_80C24 6 329255932Salfred#define FXP_PHY_82555 7 330255932Salfred#define FXP_PHY_DP83840A 10 331255932Salfred#define FXP_PHY_82555B 11 332255932Salfred 333255932Salfred/* 334255932Salfred * PHY BMCR Basic Mode Control Register 335255932Salfred * Should probably be in i82555.h or dp83840.h (Intel/National names). 336255932Salfred * (Called "Management Data Interface Control Reg" in some Intel data books). 337255932Salfred * (*) indicates bit ignored in auto negotiation mode. 338255932Salfred */ 339255932Salfred#define FXP_PHY_BMCR 0x0 340255932Salfred#define FXP_PHY_BMCR_COLTEST 0x0080 /* not on Intel parts */ 341255932Salfred#define FXP_PHY_BMCR_FULLDUPLEX 0x0100 /* 1 = Fullduplex (*) */ 342255932Salfred#define FXP_PHY_BMCR_RESTART_NEG 0x0200 /* ==> 1 to restart autoneg */ 343255932Salfred#define FXP_PHY_BMCR_ISOLATE 0x0400 /* not on Intel parts */ 344255932Salfred#define FXP_PHY_BMCR_POWERDOWN 0x0800 /* 1 = low power mode */ 345255932Salfred#define FXP_PHY_BMCR_AUTOEN 0x1000 /* 1 = for auto mode */ 346255932Salfred#define FXP_PHY_BMCR_SPEED_100M 0x2000 /* 1 = for 100Mb/sec (*) */ 347255932Salfred#define FXP_PHY_BMCR_LOOPBACK 0x4000 /* 1 = loopback at the PHY */ 348255932Salfred#define FXP_PHY_BMCR_RESET 0x8000 /* ==> 1 sets to defaults */ 349255932Salfred 350255932Salfred/* 351255932Salfred * Basic Mode Status Register (National name) 352255932Salfred * Management Data Interface Status reg. (Intel name) 353255932Salfred * in both Intel and National parts. 354255932Salfred */ 355255932Salfred#define FXP_PHY_STS 0x1 356255932Salfred#define FXP_PHY_STS_EXND 0x0001 /* Extended regs enabled */ 357255932Salfred#define FXP_PHY_STS_JABR 0x0002 /* Jabber detected */ 358255932Salfred#define FXP_PHY_STS_LINK_STS 0x0004 /* Link valid */ 359255932Salfred#define FXP_PHY_STS_CAN_AUTO 0x0008 /* Auto detection available */ 360255932Salfred#define FXP_PHY_STS_REMT_FAULT 0x0010 /* remote fault detected */ 361255932Salfred#define FXP_PHY_STS_AUTO_DONE 0x0020 /* auto negotiation completed */ 362255932Salfred#define FXP_PHY_STS_MGMT_PREAMBLE 0x0040 /* real complicated */ 363255932Salfred#define FXP_PHY_STS_10HDX_OK 0x0800 /* can do 10Mb HDX */ 364255932Salfred#define FXP_PHY_STS_10FDX_OK 0x1000 /* can do 10Mb FDX */ 365255932Salfred#define FXP_PHY_STS_100HDX_OK 0x2000 /* can do 100Mb HDX */ 366255932Salfred#define FXP_PHY_STS_100FDX_OK 0x4000 /* can do 100Mb FDX */ 367255932Salfred#define FXP_PHY_STS_100T4_OK 0x8000 /* can do 100bT4 -not Intel */ 368255932Salfred 369255932Salfred/* 370255932Salfred * More Phy regs 371255932Salfred */ 372255932Salfred#define FXP_PHY_ID1 0x2 373255932Salfred#define FXP_PHY_ID2 0x3 374255932Salfred 375255932Salfred/* 376255932Salfred * MDI Auto negotiation advertisement register. 377255932Salfred * What we advertise we can do.. 378255932Salfred * The same bits are used to indicate the response too. 379255932Salfred */ 380255932Salfred#define FXP_PHY_ADVRT 0x4 381255932Salfred#define FXP_PHY_RMT_ADVRT 0x5 /* what the other end said */ 382255932Salfred#define FXP_PHY_ADVRT_SELECT 0x001F /* real complicated */ 383255932Salfred#define FXP_PHY_ADVRT_TECH_AVAIL 0x1FE0 /* can do 10Mb HDX */ 384255932Salfred#define FXP_PHY_ADVRT_RMT_FAULT 0x2000 /* can do 10Mb FDX */ 385219820Sjeff#define FXP_PHY_ADVRT_ACK 0x4000 /* Acked */ 386219820Sjeff#define FXP_PHY_ADVRT_NXT_PAGE 0x8000 /* can do 100Mb FDX */ 387219820Sjeff 388219820Sjeff/* 389219820Sjeff * Phy Unit Status and Control Register (another one) 390219820Sjeff * This is not in the National part! 391219820Sjeff */ 392219820Sjeff#define FXP_PHY_USC 0x10 393219820Sjeff#define FXP_PHY_USC_DUPLEX 0x0001 /* in FDX mode */ 394219820Sjeff#define FXP_PHY_USC_SPEED 0x0002 /* 1 = in 100Mb mode */ 395329159Shselasky#define FXP_PHY_USC_POLARITY 0x0100 /* 1 = reverse polarity */ 396329159Shselasky#define FXP_PHY_USC_10_PWRDOWN 0x0200 /* 10Mb PHY powered down */ 397329159Shselasky#define FXP_PHY_USC_100_PWRDOWN 0x0400 /* 100Mb PHY powered down */ 398329159Shselasky#define FXP_PHY_USC_INSYNC 0x0800 /* 100Mb PHY is in sync */ 399219820Sjeff#define FXP_PHY_USC_TX_FLOWCNTRL 0x1000 /* TX FC mode in use */ 400219820Sjeff#define FXP_PHY_USC_PHY_FLOWCNTRL 0x8000 /* PHY FC mode in use */ 401255932Salfred 402255932Salfred 403255932Salfred/* 404255932Salfred * DP83830 PHY, PCS Configuration Register 405255932Salfred * NOT compatible with Intel parts, 406255932Salfred * (where it is the 100BTX premature eof counter). 407255932Salfred */ 408255932Salfred#define FXP_DP83840_PCR 0x17 409255932Salfred#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always = FDX */ 410255932Salfred#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = link disconnect bypass */ 411255932Salfred#define FXP_DP83840_PCR_BIT8 0x0100 412219820Sjeff#define FXP_DP83840_PCR_BIT10 0x0400 413219820Sjeff 414219820Sjeff/* 415219820Sjeff * DP83830 PHY, Address/status Register 416219820Sjeff * NOT compatible with Intel parts, 417219820Sjeff * (where it is the 10BT jabber detect counter). 418219820Sjeff */ 419329159Shselasky#define FXP_DP83840_PAR 0x19 420219820Sjeff#define FXP_DP83840_PAR_PHYADDR 0x1F 421219820Sjeff#define FXP_DP83840_PAR_CON_STATUS 0x20 422219820Sjeff#define FXP_DP83840_PAR_SPEED_10 0x40 /* 1 == running at 10 Mb/Sec */ 423219820Sjeff 424219820Sjeff