1/*-
2 * Copyright (c) 2015 Semihalf
3 * Copyright (c) 2015 Stormshield
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: releng/11.0/sys/dev/etherswitch/e6000sw/e6000swreg.h 289947 2015-10-25 22:14:04Z zbb $
28 *
29 */
30
31#ifndef _E6000SWREG_H_
32#define _E6000SWREG_H_
33
34struct atu_opt {
35	uint16_t mac_01;
36	uint16_t mac_23;
37	uint16_t mac_45;
38	uint16_t fid;
39};
40
41/*
42 * Definitions for the Marvell 88E6000 series Ethernet Switch.
43 */
44
45#define CPU_PORT			0x5
46
47/*
48 * Switch Registers
49 */
50#define REG_GLOBAL			0x1b
51#define REG_GLOBAL2			0x1c
52#define REG_PORT(p)			(0x10 + (p))
53
54#define REG_NUM_MAX			31
55
56/*
57 * Per-Port Switch Registers
58 */
59#define PORT_STATUS			0x0
60#define PSC_CONTROL			0x1
61#define SWITCH_ID			0x3
62#define PORT_CONTROL			0x4
63#define PORT_CONTROL_1			0x5
64#define PORT_VLAN_MAP			0x6
65#define PORT_VID			0x7
66#define PORT_ASSOCIATION_VECTOR		0xb
67#define PORT_ATU_CTRL			0xc
68#define RX_COUNTER			0x12
69#define TX_COUNTER			0x13
70
71#define PORT_VID_DEF_VID		0
72#define PORT_VID_DEF_VID_MASK		0xfff
73#define PORT_VID_PRIORITY_MASK		0xc00
74
75#define PORT_CONTROL_ENABLE		0x3
76
77/* PORT_VLAN fields */
78#define PORT_VLAN_MAP_TABLE_MASK	0x7f
79#define PORT_VLAN_MAP_FID		12
80#define PORT_VLAN_MAP_FID_MASK		0xf000
81/*
82 * Switch Global Register 1 accessed via REG_GLOBAL_ADDR
83 */
84#define SWITCH_GLOBAL_STATUS		0
85#define SWITCH_GLOBAL_CONTROL		4
86#define SWITCH_GLOBAL_CONTROL2		28
87
88#define MONITOR_CONTROL			26
89
90/* ATU operation */
91#define ATU_FID				1
92#define ATU_CONTROL			10
93#define ATU_OPERATION			11
94#define ATU_DATA			12
95#define ATU_MAC_ADDR01			13
96#define ATU_MAC_ADDR23			14
97#define ATU_MAC_ADDR45			15
98
99#define ATU_UNIT_BUSY			(1 << 15)
100#define ENTRY_STATE			0xf
101
102/* ATU_CONTROL fields */
103#define ATU_CONTROL_AGETIME		4
104#define ATU_CONTROL_AGETIME_MASK	0xff0
105#define ATU_CONTROL_LEARN2ALL		3
106
107/* ATU opcode */
108#define NO_OPERATION			(0 << 0)
109#define FLUSH_ALL			(1 << 0)
110#define FLUSH_NON_STATIC		(1 << 1)
111#define LOAD_FROM_FIB			(3 << 0)
112#define PURGE_FROM_FIB			(3 << 0)
113#define GET_NEXT_IN_FIB			(1 << 2)
114#define FLUSH_ALL_IN_FIB		(5 << 0)
115#define FLUSH_NON_STATIC_IN_FIB		(3 << 1)
116#define GET_VIOLATION_DATA		(7 << 0)
117#define CLEAR_VIOLATION_DATA		(7 << 0)
118
119/* ATU Stats */
120#define COUNT_ALL			(0 << 0)
121
122/*
123 * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR
124 */
125#define MGMT_EN_2x			2
126#define MGMT_EN_0x			3
127#define SWITCH_MGMT			5
128#define ATU_STATS			14
129
130#define MGMT_EN_ALL			0xffff
131
132/* SWITCH_MGMT fields */
133
134#define SWITCH_MGMT_PRI			0
135#define SWITCH_MGMT_PRI_MASK		7
136#define	SWITCH_MGMT_RSVD2CPU		3
137#define SWITCH_MGMT_FC_PRI		4
138#define SWITCH_MGMT_FC_PRI_MASK		(7 << 4)
139#define SWITCH_MGMT_FORCEFLOW		7
140
141/* ATU_STATS fields */
142
143#define ATU_STATS_BIN			14
144#define ATU_STATS_FLAG			12
145
146/*
147 * PHY registers accessed via 'Switch Global Registers' (REG_GLOBAL2).
148 */
149#define SMI_PHY_CMD_REG			0x18
150#define SMI_PHY_DATA_REG		0x19
151
152#define PHY_CMD				0x18
153#define PHY_DATA			0x19
154#define PHY_DATA_MASK			0xffff
155
156#define PHY_CMD_SMI_BUSY		15
157#define PHY_CMD_MODE			12
158#define PHY_CMD_MODE_MDIO		1
159#define PHY_CMD_MODE_XMDIO		0
160#define PHY_CMD_OPCODE			10
161#define PHY_CMD_OPCODE_WRITE		1
162#define PHY_CMD_OPCODE_READ		2
163#define PHY_CMD_DEV_ADDR		5
164#define PHY_CMD_DEV_ADDR_MASK		0x3e0
165#define PHY_CMD_REG_ADDR		0
166#define PHY_CMD_REG_ADDR_MASK		0x1f
167
168#define PHY_PAGE_REG			22
169
170#define E6000SW_NUM_PHYS		5
171#define E6000SW_NUM_PHY_REGS		29
172#define E6000SW_CPUPORTS_MASK		((1 << 5) | (1 << 6))
173#define E6000SW_NUM_VGROUPS		8
174#define E6000SW_NUM_PORTS		7
175#define E6000SW_PORT_NO_VGROUP		-1
176#define E6000SW_DEFAULT_AGETIME		20
177#define E6000SW_RETRIES			100
178
179
180/* Default vlangroups */
181#define E6000SW_DEF_VLANGROUP0		(1 | (1 << 1) | (1 << 2) | (1 << 3) | \
182    (1 << 6))
183#define E6000SW_DEF_VLANGROUP1		((1 << 4) | (1 << 5))
184
185#endif /* _E6000SWREG_H_ */
186