1/*- 2 * Copyright (c) 2011-2012 Stefan Bethke. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/11.0/sys/dev/etherswitch/arswitch/arswitch_reg.c 292738 2015-12-26 02:31:39Z adrian $ 27 */ 28 29#include <sys/param.h> 30#include <sys/bus.h> 31#include <sys/errno.h> 32#include <sys/kernel.h> 33#include <sys/module.h> 34#include <sys/socket.h> 35#include <sys/sockio.h> 36#include <sys/sysctl.h> 37#include <sys/systm.h> 38 39#include <net/if.h> 40#include <net/if_arp.h> 41#include <net/ethernet.h> 42#include <net/if_dl.h> 43#include <net/if_media.h> 44#include <net/if_types.h> 45 46#include <machine/bus.h> 47#include <dev/iicbus/iic.h> 48#include <dev/iicbus/iiconf.h> 49#include <dev/iicbus/iicbus.h> 50#include <dev/mii/mii.h> 51#include <dev/mii/miivar.h> 52#include <dev/mdio/mdio.h> 53 54#include <dev/etherswitch/etherswitch.h> 55 56#include <dev/etherswitch/arswitch/arswitchreg.h> 57#include <dev/etherswitch/arswitch/arswitchvar.h> 58#include <dev/etherswitch/arswitch/arswitch_reg.h> 59 60#include "mdio_if.h" 61#include "miibus_if.h" 62#include "etherswitch_if.h" 63 64static inline void 65arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, 66 uint16_t *reg) 67{ 68 struct arswitch_softc *sc = device_get_softc(dev); 69 uint16_t page; 70 71 page = (addr >> 9) & 0x1ff; 72 *phy = (addr >> 6) & 0x7; 73 *reg = (addr >> 1) & 0x1f; 74 75 if (sc->page != page) { 76 MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page); 77 DELAY(2000); 78 sc->page = page; 79 } 80} 81 82/* 83 * Read half a register. Some of the registers define control bits, and 84 * the sequence of half-word accesses matters. The register addresses 85 * are word-even (mod 4). 86 */ 87static inline int 88arswitch_readreg16(device_t dev, int addr) 89{ 90 uint16_t phy, reg; 91 92 arswitch_split_setpage(dev, addr, &phy, ®); 93 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); 94} 95 96/* 97 * Write half a register. See above! 98 */ 99static inline int 100arswitch_writereg16(device_t dev, int addr, int data) 101{ 102 uint16_t phy, reg; 103 104 arswitch_split_setpage(dev, addr, &phy, ®); 105 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); 106} 107 108/* 109 * XXX NOTE: 110 * 111 * This may not work for AR7240 series embedded switches - 112 * the per-PHY register space doesn't seem to be exposed. 113 * 114 * In that instance, it may be required to speak via 115 * the internal switch PHY MDIO bus indirection. 116 */ 117void 118arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, 119 uint16_t dbg_data) 120{ 121 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 122 MII_ATH_DBG_ADDR, dbg_addr); 123 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 124 MII_ATH_DBG_DATA, dbg_data); 125} 126 127void 128arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, 129 uint16_t dbg_data) 130{ 131 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 132 MII_ATH_MMD_ADDR, dbg_addr); 133 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 134 MII_ATH_MMD_DATA, dbg_data); 135} 136 137static uint32_t 138arswitch_reg_read32(device_t dev, int phy, int reg) 139{ 140 uint16_t lo, hi; 141 lo = MDIO_READREG(device_get_parent(dev), phy, reg); 142 hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1); 143 144 return (hi << 16) | lo; 145} 146 147static int 148arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value) 149{ 150 struct arswitch_softc *sc; 151 int r; 152 uint16_t lo, hi; 153 154 sc = device_get_softc(dev); 155 lo = value & 0xffff; 156 hi = (uint16_t) (value >> 16); 157 158 if (sc->mii_lo_first) { 159 r = MDIO_WRITEREG(device_get_parent(dev), 160 phy, reg, lo); 161 r |= MDIO_WRITEREG(device_get_parent(dev), 162 phy, reg + 1, hi); 163 } else { 164 r = MDIO_WRITEREG(device_get_parent(dev), 165 phy, reg + 1, hi); 166 r |= MDIO_WRITEREG(device_get_parent(dev), 167 phy, reg, lo); 168 } 169 170 return r; 171} 172 173int 174arswitch_readreg(device_t dev, int addr) 175{ 176 uint16_t phy, reg; 177 178 arswitch_split_setpage(dev, addr, &phy, ®); 179 return arswitch_reg_read32(dev, 0x10 | phy, reg); 180} 181 182int 183arswitch_writereg(device_t dev, int addr, int value) 184{ 185 struct arswitch_softc *sc; 186 uint16_t phy, reg; 187 188 sc = device_get_softc(dev); 189 190 arswitch_split_setpage(dev, addr, &phy, ®); 191 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 192} 193 194/* 195 * Read/write 16 bit values in the switch register space. 196 * 197 * Some of the registers are control registers (eg the MDIO 198 * data versus control space) and so need to be treated 199 * differently. 200 */ 201int 202arswitch_readreg_lsb(device_t dev, int addr) 203{ 204 205 return (arswitch_readreg16(dev, addr)); 206} 207 208int 209arswitch_readreg_msb(device_t dev, int addr) 210{ 211 212 return (arswitch_readreg16(dev, addr + 2) << 16); 213} 214 215int 216arswitch_writereg_lsb(device_t dev, int addr, int data) 217{ 218 219 return (arswitch_writereg16(dev, addr, data & 0xffff)); 220} 221 222int 223arswitch_writereg_msb(device_t dev, int addr, int data) 224{ 225 226 return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff)); 227} 228 229int 230arswitch_modifyreg(device_t dev, int addr, int mask, int set) 231{ 232 int value; 233 uint16_t phy, reg; 234 235 arswitch_split_setpage(dev, addr, &phy, ®); 236 237 value = arswitch_reg_read32(dev, 0x10 | phy, reg); 238 value &= ~mask; 239 value |= set; 240 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 241} 242 243int 244arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout) 245{ 246 int err, v; 247 uint16_t phy, reg; 248 249 arswitch_split_setpage(dev, addr, &phy, ®); 250 251 err = -1; 252 while (1) { 253 v = arswitch_reg_read32(dev, 0x10 | phy, reg); 254 v &= mask; 255 if (v == val) { 256 err = 0; 257 break; 258 } 259 if (!timeout) 260 break; 261 DELAY(1); 262 timeout--; 263 } 264 return (err); 265} 266