e1000_phy.c revision 219753
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.c 219753 2011-03-18 18:54:00Z jfv $*/ 34 35#include "e1000_api.h" 36 37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read); 40static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44/* Cable length tables */ 45static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64/** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71{ 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.read_reg = e1000_null_read_reg; 86 phy->ops.read_reg_locked = e1000_null_read_reg; 87 phy->ops.release = e1000_null_phy_generic; 88 phy->ops.reset = e1000_null_ops_generic; 89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 91 phy->ops.write_reg = e1000_null_write_reg; 92 phy->ops.write_reg_locked = e1000_null_write_reg; 93 phy->ops.power_up = e1000_null_phy_generic; 94 phy->ops.power_down = e1000_null_phy_generic; 95 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 96} 97 98/** 99 * e1000_null_read_reg - No-op function, return 0 100 * @hw: pointer to the HW structure 101 **/ 102s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 103{ 104 DEBUGFUNC("e1000_null_read_reg"); 105 return E1000_SUCCESS; 106} 107 108/** 109 * e1000_null_phy_generic - No-op function, return void 110 * @hw: pointer to the HW structure 111 **/ 112void e1000_null_phy_generic(struct e1000_hw *hw) 113{ 114 DEBUGFUNC("e1000_null_phy_generic"); 115 return; 116} 117 118/** 119 * e1000_null_lplu_state - No-op function, return 0 120 * @hw: pointer to the HW structure 121 **/ 122s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 123{ 124 DEBUGFUNC("e1000_null_lplu_state"); 125 return E1000_SUCCESS; 126} 127 128/** 129 * e1000_null_write_reg - No-op function, return 0 130 * @hw: pointer to the HW structure 131 **/ 132s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 133{ 134 DEBUGFUNC("e1000_null_write_reg"); 135 return E1000_SUCCESS; 136} 137 138/** 139 * e1000_check_reset_block_generic - Check if PHY reset is blocked 140 * @hw: pointer to the HW structure 141 * 142 * Read the PHY management control register and check whether a PHY reset 143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 144 * return E1000_BLK_PHY_RESET (12). 145 **/ 146s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 147{ 148 u32 manc; 149 150 DEBUGFUNC("e1000_check_reset_block"); 151 152 manc = E1000_READ_REG(hw, E1000_MANC); 153 154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 155 E1000_BLK_PHY_RESET : E1000_SUCCESS; 156} 157 158/** 159 * e1000_get_phy_id - Retrieve the PHY ID and revision 160 * @hw: pointer to the HW structure 161 * 162 * Reads the PHY registers and stores the PHY ID and possibly the PHY 163 * revision in the hardware structure. 164 **/ 165s32 e1000_get_phy_id(struct e1000_hw *hw) 166{ 167 struct e1000_phy_info *phy = &hw->phy; 168 s32 ret_val = E1000_SUCCESS; 169 u16 phy_id; 170 u16 retry_count = 0; 171 172 DEBUGFUNC("e1000_get_phy_id"); 173 174 if (!(phy->ops.read_reg)) 175 goto out; 176 177 while (retry_count < 2) { 178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 179 if (ret_val) 180 goto out; 181 182 phy->id = (u32)(phy_id << 16); 183 usec_delay(20); 184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 185 if (ret_val) 186 goto out; 187 188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 190 191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 192 goto out; 193 194 retry_count++; 195 } 196out: 197 return ret_val; 198} 199 200/** 201 * e1000_phy_reset_dsp_generic - Reset PHY DSP 202 * @hw: pointer to the HW structure 203 * 204 * Reset the digital signal processor. 205 **/ 206s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 207{ 208 s32 ret_val = E1000_SUCCESS; 209 210 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 211 212 if (!(hw->phy.ops.write_reg)) 213 goto out; 214 215 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 216 if (ret_val) 217 goto out; 218 219 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 220 221out: 222 return ret_val; 223} 224 225/** 226 * e1000_read_phy_reg_mdic - Read MDI control register 227 * @hw: pointer to the HW structure 228 * @offset: register offset to be read 229 * @data: pointer to the read data 230 * 231 * Reads the MDI control register in the PHY at offset and stores the 232 * information read to data. 233 **/ 234s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 235{ 236 struct e1000_phy_info *phy = &hw->phy; 237 u32 i, mdic = 0; 238 s32 ret_val = E1000_SUCCESS; 239 240 DEBUGFUNC("e1000_read_phy_reg_mdic"); 241 242 if (offset > MAX_PHY_REG_ADDRESS) { 243 DEBUGOUT1("PHY Address %d is out of range\n", offset); 244 return -E1000_ERR_PARAM; 245 } 246 247 /* 248 * Set up Op-code, Phy Address, and register offset in the MDI 249 * Control register. The MAC will take care of interfacing with the 250 * PHY to retrieve the desired data. 251 */ 252 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 253 (phy->addr << E1000_MDIC_PHY_SHIFT) | 254 (E1000_MDIC_OP_READ)); 255 256 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 257 258 /* 259 * Poll the ready bit to see if the MDI read completed 260 * Increasing the time out as testing showed failures with 261 * the lower time out 262 */ 263 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 264 usec_delay(50); 265 mdic = E1000_READ_REG(hw, E1000_MDIC); 266 if (mdic & E1000_MDIC_READY) 267 break; 268 } 269 if (!(mdic & E1000_MDIC_READY)) { 270 DEBUGOUT("MDI Read did not complete\n"); 271 ret_val = -E1000_ERR_PHY; 272 goto out; 273 } 274 if (mdic & E1000_MDIC_ERROR) { 275 DEBUGOUT("MDI Error\n"); 276 ret_val = -E1000_ERR_PHY; 277 goto out; 278 } 279 *data = (u16) mdic; 280 281 /* 282 * Allow some time after each MDIC transaction to avoid 283 * reading duplicate data in the next MDIC transaction. 284 */ 285 if (hw->mac.type == e1000_pch2lan) 286 usec_delay(100); 287 288out: 289 return ret_val; 290} 291 292/** 293 * e1000_write_phy_reg_mdic - Write MDI control register 294 * @hw: pointer to the HW structure 295 * @offset: register offset to write to 296 * @data: data to write to register at offset 297 * 298 * Writes data to MDI control register in the PHY at offset. 299 **/ 300s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 301{ 302 struct e1000_phy_info *phy = &hw->phy; 303 u32 i, mdic = 0; 304 s32 ret_val = E1000_SUCCESS; 305 306 DEBUGFUNC("e1000_write_phy_reg_mdic"); 307 308 if (offset > MAX_PHY_REG_ADDRESS) { 309 DEBUGOUT1("PHY Address %d is out of range\n", offset); 310 return -E1000_ERR_PARAM; 311 } 312 313 /* 314 * Set up Op-code, Phy Address, and register offset in the MDI 315 * Control register. The MAC will take care of interfacing with the 316 * PHY to retrieve the desired data. 317 */ 318 mdic = (((u32)data) | 319 (offset << E1000_MDIC_REG_SHIFT) | 320 (phy->addr << E1000_MDIC_PHY_SHIFT) | 321 (E1000_MDIC_OP_WRITE)); 322 323 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 324 325 /* 326 * Poll the ready bit to see if the MDI read completed 327 * Increasing the time out as testing showed failures with 328 * the lower time out 329 */ 330 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 331 usec_delay(50); 332 mdic = E1000_READ_REG(hw, E1000_MDIC); 333 if (mdic & E1000_MDIC_READY) 334 break; 335 } 336 if (!(mdic & E1000_MDIC_READY)) { 337 DEBUGOUT("MDI Write did not complete\n"); 338 ret_val = -E1000_ERR_PHY; 339 goto out; 340 } 341 if (mdic & E1000_MDIC_ERROR) { 342 DEBUGOUT("MDI Error\n"); 343 ret_val = -E1000_ERR_PHY; 344 goto out; 345 } 346 347 /* 348 * Allow some time after each MDIC transaction to avoid 349 * reading duplicate data in the next MDIC transaction. 350 */ 351 if (hw->mac.type == e1000_pch2lan) 352 usec_delay(100); 353 354out: 355 return ret_val; 356} 357 358/** 359 * e1000_read_phy_reg_i2c - Read PHY register using i2c 360 * @hw: pointer to the HW structure 361 * @offset: register offset to be read 362 * @data: pointer to the read data 363 * 364 * Reads the PHY register at offset using the i2c interface and stores the 365 * retrieved information in data. 366 **/ 367s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 368{ 369 struct e1000_phy_info *phy = &hw->phy; 370 u32 i, i2ccmd = 0; 371 372 DEBUGFUNC("e1000_read_phy_reg_i2c"); 373 374 /* 375 * Set up Op-code, Phy Address, and register address in the I2CCMD 376 * register. The MAC will take care of interfacing with the 377 * PHY to retrieve the desired data. 378 */ 379 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 380 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 381 (E1000_I2CCMD_OPCODE_READ)); 382 383 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 384 385 /* Poll the ready bit to see if the I2C read completed */ 386 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 387 usec_delay(50); 388 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 389 if (i2ccmd & E1000_I2CCMD_READY) 390 break; 391 } 392 if (!(i2ccmd & E1000_I2CCMD_READY)) { 393 DEBUGOUT("I2CCMD Read did not complete\n"); 394 return -E1000_ERR_PHY; 395 } 396 if (i2ccmd & E1000_I2CCMD_ERROR) { 397 DEBUGOUT("I2CCMD Error bit set\n"); 398 return -E1000_ERR_PHY; 399 } 400 401 /* Need to byte-swap the 16-bit value. */ 402 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 403 404 return E1000_SUCCESS; 405} 406 407/** 408 * e1000_write_phy_reg_i2c - Write PHY register using i2c 409 * @hw: pointer to the HW structure 410 * @offset: register offset to write to 411 * @data: data to write at register offset 412 * 413 * Writes the data to PHY register at the offset using the i2c interface. 414 **/ 415s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 416{ 417 struct e1000_phy_info *phy = &hw->phy; 418 u32 i, i2ccmd = 0; 419 u16 phy_data_swapped; 420 421 DEBUGFUNC("e1000_write_phy_reg_i2c"); 422 423 /* Swap the data bytes for the I2C interface */ 424 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 425 426 /* 427 * Set up Op-code, Phy Address, and register address in the I2CCMD 428 * register. The MAC will take care of interfacing with the 429 * PHY to retrieve the desired data. 430 */ 431 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 432 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 433 E1000_I2CCMD_OPCODE_WRITE | 434 phy_data_swapped); 435 436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 437 438 /* Poll the ready bit to see if the I2C read completed */ 439 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 440 usec_delay(50); 441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 442 if (i2ccmd & E1000_I2CCMD_READY) 443 break; 444 } 445 if (!(i2ccmd & E1000_I2CCMD_READY)) { 446 DEBUGOUT("I2CCMD Write did not complete\n"); 447 return -E1000_ERR_PHY; 448 } 449 if (i2ccmd & E1000_I2CCMD_ERROR) { 450 DEBUGOUT("I2CCMD Error bit set\n"); 451 return -E1000_ERR_PHY; 452 } 453 454 return E1000_SUCCESS; 455} 456 457/** 458 * e1000_read_phy_reg_m88 - Read m88 PHY register 459 * @hw: pointer to the HW structure 460 * @offset: register offset to be read 461 * @data: pointer to the read data 462 * 463 * Acquires semaphore, if necessary, then reads the PHY register at offset 464 * and storing the retrieved information in data. Release any acquired 465 * semaphores before exiting. 466 **/ 467s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 468{ 469 s32 ret_val = E1000_SUCCESS; 470 471 DEBUGFUNC("e1000_read_phy_reg_m88"); 472 473 if (!(hw->phy.ops.acquire)) 474 goto out; 475 476 ret_val = hw->phy.ops.acquire(hw); 477 if (ret_val) 478 goto out; 479 480 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 481 data); 482 483 hw->phy.ops.release(hw); 484 485out: 486 return ret_val; 487} 488 489/** 490 * e1000_write_phy_reg_m88 - Write m88 PHY register 491 * @hw: pointer to the HW structure 492 * @offset: register offset to write to 493 * @data: data to write at register offset 494 * 495 * Acquires semaphore, if necessary, then writes the data to PHY register 496 * at the offset. Release any acquired semaphores before exiting. 497 **/ 498s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 499{ 500 s32 ret_val = E1000_SUCCESS; 501 502 DEBUGFUNC("e1000_write_phy_reg_m88"); 503 504 if (!(hw->phy.ops.acquire)) 505 goto out; 506 507 ret_val = hw->phy.ops.acquire(hw); 508 if (ret_val) 509 goto out; 510 511 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 512 data); 513 514 hw->phy.ops.release(hw); 515 516out: 517 return ret_val; 518} 519 520/** 521 * __e1000_read_phy_reg_igp - Read igp PHY register 522 * @hw: pointer to the HW structure 523 * @offset: register offset to be read 524 * @data: pointer to the read data 525 * @locked: semaphore has already been acquired or not 526 * 527 * Acquires semaphore, if necessary, then reads the PHY register at offset 528 * and stores the retrieved information in data. Release any acquired 529 * semaphores before exiting. 530 **/ 531static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 532 bool locked) 533{ 534 s32 ret_val = E1000_SUCCESS; 535 536 DEBUGFUNC("__e1000_read_phy_reg_igp"); 537 538 if (!locked) { 539 if (!(hw->phy.ops.acquire)) 540 goto out; 541 542 ret_val = hw->phy.ops.acquire(hw); 543 if (ret_val) 544 goto out; 545 } 546 547 if (offset > MAX_PHY_MULTI_PAGE_REG) { 548 ret_val = e1000_write_phy_reg_mdic(hw, 549 IGP01E1000_PHY_PAGE_SELECT, 550 (u16)offset); 551 if (ret_val) 552 goto release; 553 } 554 555 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 556 data); 557 558release: 559 if (!locked) 560 hw->phy.ops.release(hw); 561out: 562 return ret_val; 563} 564 565/** 566 * e1000_read_phy_reg_igp - Read igp PHY register 567 * @hw: pointer to the HW structure 568 * @offset: register offset to be read 569 * @data: pointer to the read data 570 * 571 * Acquires semaphore then reads the PHY register at offset and stores the 572 * retrieved information in data. 573 * Release the acquired semaphore before exiting. 574 **/ 575s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 576{ 577 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 578} 579 580/** 581 * e1000_read_phy_reg_igp_locked - Read igp PHY register 582 * @hw: pointer to the HW structure 583 * @offset: register offset to be read 584 * @data: pointer to the read data 585 * 586 * Reads the PHY register at offset and stores the retrieved information 587 * in data. Assumes semaphore already acquired. 588 **/ 589s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 590{ 591 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 592} 593 594/** 595 * e1000_write_phy_reg_igp - Write igp PHY register 596 * @hw: pointer to the HW structure 597 * @offset: register offset to write to 598 * @data: data to write at register offset 599 * @locked: semaphore has already been acquired or not 600 * 601 * Acquires semaphore, if necessary, then writes the data to PHY register 602 * at the offset. Release any acquired semaphores before exiting. 603 **/ 604static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 605 bool locked) 606{ 607 s32 ret_val = E1000_SUCCESS; 608 609 DEBUGFUNC("e1000_write_phy_reg_igp"); 610 611 if (!locked) { 612 if (!(hw->phy.ops.acquire)) 613 goto out; 614 615 ret_val = hw->phy.ops.acquire(hw); 616 if (ret_val) 617 goto out; 618 } 619 620 if (offset > MAX_PHY_MULTI_PAGE_REG) { 621 ret_val = e1000_write_phy_reg_mdic(hw, 622 IGP01E1000_PHY_PAGE_SELECT, 623 (u16)offset); 624 if (ret_val) 625 goto release; 626 } 627 628 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 629 data); 630 631release: 632 if (!locked) 633 hw->phy.ops.release(hw); 634 635out: 636 return ret_val; 637} 638 639/** 640 * e1000_write_phy_reg_igp - Write igp PHY register 641 * @hw: pointer to the HW structure 642 * @offset: register offset to write to 643 * @data: data to write at register offset 644 * 645 * Acquires semaphore then writes the data to PHY register 646 * at the offset. Release any acquired semaphores before exiting. 647 **/ 648s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 649{ 650 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 651} 652 653/** 654 * e1000_write_phy_reg_igp_locked - Write igp PHY register 655 * @hw: pointer to the HW structure 656 * @offset: register offset to write to 657 * @data: data to write at register offset 658 * 659 * Writes the data to PHY register at the offset. 660 * Assumes semaphore already acquired. 661 **/ 662s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 663{ 664 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 665} 666 667/** 668 * __e1000_read_kmrn_reg - Read kumeran register 669 * @hw: pointer to the HW structure 670 * @offset: register offset to be read 671 * @data: pointer to the read data 672 * @locked: semaphore has already been acquired or not 673 * 674 * Acquires semaphore, if necessary. Then reads the PHY register at offset 675 * using the kumeran interface. The information retrieved is stored in data. 676 * Release any acquired semaphores before exiting. 677 **/ 678static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 679 bool locked) 680{ 681 u32 kmrnctrlsta; 682 s32 ret_val = E1000_SUCCESS; 683 684 DEBUGFUNC("__e1000_read_kmrn_reg"); 685 686 if (!locked) { 687 if (!(hw->phy.ops.acquire)) 688 goto out; 689 690 ret_val = hw->phy.ops.acquire(hw); 691 if (ret_val) 692 goto out; 693 } 694 695 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 696 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 697 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 698 699 usec_delay(2); 700 701 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 702 *data = (u16)kmrnctrlsta; 703 704 if (!locked) 705 hw->phy.ops.release(hw); 706 707out: 708 return ret_val; 709} 710 711/** 712 * e1000_read_kmrn_reg_generic - Read kumeran register 713 * @hw: pointer to the HW structure 714 * @offset: register offset to be read 715 * @data: pointer to the read data 716 * 717 * Acquires semaphore then reads the PHY register at offset using the 718 * kumeran interface. The information retrieved is stored in data. 719 * Release the acquired semaphore before exiting. 720 **/ 721s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 722{ 723 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 724} 725 726/** 727 * e1000_read_kmrn_reg_locked - Read kumeran register 728 * @hw: pointer to the HW structure 729 * @offset: register offset to be read 730 * @data: pointer to the read data 731 * 732 * Reads the PHY register at offset using the kumeran interface. The 733 * information retrieved is stored in data. 734 * Assumes semaphore already acquired. 735 **/ 736s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 737{ 738 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 739} 740 741/** 742 * __e1000_write_kmrn_reg - Write kumeran register 743 * @hw: pointer to the HW structure 744 * @offset: register offset to write to 745 * @data: data to write at register offset 746 * @locked: semaphore has already been acquired or not 747 * 748 * Acquires semaphore, if necessary. Then write the data to PHY register 749 * at the offset using the kumeran interface. Release any acquired semaphores 750 * before exiting. 751 **/ 752static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 753 bool locked) 754{ 755 u32 kmrnctrlsta; 756 s32 ret_val = E1000_SUCCESS; 757 758 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 759 760 if (!locked) { 761 if (!(hw->phy.ops.acquire)) 762 goto out; 763 764 ret_val = hw->phy.ops.acquire(hw); 765 if (ret_val) 766 goto out; 767 } 768 769 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 770 E1000_KMRNCTRLSTA_OFFSET) | data; 771 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 772 773 usec_delay(2); 774 775 if (!locked) 776 hw->phy.ops.release(hw); 777 778out: 779 return ret_val; 780} 781 782/** 783 * e1000_write_kmrn_reg_generic - Write kumeran register 784 * @hw: pointer to the HW structure 785 * @offset: register offset to write to 786 * @data: data to write at register offset 787 * 788 * Acquires semaphore then writes the data to the PHY register at the offset 789 * using the kumeran interface. Release the acquired semaphore before exiting. 790 **/ 791s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 792{ 793 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 794} 795 796/** 797 * e1000_write_kmrn_reg_locked - Write kumeran register 798 * @hw: pointer to the HW structure 799 * @offset: register offset to write to 800 * @data: data to write at register offset 801 * 802 * Write the data to PHY register at the offset using the kumeran interface. 803 * Assumes semaphore already acquired. 804 **/ 805s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 806{ 807 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 808} 809 810/** 811 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 812 * @hw: pointer to the HW structure 813 * 814 * Sets up Carrier-sense on Transmit and downshift values. 815 **/ 816s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 817{ 818 s32 ret_val; 819 u16 phy_data; 820 821 DEBUGFUNC("e1000_copper_link_setup_82577"); 822 823 if (hw->phy.reset_disable) { 824 ret_val = E1000_SUCCESS; 825 goto out; 826 } 827 828 if (hw->phy.type == e1000_phy_82580) { 829 ret_val = hw->phy.ops.reset(hw); 830 if (ret_val) { 831 DEBUGOUT("Error resetting the PHY.\n"); 832 goto out; 833 } 834 } 835 836 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 837 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 838 if (ret_val) 839 goto out; 840 841 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 842 843 /* Enable downshift */ 844 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 845 846 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 847 848out: 849 return ret_val; 850} 851 852/** 853 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 854 * @hw: pointer to the HW structure 855 * 856 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 857 * and downshift values are set also. 858 **/ 859s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 860{ 861 struct e1000_phy_info *phy = &hw->phy; 862 s32 ret_val; 863 u16 phy_data; 864 865 DEBUGFUNC("e1000_copper_link_setup_m88"); 866 867 if (phy->reset_disable) { 868 ret_val = E1000_SUCCESS; 869 goto out; 870 } 871 872 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 873 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 874 if (ret_val) 875 goto out; 876 877 /* For BM PHY this bit is downshift enable */ 878 if (phy->type != e1000_phy_bm) 879 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 880 881 /* 882 * Options: 883 * MDI/MDI-X = 0 (default) 884 * 0 - Auto for all speeds 885 * 1 - MDI mode 886 * 2 - MDI-X mode 887 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 888 */ 889 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 890 891 switch (phy->mdix) { 892 case 1: 893 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 894 break; 895 case 2: 896 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 897 break; 898 case 3: 899 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 900 break; 901 case 0: 902 default: 903 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 904 break; 905 } 906 907 /* 908 * Options: 909 * disable_polarity_correction = 0 (default) 910 * Automatic Correction for Reversed Cable Polarity 911 * 0 - Disabled 912 * 1 - Enabled 913 */ 914 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 915 if (phy->disable_polarity_correction == 1) 916 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 917 918 /* Enable downshift on BM (disabled by default) */ 919 if (phy->type == e1000_phy_bm) 920 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 921 922 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 923 if (ret_val) 924 goto out; 925 926 if ((phy->type == e1000_phy_m88) && 927 (phy->revision < E1000_REVISION_4) && 928 (phy->id != BME1000_E_PHY_ID_R2)) { 929 /* 930 * Force TX_CLK in the Extended PHY Specific Control Register 931 * to 25MHz clock. 932 */ 933 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 934 &phy_data); 935 if (ret_val) 936 goto out; 937 938 phy_data |= M88E1000_EPSCR_TX_CLK_25; 939 940 if ((phy->revision == E1000_REVISION_2) && 941 (phy->id == M88E1111_I_PHY_ID)) { 942 /* 82573L PHY - set the downshift counter to 5x. */ 943 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 944 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 945 } else { 946 /* Configure Master and Slave downshift values */ 947 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 948 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 949 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 950 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 951 } 952 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 953 phy_data); 954 if (ret_val) 955 goto out; 956 } 957 958 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 959 /* Set PHY page 0, register 29 to 0x0003 */ 960 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 961 if (ret_val) 962 goto out; 963 964 /* Set PHY page 0, register 30 to 0x0000 */ 965 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 966 if (ret_val) 967 goto out; 968 } 969 970 /* Commit the changes. */ 971 ret_val = phy->ops.commit(hw); 972 if (ret_val) { 973 DEBUGOUT("Error committing the PHY changes\n"); 974 goto out; 975 } 976 977 if (phy->type == e1000_phy_82578) { 978 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 979 &phy_data); 980 if (ret_val) 981 goto out; 982 983 /* 82578 PHY - set the downshift count to 1x. */ 984 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 985 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 986 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 987 phy_data); 988 if (ret_val) 989 goto out; 990 } 991 992out: 993 return ret_val; 994} 995 996/** 997 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 998 * @hw: pointer to the HW structure 999 * 1000 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1001 * Also enables and sets the downshift parameters. 1002 **/ 1003s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1004{ 1005 struct e1000_phy_info *phy = &hw->phy; 1006 s32 ret_val; 1007 u16 phy_data; 1008 1009 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1010 1011 if (phy->reset_disable) { 1012 ret_val = E1000_SUCCESS; 1013 goto out; 1014 } 1015 1016 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1017 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1018 if (ret_val) 1019 goto out; 1020 1021 /* 1022 * Options: 1023 * MDI/MDI-X = 0 (default) 1024 * 0 - Auto for all speeds 1025 * 1 - MDI mode 1026 * 2 - MDI-X mode 1027 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1028 */ 1029 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1030 1031 switch (phy->mdix) { 1032 case 1: 1033 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1034 break; 1035 case 2: 1036 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1037 break; 1038 case 3: 1039 /* M88E1112 does not support this mode) */ 1040 if (phy->id != M88E1112_E_PHY_ID) { 1041 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1042 break; 1043 } 1044 case 0: 1045 default: 1046 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1047 break; 1048 } 1049 1050 /* 1051 * Options: 1052 * disable_polarity_correction = 0 (default) 1053 * Automatic Correction for Reversed Cable Polarity 1054 * 0 - Disabled 1055 * 1 - Enabled 1056 */ 1057 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1058 if (phy->disable_polarity_correction == 1) 1059 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1060 1061 /* Enable downshift and setting it to X6 */ 1062 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1063 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1064 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1065 1066 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1067 if (ret_val) 1068 goto out; 1069 1070 /* Commit the changes. */ 1071 ret_val = phy->ops.commit(hw); 1072 if (ret_val) { 1073 DEBUGOUT("Error committing the PHY changes\n"); 1074 goto out; 1075 } 1076 1077out: 1078 return ret_val; 1079} 1080 1081/** 1082 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1083 * @hw: pointer to the HW structure 1084 * 1085 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1086 * igp PHY's. 1087 **/ 1088s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1089{ 1090 struct e1000_phy_info *phy = &hw->phy; 1091 s32 ret_val; 1092 u16 data; 1093 1094 DEBUGFUNC("e1000_copper_link_setup_igp"); 1095 1096 if (phy->reset_disable) { 1097 ret_val = E1000_SUCCESS; 1098 goto out; 1099 } 1100 1101 ret_val = hw->phy.ops.reset(hw); 1102 if (ret_val) { 1103 DEBUGOUT("Error resetting the PHY.\n"); 1104 goto out; 1105 } 1106 1107 /* 1108 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1109 * timeout issues when LFS is enabled. 1110 */ 1111 msec_delay(100); 1112 1113 /* 1114 * The NVM settings will configure LPLU in D3 for 1115 * non-IGP1 PHYs. 1116 */ 1117 if (phy->type == e1000_phy_igp) { 1118 /* disable lplu d3 during driver init */ 1119 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1120 if (ret_val) { 1121 DEBUGOUT("Error Disabling LPLU D3\n"); 1122 goto out; 1123 } 1124 } 1125 1126 /* disable lplu d0 during driver init */ 1127 if (hw->phy.ops.set_d0_lplu_state) { 1128 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1129 if (ret_val) { 1130 DEBUGOUT("Error Disabling LPLU D0\n"); 1131 goto out; 1132 } 1133 } 1134 /* Configure mdi-mdix settings */ 1135 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1136 if (ret_val) 1137 goto out; 1138 1139 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1140 1141 switch (phy->mdix) { 1142 case 1: 1143 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1144 break; 1145 case 2: 1146 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1147 break; 1148 case 0: 1149 default: 1150 data |= IGP01E1000_PSCR_AUTO_MDIX; 1151 break; 1152 } 1153 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1154 if (ret_val) 1155 goto out; 1156 1157 /* set auto-master slave resolution settings */ 1158 if (hw->mac.autoneg) { 1159 /* 1160 * when autonegotiation advertisement is only 1000Mbps then we 1161 * should disable SmartSpeed and enable Auto MasterSlave 1162 * resolution as hardware default. 1163 */ 1164 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1165 /* Disable SmartSpeed */ 1166 ret_val = phy->ops.read_reg(hw, 1167 IGP01E1000_PHY_PORT_CONFIG, 1168 &data); 1169 if (ret_val) 1170 goto out; 1171 1172 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1173 ret_val = phy->ops.write_reg(hw, 1174 IGP01E1000_PHY_PORT_CONFIG, 1175 data); 1176 if (ret_val) 1177 goto out; 1178 1179 /* Set auto Master/Slave resolution process */ 1180 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1181 if (ret_val) 1182 goto out; 1183 1184 data &= ~CR_1000T_MS_ENABLE; 1185 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1186 if (ret_val) 1187 goto out; 1188 } 1189 1190 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1191 if (ret_val) 1192 goto out; 1193 1194 /* load defaults for future use */ 1195 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 1196 ((data & CR_1000T_MS_VALUE) ? 1197 e1000_ms_force_master : 1198 e1000_ms_force_slave) : 1199 e1000_ms_auto; 1200 1201 switch (phy->ms_type) { 1202 case e1000_ms_force_master: 1203 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1204 break; 1205 case e1000_ms_force_slave: 1206 data |= CR_1000T_MS_ENABLE; 1207 data &= ~(CR_1000T_MS_VALUE); 1208 break; 1209 case e1000_ms_auto: 1210 data &= ~CR_1000T_MS_ENABLE; 1211 default: 1212 break; 1213 } 1214 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1215 if (ret_val) 1216 goto out; 1217 } 1218 1219out: 1220 return ret_val; 1221} 1222 1223/** 1224 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1225 * @hw: pointer to the HW structure 1226 * 1227 * Performs initial bounds checking on autoneg advertisement parameter, then 1228 * configure to advertise the full capability. Setup the PHY to autoneg 1229 * and restart the negotiation process between the link partner. If 1230 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1231 **/ 1232s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1233{ 1234 struct e1000_phy_info *phy = &hw->phy; 1235 s32 ret_val; 1236 u16 phy_ctrl; 1237 1238 DEBUGFUNC("e1000_copper_link_autoneg"); 1239 1240 /* 1241 * Perform some bounds checking on the autoneg advertisement 1242 * parameter. 1243 */ 1244 phy->autoneg_advertised &= phy->autoneg_mask; 1245 1246 /* 1247 * If autoneg_advertised is zero, we assume it was not defaulted 1248 * by the calling code so we set to advertise full capability. 1249 */ 1250 if (phy->autoneg_advertised == 0) 1251 phy->autoneg_advertised = phy->autoneg_mask; 1252 1253 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1254 ret_val = e1000_phy_setup_autoneg(hw); 1255 if (ret_val) { 1256 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1257 goto out; 1258 } 1259 DEBUGOUT("Restarting Auto-Neg\n"); 1260 1261 /* 1262 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1263 * the Auto Neg Restart bit in the PHY control register. 1264 */ 1265 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1266 if (ret_val) 1267 goto out; 1268 1269 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1270 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1271 if (ret_val) 1272 goto out; 1273 1274 /* 1275 * Does the user want to wait for Auto-Neg to complete here, or 1276 * check at a later time (for example, callback routine). 1277 */ 1278 if (phy->autoneg_wait_to_complete) { 1279 ret_val = hw->mac.ops.wait_autoneg(hw); 1280 if (ret_val) { 1281 DEBUGOUT("Error while waiting for " 1282 "autoneg to complete\n"); 1283 goto out; 1284 } 1285 } 1286 1287 hw->mac.get_link_status = TRUE; 1288 1289out: 1290 return ret_val; 1291} 1292 1293/** 1294 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1295 * @hw: pointer to the HW structure 1296 * 1297 * Reads the MII auto-neg advertisement register and/or the 1000T control 1298 * register and if the PHY is already setup for auto-negotiation, then 1299 * return successful. Otherwise, setup advertisement and flow control to 1300 * the appropriate values for the wanted auto-negotiation. 1301 **/ 1302s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1303{ 1304 struct e1000_phy_info *phy = &hw->phy; 1305 s32 ret_val; 1306 u16 mii_autoneg_adv_reg; 1307 u16 mii_1000t_ctrl_reg = 0; 1308 1309 DEBUGFUNC("e1000_phy_setup_autoneg"); 1310 1311 phy->autoneg_advertised &= phy->autoneg_mask; 1312 1313 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1314 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1315 if (ret_val) 1316 goto out; 1317 1318 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1319 /* Read the MII 1000Base-T Control Register (Address 9). */ 1320 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1321 &mii_1000t_ctrl_reg); 1322 if (ret_val) 1323 goto out; 1324 } 1325 1326 /* 1327 * Need to parse both autoneg_advertised and fc and set up 1328 * the appropriate PHY registers. First we will parse for 1329 * autoneg_advertised software override. Since we can advertise 1330 * a plethora of combinations, we need to check each bit 1331 * individually. 1332 */ 1333 1334 /* 1335 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1336 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1337 * the 1000Base-T Control Register (Address 9). 1338 */ 1339 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1340 NWAY_AR_100TX_HD_CAPS | 1341 NWAY_AR_10T_FD_CAPS | 1342 NWAY_AR_10T_HD_CAPS); 1343 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1344 1345 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1346 1347 /* Do we want to advertise 10 Mb Half Duplex? */ 1348 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1349 DEBUGOUT("Advertise 10mb Half duplex\n"); 1350 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1351 } 1352 1353 /* Do we want to advertise 10 Mb Full Duplex? */ 1354 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1355 DEBUGOUT("Advertise 10mb Full duplex\n"); 1356 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1357 } 1358 1359 /* Do we want to advertise 100 Mb Half Duplex? */ 1360 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1361 DEBUGOUT("Advertise 100mb Half duplex\n"); 1362 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1363 } 1364 1365 /* Do we want to advertise 100 Mb Full Duplex? */ 1366 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1367 DEBUGOUT("Advertise 100mb Full duplex\n"); 1368 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1369 } 1370 1371 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1372 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1373 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1374 1375 /* Do we want to advertise 1000 Mb Full Duplex? */ 1376 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1377 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1378 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1379 } 1380 1381 /* 1382 * Check for a software override of the flow control settings, and 1383 * setup the PHY advertisement registers accordingly. If 1384 * auto-negotiation is enabled, then software will have to set the 1385 * "PAUSE" bits to the correct value in the Auto-Negotiation 1386 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1387 * negotiation. 1388 * 1389 * The possible values of the "fc" parameter are: 1390 * 0: Flow control is completely disabled 1391 * 1: Rx flow control is enabled (we can receive pause frames 1392 * but not send pause frames). 1393 * 2: Tx flow control is enabled (we can send pause frames 1394 * but we do not support receiving pause frames). 1395 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1396 * other: No software override. The flow control configuration 1397 * in the EEPROM is used. 1398 */ 1399 switch (hw->fc.current_mode) { 1400 case e1000_fc_none: 1401 /* 1402 * Flow control (Rx & Tx) is completely disabled by a 1403 * software over-ride. 1404 */ 1405 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1406 break; 1407 case e1000_fc_rx_pause: 1408 /* 1409 * Rx Flow control is enabled, and Tx Flow control is 1410 * disabled, by a software over-ride. 1411 * 1412 * Since there really isn't a way to advertise that we are 1413 * capable of Rx Pause ONLY, we will advertise that we 1414 * support both symmetric and asymmetric Rx PAUSE. Later 1415 * (in e1000_config_fc_after_link_up) we will disable the 1416 * hw's ability to send PAUSE frames. 1417 */ 1418 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1419 break; 1420 case e1000_fc_tx_pause: 1421 /* 1422 * Tx Flow control is enabled, and Rx Flow control is 1423 * disabled, by a software over-ride. 1424 */ 1425 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1426 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1427 break; 1428 case e1000_fc_full: 1429 /* 1430 * Flow control (both Rx and Tx) is enabled by a software 1431 * over-ride. 1432 */ 1433 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1434 break; 1435 default: 1436 DEBUGOUT("Flow control param set incorrectly\n"); 1437 ret_val = -E1000_ERR_CONFIG; 1438 goto out; 1439 } 1440 1441 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1442 if (ret_val) 1443 goto out; 1444 1445 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1446 1447 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1448 ret_val = phy->ops.write_reg(hw, 1449 PHY_1000T_CTRL, 1450 mii_1000t_ctrl_reg); 1451 if (ret_val) 1452 goto out; 1453 } 1454 1455out: 1456 return ret_val; 1457} 1458 1459/** 1460 * e1000_setup_copper_link_generic - Configure copper link settings 1461 * @hw: pointer to the HW structure 1462 * 1463 * Calls the appropriate function to configure the link for auto-neg or forced 1464 * speed and duplex. Then we check for link, once link is established calls 1465 * to configure collision distance and flow control are called. If link is 1466 * not established, we return -E1000_ERR_PHY (-2). 1467 **/ 1468s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1469{ 1470 s32 ret_val; 1471 bool link; 1472 1473 DEBUGFUNC("e1000_setup_copper_link_generic"); 1474 1475 if (hw->mac.autoneg) { 1476 /* 1477 * Setup autoneg and flow control advertisement and perform 1478 * autonegotiation. 1479 */ 1480 ret_val = e1000_copper_link_autoneg(hw); 1481 if (ret_val) 1482 goto out; 1483 } else { 1484 /* 1485 * PHY will be set to 10H, 10F, 100H or 100F 1486 * depending on user settings. 1487 */ 1488 DEBUGOUT("Forcing Speed and Duplex\n"); 1489 ret_val = hw->phy.ops.force_speed_duplex(hw); 1490 if (ret_val) { 1491 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1492 goto out; 1493 } 1494 } 1495 1496 /* 1497 * Check link status. Wait up to 100 microseconds for link to become 1498 * valid. 1499 */ 1500 ret_val = e1000_phy_has_link_generic(hw, 1501 COPPER_LINK_UP_LIMIT, 1502 10, 1503 &link); 1504 if (ret_val) 1505 goto out; 1506 1507 if (link) { 1508 DEBUGOUT("Valid link established!!!\n"); 1509 e1000_config_collision_dist_generic(hw); 1510 ret_val = e1000_config_fc_after_link_up_generic(hw); 1511 } else { 1512 DEBUGOUT("Unable to establish link!!!\n"); 1513 } 1514 1515out: 1516 return ret_val; 1517} 1518 1519/** 1520 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1521 * @hw: pointer to the HW structure 1522 * 1523 * Calls the PHY setup function to force speed and duplex. Clears the 1524 * auto-crossover to force MDI manually. Waits for link and returns 1525 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1526 **/ 1527s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1528{ 1529 struct e1000_phy_info *phy = &hw->phy; 1530 s32 ret_val; 1531 u16 phy_data; 1532 bool link; 1533 1534 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1535 1536 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1537 if (ret_val) 1538 goto out; 1539 1540 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1541 1542 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1543 if (ret_val) 1544 goto out; 1545 1546 /* 1547 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1548 * forced whenever speed and duplex are forced. 1549 */ 1550 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1551 if (ret_val) 1552 goto out; 1553 1554 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1555 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1556 1557 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1558 if (ret_val) 1559 goto out; 1560 1561 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1562 1563 usec_delay(1); 1564 1565 if (phy->autoneg_wait_to_complete) { 1566 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1567 1568 ret_val = e1000_phy_has_link_generic(hw, 1569 PHY_FORCE_LIMIT, 1570 100000, 1571 &link); 1572 if (ret_val) 1573 goto out; 1574 1575 if (!link) 1576 DEBUGOUT("Link taking longer than expected.\n"); 1577 1578 /* Try once more */ 1579 ret_val = e1000_phy_has_link_generic(hw, 1580 PHY_FORCE_LIMIT, 1581 100000, 1582 &link); 1583 if (ret_val) 1584 goto out; 1585 } 1586 1587out: 1588 return ret_val; 1589} 1590 1591/** 1592 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1593 * @hw: pointer to the HW structure 1594 * 1595 * Calls the PHY setup function to force speed and duplex. Clears the 1596 * auto-crossover to force MDI manually. Resets the PHY to commit the 1597 * changes. If time expires while waiting for link up, we reset the DSP. 1598 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1599 * successful completion, else return corresponding error code. 1600 **/ 1601s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1602{ 1603 struct e1000_phy_info *phy = &hw->phy; 1604 s32 ret_val; 1605 u16 phy_data; 1606 bool link; 1607 1608 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1609 1610 /* 1611 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1612 * forced whenever speed and duplex are forced. 1613 */ 1614 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1615 if (ret_val) 1616 goto out; 1617 1618 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1619 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1620 if (ret_val) 1621 goto out; 1622 1623 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1624 1625 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1626 if (ret_val) 1627 goto out; 1628 1629 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1630 1631 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1632 if (ret_val) 1633 goto out; 1634 1635 /* Reset the phy to commit changes. */ 1636 ret_val = hw->phy.ops.commit(hw); 1637 if (ret_val) 1638 goto out; 1639 1640 if (phy->autoneg_wait_to_complete) { 1641 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1642 1643 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1644 100000, &link); 1645 if (ret_val) 1646 goto out; 1647 1648 if (!link) { 1649 if (hw->phy.type != e1000_phy_m88 || 1650 hw->phy.id == I347AT4_E_PHY_ID || 1651 hw->phy.id == M88E1340M_E_PHY_ID || 1652 hw->phy.id == M88E1112_E_PHY_ID) { 1653 DEBUGOUT("Link taking longer than expected.\n"); 1654 } else { 1655 /* 1656 * We didn't get link. 1657 * Reset the DSP and cross our fingers. 1658 */ 1659 ret_val = phy->ops.write_reg(hw, 1660 M88E1000_PHY_PAGE_SELECT, 1661 0x001d); 1662 if (ret_val) 1663 goto out; 1664 ret_val = e1000_phy_reset_dsp_generic(hw); 1665 if (ret_val) 1666 goto out; 1667 } 1668 } 1669 1670 /* Try once more */ 1671 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1672 100000, &link); 1673 if (ret_val) 1674 goto out; 1675 } 1676 1677 if (hw->phy.type != e1000_phy_m88 || 1678 hw->phy.id == I347AT4_E_PHY_ID || 1679 hw->phy.id == M88E1340M_E_PHY_ID || 1680 hw->phy.id == M88E1112_E_PHY_ID) 1681 goto out; 1682 1683 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1684 if (ret_val) 1685 goto out; 1686 1687 /* 1688 * Resetting the phy means we need to re-force TX_CLK in the 1689 * Extended PHY Specific Control Register to 25MHz clock from 1690 * the reset value of 2.5MHz. 1691 */ 1692 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1693 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1694 if (ret_val) 1695 goto out; 1696 1697 /* 1698 * In addition, we must re-enable CRS on Tx for both half and full 1699 * duplex. 1700 */ 1701 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1702 if (ret_val) 1703 goto out; 1704 1705 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1706 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1707 1708out: 1709 return ret_val; 1710} 1711 1712/** 1713 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1714 * @hw: pointer to the HW structure 1715 * 1716 * Forces the speed and duplex settings of the PHY. 1717 * This is a function pointer entry point only called by 1718 * PHY setup routines. 1719 **/ 1720s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1721{ 1722 struct e1000_phy_info *phy = &hw->phy; 1723 s32 ret_val; 1724 u16 data; 1725 bool link; 1726 1727 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1728 1729 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1730 if (ret_val) 1731 goto out; 1732 1733 e1000_phy_force_speed_duplex_setup(hw, &data); 1734 1735 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1736 if (ret_val) 1737 goto out; 1738 1739 /* Disable MDI-X support for 10/100 */ 1740 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1741 if (ret_val) 1742 goto out; 1743 1744 data &= ~IFE_PMC_AUTO_MDIX; 1745 data &= ~IFE_PMC_FORCE_MDIX; 1746 1747 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1748 if (ret_val) 1749 goto out; 1750 1751 DEBUGOUT1("IFE PMC: %X\n", data); 1752 1753 usec_delay(1); 1754 1755 if (phy->autoneg_wait_to_complete) { 1756 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1757 1758 ret_val = e1000_phy_has_link_generic(hw, 1759 PHY_FORCE_LIMIT, 1760 100000, 1761 &link); 1762 if (ret_val) 1763 goto out; 1764 1765 if (!link) 1766 DEBUGOUT("Link taking longer than expected.\n"); 1767 1768 /* Try once more */ 1769 ret_val = e1000_phy_has_link_generic(hw, 1770 PHY_FORCE_LIMIT, 1771 100000, 1772 &link); 1773 if (ret_val) 1774 goto out; 1775 } 1776 1777out: 1778 return ret_val; 1779} 1780 1781/** 1782 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1783 * @hw: pointer to the HW structure 1784 * @phy_ctrl: pointer to current value of PHY_CONTROL 1785 * 1786 * Forces speed and duplex on the PHY by doing the following: disable flow 1787 * control, force speed/duplex on the MAC, disable auto speed detection, 1788 * disable auto-negotiation, configure duplex, configure speed, configure 1789 * the collision distance, write configuration to CTRL register. The 1790 * caller must write to the PHY_CONTROL register for these settings to 1791 * take affect. 1792 **/ 1793void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1794{ 1795 struct e1000_mac_info *mac = &hw->mac; 1796 u32 ctrl; 1797 1798 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1799 1800 /* Turn off flow control when forcing speed/duplex */ 1801 hw->fc.current_mode = e1000_fc_none; 1802 1803 /* Force speed/duplex on the mac */ 1804 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1805 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1806 ctrl &= ~E1000_CTRL_SPD_SEL; 1807 1808 /* Disable Auto Speed Detection */ 1809 ctrl &= ~E1000_CTRL_ASDE; 1810 1811 /* Disable autoneg on the phy */ 1812 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1813 1814 /* Forcing Full or Half Duplex? */ 1815 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1816 ctrl &= ~E1000_CTRL_FD; 1817 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1818 DEBUGOUT("Half Duplex\n"); 1819 } else { 1820 ctrl |= E1000_CTRL_FD; 1821 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1822 DEBUGOUT("Full Duplex\n"); 1823 } 1824 1825 /* Forcing 10mb or 100mb? */ 1826 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1827 ctrl |= E1000_CTRL_SPD_100; 1828 *phy_ctrl |= MII_CR_SPEED_100; 1829 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1830 DEBUGOUT("Forcing 100mb\n"); 1831 } else { 1832 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1833 *phy_ctrl |= MII_CR_SPEED_10; 1834 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1835 DEBUGOUT("Forcing 10mb\n"); 1836 } 1837 1838 e1000_config_collision_dist_generic(hw); 1839 1840 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1841} 1842 1843/** 1844 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1845 * @hw: pointer to the HW structure 1846 * @active: boolean used to enable/disable lplu 1847 * 1848 * Success returns 0, Failure returns 1 1849 * 1850 * The low power link up (lplu) state is set to the power management level D3 1851 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1852 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1853 * is used during Dx states where the power conservation is most important. 1854 * During driver activity, SmartSpeed should be enabled so performance is 1855 * maintained. 1856 **/ 1857s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1858{ 1859 struct e1000_phy_info *phy = &hw->phy; 1860 s32 ret_val = E1000_SUCCESS; 1861 u16 data; 1862 1863 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1864 1865 if (!(hw->phy.ops.read_reg)) 1866 goto out; 1867 1868 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1869 if (ret_val) 1870 goto out; 1871 1872 if (!active) { 1873 data &= ~IGP02E1000_PM_D3_LPLU; 1874 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1875 data); 1876 if (ret_val) 1877 goto out; 1878 /* 1879 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1880 * during Dx states where the power conservation is most 1881 * important. During driver activity we should enable 1882 * SmartSpeed, so performance is maintained. 1883 */ 1884 if (phy->smart_speed == e1000_smart_speed_on) { 1885 ret_val = phy->ops.read_reg(hw, 1886 IGP01E1000_PHY_PORT_CONFIG, 1887 &data); 1888 if (ret_val) 1889 goto out; 1890 1891 data |= IGP01E1000_PSCFR_SMART_SPEED; 1892 ret_val = phy->ops.write_reg(hw, 1893 IGP01E1000_PHY_PORT_CONFIG, 1894 data); 1895 if (ret_val) 1896 goto out; 1897 } else if (phy->smart_speed == e1000_smart_speed_off) { 1898 ret_val = phy->ops.read_reg(hw, 1899 IGP01E1000_PHY_PORT_CONFIG, 1900 &data); 1901 if (ret_val) 1902 goto out; 1903 1904 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1905 ret_val = phy->ops.write_reg(hw, 1906 IGP01E1000_PHY_PORT_CONFIG, 1907 data); 1908 if (ret_val) 1909 goto out; 1910 } 1911 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1912 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1913 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1914 data |= IGP02E1000_PM_D3_LPLU; 1915 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1916 data); 1917 if (ret_val) 1918 goto out; 1919 1920 /* When LPLU is enabled, we should disable SmartSpeed */ 1921 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1922 &data); 1923 if (ret_val) 1924 goto out; 1925 1926 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1927 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1928 data); 1929 } 1930 1931out: 1932 return ret_val; 1933} 1934 1935/** 1936 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1937 * @hw: pointer to the HW structure 1938 * 1939 * Success returns 0, Failure returns 1 1940 * 1941 * A downshift is detected by querying the PHY link health. 1942 **/ 1943s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1944{ 1945 struct e1000_phy_info *phy = &hw->phy; 1946 s32 ret_val; 1947 u16 phy_data, offset, mask; 1948 1949 DEBUGFUNC("e1000_check_downshift_generic"); 1950 1951 switch (phy->type) { 1952 case e1000_phy_m88: 1953 case e1000_phy_gg82563: 1954 case e1000_phy_bm: 1955 case e1000_phy_82578: 1956 offset = M88E1000_PHY_SPEC_STATUS; 1957 mask = M88E1000_PSSR_DOWNSHIFT; 1958 break; 1959 case e1000_phy_igp: 1960 case e1000_phy_igp_2: 1961 case e1000_phy_igp_3: 1962 offset = IGP01E1000_PHY_LINK_HEALTH; 1963 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1964 break; 1965 default: 1966 /* speed downshift not supported */ 1967 phy->speed_downgraded = FALSE; 1968 ret_val = E1000_SUCCESS; 1969 goto out; 1970 } 1971 1972 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1973 1974 if (!ret_val) 1975 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1976 1977out: 1978 return ret_val; 1979} 1980 1981/** 1982 * e1000_check_polarity_m88 - Checks the polarity. 1983 * @hw: pointer to the HW structure 1984 * 1985 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1986 * 1987 * Polarity is determined based on the PHY specific status register. 1988 **/ 1989s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1990{ 1991 struct e1000_phy_info *phy = &hw->phy; 1992 s32 ret_val; 1993 u16 data; 1994 1995 DEBUGFUNC("e1000_check_polarity_m88"); 1996 1997 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1998 1999 if (!ret_val) 2000 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 2001 ? e1000_rev_polarity_reversed 2002 : e1000_rev_polarity_normal; 2003 2004 return ret_val; 2005} 2006 2007/** 2008 * e1000_check_polarity_igp - Checks the polarity. 2009 * @hw: pointer to the HW structure 2010 * 2011 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2012 * 2013 * Polarity is determined based on the PHY port status register, and the 2014 * current speed (since there is no polarity at 100Mbps). 2015 **/ 2016s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2017{ 2018 struct e1000_phy_info *phy = &hw->phy; 2019 s32 ret_val; 2020 u16 data, offset, mask; 2021 2022 DEBUGFUNC("e1000_check_polarity_igp"); 2023 2024 /* 2025 * Polarity is determined based on the speed of 2026 * our connection. 2027 */ 2028 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2029 if (ret_val) 2030 goto out; 2031 2032 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2033 IGP01E1000_PSSR_SPEED_1000MBPS) { 2034 offset = IGP01E1000_PHY_PCS_INIT_REG; 2035 mask = IGP01E1000_PHY_POLARITY_MASK; 2036 } else { 2037 /* 2038 * This really only applies to 10Mbps since 2039 * there is no polarity for 100Mbps (always 0). 2040 */ 2041 offset = IGP01E1000_PHY_PORT_STATUS; 2042 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2043 } 2044 2045 ret_val = phy->ops.read_reg(hw, offset, &data); 2046 2047 if (!ret_val) 2048 phy->cable_polarity = (data & mask) 2049 ? e1000_rev_polarity_reversed 2050 : e1000_rev_polarity_normal; 2051 2052out: 2053 return ret_val; 2054} 2055 2056/** 2057 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2058 * @hw: pointer to the HW structure 2059 * 2060 * Polarity is determined on the polarity reversal feature being enabled. 2061 **/ 2062s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2063{ 2064 struct e1000_phy_info *phy = &hw->phy; 2065 s32 ret_val; 2066 u16 phy_data, offset, mask; 2067 2068 DEBUGFUNC("e1000_check_polarity_ife"); 2069 2070 /* 2071 * Polarity is determined based on the reversal feature being enabled. 2072 */ 2073 if (phy->polarity_correction) { 2074 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2075 mask = IFE_PESC_POLARITY_REVERSED; 2076 } else { 2077 offset = IFE_PHY_SPECIAL_CONTROL; 2078 mask = IFE_PSC_FORCE_POLARITY; 2079 } 2080 2081 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2082 2083 if (!ret_val) 2084 phy->cable_polarity = (phy_data & mask) 2085 ? e1000_rev_polarity_reversed 2086 : e1000_rev_polarity_normal; 2087 2088 return ret_val; 2089} 2090 2091/** 2092 * e1000_wait_autoneg_generic - Wait for auto-neg completion 2093 * @hw: pointer to the HW structure 2094 * 2095 * Waits for auto-negotiation to complete or for the auto-negotiation time 2096 * limit to expire, which ever happens first. 2097 **/ 2098s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 2099{ 2100 s32 ret_val = E1000_SUCCESS; 2101 u16 i, phy_status; 2102 2103 DEBUGFUNC("e1000_wait_autoneg_generic"); 2104 2105 if (!(hw->phy.ops.read_reg)) 2106 return E1000_SUCCESS; 2107 2108 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2109 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2110 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2111 if (ret_val) 2112 break; 2113 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2114 if (ret_val) 2115 break; 2116 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2117 break; 2118 msec_delay(100); 2119 } 2120 2121 /* 2122 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2123 * has completed. 2124 */ 2125 return ret_val; 2126} 2127 2128/** 2129 * e1000_phy_has_link_generic - Polls PHY for link 2130 * @hw: pointer to the HW structure 2131 * @iterations: number of times to poll for link 2132 * @usec_interval: delay between polling attempts 2133 * @success: pointer to whether polling was successful or not 2134 * 2135 * Polls the PHY status register for link, 'iterations' number of times. 2136 **/ 2137s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2138 u32 usec_interval, bool *success) 2139{ 2140 s32 ret_val = E1000_SUCCESS; 2141 u16 i, phy_status; 2142 2143 DEBUGFUNC("e1000_phy_has_link_generic"); 2144 2145 if (!(hw->phy.ops.read_reg)) 2146 return E1000_SUCCESS; 2147 2148 for (i = 0; i < iterations; i++) { 2149 /* 2150 * Some PHYs require the PHY_STATUS register to be read 2151 * twice due to the link bit being sticky. No harm doing 2152 * it across the board. 2153 */ 2154 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2155 if (ret_val) 2156 /* 2157 * If the first read fails, another entity may have 2158 * ownership of the resources, wait and try again to 2159 * see if they have relinquished the resources yet. 2160 */ 2161 usec_delay(usec_interval); 2162 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2163 if (ret_val) 2164 break; 2165 if (phy_status & MII_SR_LINK_STATUS) 2166 break; 2167 if (usec_interval >= 1000) 2168 msec_delay_irq(usec_interval/1000); 2169 else 2170 usec_delay(usec_interval); 2171 } 2172 2173 *success = (i < iterations) ? TRUE : FALSE; 2174 2175 return ret_val; 2176} 2177 2178/** 2179 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2180 * @hw: pointer to the HW structure 2181 * 2182 * Reads the PHY specific status register to retrieve the cable length 2183 * information. The cable length is determined by averaging the minimum and 2184 * maximum values to get the "average" cable length. The m88 PHY has four 2185 * possible cable length values, which are: 2186 * Register Value Cable Length 2187 * 0 < 50 meters 2188 * 1 50 - 80 meters 2189 * 2 80 - 110 meters 2190 * 3 110 - 140 meters 2191 * 4 > 140 meters 2192 **/ 2193s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2194{ 2195 struct e1000_phy_info *phy = &hw->phy; 2196 s32 ret_val; 2197 u16 phy_data, index; 2198 2199 DEBUGFUNC("e1000_get_cable_length_m88"); 2200 2201 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2202 if (ret_val) 2203 goto out; 2204 2205 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2206 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2207 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2208 ret_val = -E1000_ERR_PHY; 2209 goto out; 2210 } 2211 2212 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2213 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2214 2215 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2216 2217out: 2218 return ret_val; 2219} 2220 2221s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2222{ 2223 struct e1000_phy_info *phy = &hw->phy; 2224 s32 ret_val; 2225 u16 phy_data, phy_data2, index, default_page, is_cm; 2226 2227 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2228 2229 switch (hw->phy.id) { 2230 case M88E1340M_E_PHY_ID: 2231 case I347AT4_E_PHY_ID: 2232 /* Remember the original page select and set it to 7 */ 2233 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2234 &default_page); 2235 if (ret_val) 2236 goto out; 2237 2238 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2239 if (ret_val) 2240 goto out; 2241 2242 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2243 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2244 &phy_data); 2245 if (ret_val) 2246 goto out; 2247 2248 /* Check if the unit of cable length is meters or cm */ 2249 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2250 if (ret_val) 2251 goto out; 2252 2253 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2254 2255 /* Populate the phy structure with cable length in meters */ 2256 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2257 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2258 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2259 2260 /* Reset the page selec to its original value */ 2261 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2262 default_page); 2263 if (ret_val) 2264 goto out; 2265 break; 2266 case M88E1112_E_PHY_ID: 2267 /* Remember the original page select and set it to 5 */ 2268 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2269 &default_page); 2270 if (ret_val) 2271 goto out; 2272 2273 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2274 if (ret_val) 2275 goto out; 2276 2277 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2278 &phy_data); 2279 if (ret_val) 2280 goto out; 2281 2282 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2283 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2284 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2285 ret_val = -E1000_ERR_PHY; 2286 goto out; 2287 } 2288 2289 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2290 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2291 2292 phy->cable_length = (phy->min_cable_length + 2293 phy->max_cable_length) / 2; 2294 2295 /* Reset the page select to its original value */ 2296 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2297 default_page); 2298 if (ret_val) 2299 goto out; 2300 2301 break; 2302 default: 2303 ret_val = -E1000_ERR_PHY; 2304 goto out; 2305 } 2306 2307out: 2308 return ret_val; 2309} 2310 2311/** 2312 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2313 * @hw: pointer to the HW structure 2314 * 2315 * The automatic gain control (agc) normalizes the amplitude of the 2316 * received signal, adjusting for the attenuation produced by the 2317 * cable. By reading the AGC registers, which represent the 2318 * combination of coarse and fine gain value, the value can be put 2319 * into a lookup table to obtain the approximate cable length 2320 * for each channel. 2321 **/ 2322s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2323{ 2324 struct e1000_phy_info *phy = &hw->phy; 2325 s32 ret_val = E1000_SUCCESS; 2326 u16 phy_data, i, agc_value = 0; 2327 u16 cur_agc_index, max_agc_index = 0; 2328 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2329 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2330 IGP02E1000_PHY_AGC_A, 2331 IGP02E1000_PHY_AGC_B, 2332 IGP02E1000_PHY_AGC_C, 2333 IGP02E1000_PHY_AGC_D 2334 }; 2335 2336 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2337 2338 /* Read the AGC registers for all channels */ 2339 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2340 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2341 if (ret_val) 2342 goto out; 2343 2344 /* 2345 * Getting bits 15:9, which represent the combination of 2346 * coarse and fine gain values. The result is a number 2347 * that can be put into the lookup table to obtain the 2348 * approximate cable length. 2349 */ 2350 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2351 IGP02E1000_AGC_LENGTH_MASK; 2352 2353 /* Array index bound check. */ 2354 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2355 (cur_agc_index == 0)) { 2356 ret_val = -E1000_ERR_PHY; 2357 goto out; 2358 } 2359 2360 /* Remove min & max AGC values from calculation. */ 2361 if (e1000_igp_2_cable_length_table[min_agc_index] > 2362 e1000_igp_2_cable_length_table[cur_agc_index]) 2363 min_agc_index = cur_agc_index; 2364 if (e1000_igp_2_cable_length_table[max_agc_index] < 2365 e1000_igp_2_cable_length_table[cur_agc_index]) 2366 max_agc_index = cur_agc_index; 2367 2368 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2369 } 2370 2371 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2372 e1000_igp_2_cable_length_table[max_agc_index]); 2373 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2374 2375 /* Calculate cable length with the error range of +/- 10 meters. */ 2376 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2377 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2378 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2379 2380 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2381 2382out: 2383 return ret_val; 2384} 2385 2386/** 2387 * e1000_get_phy_info_m88 - Retrieve PHY information 2388 * @hw: pointer to the HW structure 2389 * 2390 * Valid for only copper links. Read the PHY status register (sticky read) 2391 * to verify that link is up. Read the PHY special control register to 2392 * determine the polarity and 10base-T extended distance. Read the PHY 2393 * special status register to determine MDI/MDIx and current speed. If 2394 * speed is 1000, then determine cable length, local and remote receiver. 2395 **/ 2396s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2397{ 2398 struct e1000_phy_info *phy = &hw->phy; 2399 s32 ret_val; 2400 u16 phy_data; 2401 bool link; 2402 2403 DEBUGFUNC("e1000_get_phy_info_m88"); 2404 2405 if (phy->media_type != e1000_media_type_copper) { 2406 DEBUGOUT("Phy info is only valid for copper media\n"); 2407 ret_val = -E1000_ERR_CONFIG; 2408 goto out; 2409 } 2410 2411 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2412 if (ret_val) 2413 goto out; 2414 2415 if (!link) { 2416 DEBUGOUT("Phy info is only valid if link is up\n"); 2417 ret_val = -E1000_ERR_CONFIG; 2418 goto out; 2419 } 2420 2421 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2422 if (ret_val) 2423 goto out; 2424 2425 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2426 ? TRUE : FALSE; 2427 2428 ret_val = e1000_check_polarity_m88(hw); 2429 if (ret_val) 2430 goto out; 2431 2432 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2433 if (ret_val) 2434 goto out; 2435 2436 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 2437 2438 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2439 ret_val = hw->phy.ops.get_cable_length(hw); 2440 if (ret_val) 2441 goto out; 2442 2443 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2444 if (ret_val) 2445 goto out; 2446 2447 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2448 ? e1000_1000t_rx_status_ok 2449 : e1000_1000t_rx_status_not_ok; 2450 2451 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2452 ? e1000_1000t_rx_status_ok 2453 : e1000_1000t_rx_status_not_ok; 2454 } else { 2455 /* Set values to "undefined" */ 2456 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2457 phy->local_rx = e1000_1000t_rx_status_undefined; 2458 phy->remote_rx = e1000_1000t_rx_status_undefined; 2459 } 2460 2461out: 2462 return ret_val; 2463} 2464 2465/** 2466 * e1000_get_phy_info_igp - Retrieve igp PHY information 2467 * @hw: pointer to the HW structure 2468 * 2469 * Read PHY status to determine if link is up. If link is up, then 2470 * set/determine 10base-T extended distance and polarity correction. Read 2471 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2472 * determine on the cable length, local and remote receiver. 2473 **/ 2474s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2475{ 2476 struct e1000_phy_info *phy = &hw->phy; 2477 s32 ret_val; 2478 u16 data; 2479 bool link; 2480 2481 DEBUGFUNC("e1000_get_phy_info_igp"); 2482 2483 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2484 if (ret_val) 2485 goto out; 2486 2487 if (!link) { 2488 DEBUGOUT("Phy info is only valid if link is up\n"); 2489 ret_val = -E1000_ERR_CONFIG; 2490 goto out; 2491 } 2492 2493 phy->polarity_correction = TRUE; 2494 2495 ret_val = e1000_check_polarity_igp(hw); 2496 if (ret_val) 2497 goto out; 2498 2499 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2500 if (ret_val) 2501 goto out; 2502 2503 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 2504 2505 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2506 IGP01E1000_PSSR_SPEED_1000MBPS) { 2507 ret_val = phy->ops.get_cable_length(hw); 2508 if (ret_val) 2509 goto out; 2510 2511 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2512 if (ret_val) 2513 goto out; 2514 2515 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2516 ? e1000_1000t_rx_status_ok 2517 : e1000_1000t_rx_status_not_ok; 2518 2519 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2520 ? e1000_1000t_rx_status_ok 2521 : e1000_1000t_rx_status_not_ok; 2522 } else { 2523 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2524 phy->local_rx = e1000_1000t_rx_status_undefined; 2525 phy->remote_rx = e1000_1000t_rx_status_undefined; 2526 } 2527 2528out: 2529 return ret_val; 2530} 2531 2532/** 2533 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2534 * @hw: pointer to the HW structure 2535 * 2536 * Populates "phy" structure with various feature states. 2537 **/ 2538s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2539{ 2540 struct e1000_phy_info *phy = &hw->phy; 2541 s32 ret_val; 2542 u16 data; 2543 bool link; 2544 2545 DEBUGFUNC("e1000_get_phy_info_ife"); 2546 2547 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2548 if (ret_val) 2549 goto out; 2550 2551 if (!link) { 2552 DEBUGOUT("Phy info is only valid if link is up\n"); 2553 ret_val = -E1000_ERR_CONFIG; 2554 goto out; 2555 } 2556 2557 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2558 if (ret_val) 2559 goto out; 2560 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2561 ? FALSE : TRUE; 2562 2563 if (phy->polarity_correction) { 2564 ret_val = e1000_check_polarity_ife(hw); 2565 if (ret_val) 2566 goto out; 2567 } else { 2568 /* Polarity is forced */ 2569 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2570 ? e1000_rev_polarity_reversed 2571 : e1000_rev_polarity_normal; 2572 } 2573 2574 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2575 if (ret_val) 2576 goto out; 2577 2578 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 2579 2580 /* The following parameters are undefined for 10/100 operation. */ 2581 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2582 phy->local_rx = e1000_1000t_rx_status_undefined; 2583 phy->remote_rx = e1000_1000t_rx_status_undefined; 2584 2585out: 2586 return ret_val; 2587} 2588 2589/** 2590 * e1000_phy_sw_reset_generic - PHY software reset 2591 * @hw: pointer to the HW structure 2592 * 2593 * Does a software reset of the PHY by reading the PHY control register and 2594 * setting/write the control register reset bit to the PHY. 2595 **/ 2596s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2597{ 2598 s32 ret_val = E1000_SUCCESS; 2599 u16 phy_ctrl; 2600 2601 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2602 2603 if (!(hw->phy.ops.read_reg)) 2604 goto out; 2605 2606 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2607 if (ret_val) 2608 goto out; 2609 2610 phy_ctrl |= MII_CR_RESET; 2611 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2612 if (ret_val) 2613 goto out; 2614 2615 usec_delay(1); 2616 2617out: 2618 return ret_val; 2619} 2620 2621/** 2622 * e1000_phy_hw_reset_generic - PHY hardware reset 2623 * @hw: pointer to the HW structure 2624 * 2625 * Verify the reset block is not blocking us from resetting. Acquire 2626 * semaphore (if necessary) and read/set/write the device control reset 2627 * bit in the PHY. Wait the appropriate delay time for the device to 2628 * reset and release the semaphore (if necessary). 2629 **/ 2630s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2631{ 2632 struct e1000_phy_info *phy = &hw->phy; 2633 s32 ret_val = E1000_SUCCESS; 2634 u32 ctrl; 2635 2636 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2637 2638 ret_val = phy->ops.check_reset_block(hw); 2639 if (ret_val) { 2640 ret_val = E1000_SUCCESS; 2641 goto out; 2642 } 2643 2644 ret_val = phy->ops.acquire(hw); 2645 if (ret_val) 2646 goto out; 2647 2648 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2649 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2650 E1000_WRITE_FLUSH(hw); 2651 2652 usec_delay(phy->reset_delay_us); 2653 2654 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2655 E1000_WRITE_FLUSH(hw); 2656 2657 usec_delay(150); 2658 2659 phy->ops.release(hw); 2660 2661 ret_val = phy->ops.get_cfg_done(hw); 2662 2663out: 2664 return ret_val; 2665} 2666 2667/** 2668 * e1000_get_cfg_done_generic - Generic configuration done 2669 * @hw: pointer to the HW structure 2670 * 2671 * Generic function to wait 10 milli-seconds for configuration to complete 2672 * and return success. 2673 **/ 2674s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2675{ 2676 DEBUGFUNC("e1000_get_cfg_done_generic"); 2677 2678 msec_delay_irq(10); 2679 2680 return E1000_SUCCESS; 2681} 2682 2683/** 2684 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2685 * @hw: pointer to the HW structure 2686 * 2687 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2688 **/ 2689s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2690{ 2691 DEBUGOUT("Running IGP 3 PHY init script\n"); 2692 2693 /* PHY init IGP 3 */ 2694 /* Enable rise/fall, 10-mode work in class-A */ 2695 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2696 /* Remove all caps from Replica path filter */ 2697 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2698 /* Bias trimming for ADC, AFE and Driver (Default) */ 2699 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2700 /* Increase Hybrid poly bias */ 2701 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2702 /* Add 4% to Tx amplitude in Gig mode */ 2703 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2704 /* Disable trimming (TTT) */ 2705 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2706 /* Poly DC correction to 94.6% + 2% for all channels */ 2707 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2708 /* ABS DC correction to 95.9% */ 2709 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2710 /* BG temp curve trim */ 2711 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2712 /* Increasing ADC OPAMP stage 1 currents to max */ 2713 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2714 /* Force 1000 ( required for enabling PHY regs configuration) */ 2715 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2716 /* Set upd_freq to 6 */ 2717 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2718 /* Disable NPDFE */ 2719 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2720 /* Disable adaptive fixed FFE (Default) */ 2721 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2722 /* Enable FFE hysteresis */ 2723 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2724 /* Fixed FFE for short cable lengths */ 2725 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2726 /* Fixed FFE for medium cable lengths */ 2727 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2728 /* Fixed FFE for long cable lengths */ 2729 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2730 /* Enable Adaptive Clip Threshold */ 2731 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2732 /* AHT reset limit to 1 */ 2733 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2734 /* Set AHT master delay to 127 msec */ 2735 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2736 /* Set scan bits for AHT */ 2737 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2738 /* Set AHT Preset bits */ 2739 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2740 /* Change integ_factor of channel A to 3 */ 2741 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2742 /* Change prop_factor of channels BCD to 8 */ 2743 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2744 /* Change cg_icount + enable integbp for channels BCD */ 2745 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2746 /* 2747 * Change cg_icount + enable integbp + change prop_factor_master 2748 * to 8 for channel A 2749 */ 2750 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2751 /* Disable AHT in Slave mode on channel A */ 2752 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2753 /* 2754 * Enable LPLU and disable AN to 1000 in non-D0a states, 2755 * Enable SPD+B2B 2756 */ 2757 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2758 /* Enable restart AN on an1000_dis change */ 2759 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2760 /* Enable wh_fifo read clock in 10/100 modes */ 2761 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2762 /* Restart AN, Speed selection is 1000 */ 2763 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2764 2765 return E1000_SUCCESS; 2766} 2767 2768/** 2769 * e1000_get_phy_type_from_id - Get PHY type from id 2770 * @phy_id: phy_id read from the phy 2771 * 2772 * Returns the phy type from the id. 2773 **/ 2774enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2775{ 2776 enum e1000_phy_type phy_type = e1000_phy_unknown; 2777 2778 switch (phy_id) { 2779 case M88E1000_I_PHY_ID: 2780 case M88E1000_E_PHY_ID: 2781 case M88E1111_I_PHY_ID: 2782 case M88E1011_I_PHY_ID: 2783 case I347AT4_E_PHY_ID: 2784 case M88E1112_E_PHY_ID: 2785 case M88E1340M_E_PHY_ID: 2786 phy_type = e1000_phy_m88; 2787 break; 2788 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2789 phy_type = e1000_phy_igp_2; 2790 break; 2791 case GG82563_E_PHY_ID: 2792 phy_type = e1000_phy_gg82563; 2793 break; 2794 case IGP03E1000_E_PHY_ID: 2795 phy_type = e1000_phy_igp_3; 2796 break; 2797 case IFE_E_PHY_ID: 2798 case IFE_PLUS_E_PHY_ID: 2799 case IFE_C_E_PHY_ID: 2800 phy_type = e1000_phy_ife; 2801 break; 2802 case BME1000_E_PHY_ID: 2803 case BME1000_E_PHY_ID_R2: 2804 phy_type = e1000_phy_bm; 2805 break; 2806 case I82578_E_PHY_ID: 2807 phy_type = e1000_phy_82578; 2808 break; 2809 case I82577_E_PHY_ID: 2810 phy_type = e1000_phy_82577; 2811 break; 2812 case I82579_E_PHY_ID: 2813 phy_type = e1000_phy_82579; 2814 break; 2815 case I82580_I_PHY_ID: 2816 phy_type = e1000_phy_82580; 2817 break; 2818 default: 2819 phy_type = e1000_phy_unknown; 2820 break; 2821 } 2822 return phy_type; 2823} 2824 2825/** 2826 * e1000_determine_phy_address - Determines PHY address. 2827 * @hw: pointer to the HW structure 2828 * 2829 * This uses a trial and error method to loop through possible PHY 2830 * addresses. It tests each by reading the PHY ID registers and 2831 * checking for a match. 2832 **/ 2833s32 e1000_determine_phy_address(struct e1000_hw *hw) 2834{ 2835 s32 ret_val = -E1000_ERR_PHY_TYPE; 2836 u32 phy_addr = 0; 2837 u32 i; 2838 enum e1000_phy_type phy_type = e1000_phy_unknown; 2839 2840 hw->phy.id = phy_type; 2841 2842 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2843 hw->phy.addr = phy_addr; 2844 i = 0; 2845 2846 do { 2847 e1000_get_phy_id(hw); 2848 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2849 2850 /* 2851 * If phy_type is valid, break - we found our 2852 * PHY address 2853 */ 2854 if (phy_type != e1000_phy_unknown) { 2855 ret_val = E1000_SUCCESS; 2856 goto out; 2857 } 2858 msec_delay(1); 2859 i++; 2860 } while (i < 10); 2861 } 2862 2863out: 2864 return ret_val; 2865} 2866 2867/** 2868 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2869 * @page: page to access 2870 * 2871 * Returns the phy address for the page requested. 2872 **/ 2873static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2874{ 2875 u32 phy_addr = 2; 2876 2877 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2878 phy_addr = 1; 2879 2880 return phy_addr; 2881} 2882 2883/** 2884 * e1000_write_phy_reg_bm - Write BM PHY register 2885 * @hw: pointer to the HW structure 2886 * @offset: register offset to write to 2887 * @data: data to write at register offset 2888 * 2889 * Acquires semaphore, if necessary, then writes the data to PHY register 2890 * at the offset. Release any acquired semaphores before exiting. 2891 **/ 2892s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2893{ 2894 s32 ret_val; 2895 u32 page = offset >> IGP_PAGE_SHIFT; 2896 2897 DEBUGFUNC("e1000_write_phy_reg_bm"); 2898 2899 ret_val = hw->phy.ops.acquire(hw); 2900 if (ret_val) 2901 return ret_val; 2902 2903 /* Page 800 works differently than the rest so it has its own func */ 2904 if (page == BM_WUC_PAGE) { 2905 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2906 FALSE); 2907 goto out; 2908 } 2909 2910 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2911 2912 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2913 u32 page_shift, page_select; 2914 2915 /* 2916 * Page select is register 31 for phy address 1 and 22 for 2917 * phy address 2 and 3. Page select is shifted only for 2918 * phy address 1. 2919 */ 2920 if (hw->phy.addr == 1) { 2921 page_shift = IGP_PAGE_SHIFT; 2922 page_select = IGP01E1000_PHY_PAGE_SELECT; 2923 } else { 2924 page_shift = 0; 2925 page_select = BM_PHY_PAGE_SELECT; 2926 } 2927 2928 /* Page is shifted left, PHY expects (page x 32) */ 2929 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2930 (page << page_shift)); 2931 if (ret_val) 2932 goto out; 2933 } 2934 2935 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2936 data); 2937 2938out: 2939 hw->phy.ops.release(hw); 2940 return ret_val; 2941} 2942 2943/** 2944 * e1000_read_phy_reg_bm - Read BM PHY register 2945 * @hw: pointer to the HW structure 2946 * @offset: register offset to be read 2947 * @data: pointer to the read data 2948 * 2949 * Acquires semaphore, if necessary, then reads the PHY register at offset 2950 * and storing the retrieved information in data. Release any acquired 2951 * semaphores before exiting. 2952 **/ 2953s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2954{ 2955 s32 ret_val; 2956 u32 page = offset >> IGP_PAGE_SHIFT; 2957 2958 DEBUGFUNC("e1000_read_phy_reg_bm"); 2959 2960 ret_val = hw->phy.ops.acquire(hw); 2961 if (ret_val) 2962 return ret_val; 2963 2964 /* Page 800 works differently than the rest so it has its own func */ 2965 if (page == BM_WUC_PAGE) { 2966 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2967 TRUE); 2968 goto out; 2969 } 2970 2971 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2972 2973 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2974 u32 page_shift, page_select; 2975 2976 /* 2977 * Page select is register 31 for phy address 1 and 22 for 2978 * phy address 2 and 3. Page select is shifted only for 2979 * phy address 1. 2980 */ 2981 if (hw->phy.addr == 1) { 2982 page_shift = IGP_PAGE_SHIFT; 2983 page_select = IGP01E1000_PHY_PAGE_SELECT; 2984 } else { 2985 page_shift = 0; 2986 page_select = BM_PHY_PAGE_SELECT; 2987 } 2988 2989 /* Page is shifted left, PHY expects (page x 32) */ 2990 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2991 (page << page_shift)); 2992 if (ret_val) 2993 goto out; 2994 } 2995 2996 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2997 data); 2998out: 2999 hw->phy.ops.release(hw); 3000 return ret_val; 3001} 3002 3003/** 3004 * e1000_read_phy_reg_bm2 - Read BM PHY register 3005 * @hw: pointer to the HW structure 3006 * @offset: register offset to be read 3007 * @data: pointer to the read data 3008 * 3009 * Acquires semaphore, if necessary, then reads the PHY register at offset 3010 * and storing the retrieved information in data. Release any acquired 3011 * semaphores before exiting. 3012 **/ 3013s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3014{ 3015 s32 ret_val; 3016 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3017 3018 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3019 3020 ret_val = hw->phy.ops.acquire(hw); 3021 if (ret_val) 3022 return ret_val; 3023 3024 /* Page 800 works differently than the rest so it has its own func */ 3025 if (page == BM_WUC_PAGE) { 3026 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3027 TRUE); 3028 goto out; 3029 } 3030 3031 hw->phy.addr = 1; 3032 3033 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3034 3035 /* Page is shifted left, PHY expects (page x 32) */ 3036 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3037 page); 3038 3039 if (ret_val) 3040 goto out; 3041 } 3042 3043 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3044 data); 3045out: 3046 hw->phy.ops.release(hw); 3047 return ret_val; 3048} 3049 3050/** 3051 * e1000_write_phy_reg_bm2 - Write BM PHY register 3052 * @hw: pointer to the HW structure 3053 * @offset: register offset to write to 3054 * @data: data to write at register offset 3055 * 3056 * Acquires semaphore, if necessary, then writes the data to PHY register 3057 * at the offset. Release any acquired semaphores before exiting. 3058 **/ 3059s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3060{ 3061 s32 ret_val; 3062 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3063 3064 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3065 3066 ret_val = hw->phy.ops.acquire(hw); 3067 if (ret_val) 3068 return ret_val; 3069 3070 /* Page 800 works differently than the rest so it has its own func */ 3071 if (page == BM_WUC_PAGE) { 3072 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3073 FALSE); 3074 goto out; 3075 } 3076 3077 hw->phy.addr = 1; 3078 3079 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3080 /* Page is shifted left, PHY expects (page x 32) */ 3081 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3082 page); 3083 3084 if (ret_val) 3085 goto out; 3086 } 3087 3088 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3089 data); 3090 3091out: 3092 hw->phy.ops.release(hw); 3093 return ret_val; 3094} 3095 3096/** 3097 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 3098 * @hw: pointer to the HW structure 3099 * @offset: register offset to be read or written 3100 * @data: pointer to the data to read or write 3101 * @read: determines if operation is read or write 3102 * 3103 * Acquires semaphore, if necessary, then reads the PHY register at offset 3104 * and storing the retrieved information in data. Release any acquired 3105 * semaphores before exiting. Note that procedure to read the wakeup 3106 * registers are different. It works as such: 3107 * 1) Set page 769, register 17, bit 2 = 1 3108 * 2) Set page to 800 for host (801 if we were manageability) 3109 * 3) Write the address using the address opcode (0x11) 3110 * 4) Read or write the data using the data opcode (0x12) 3111 * 5) Restore 769_17.2 to its original value 3112 * 3113 * Assumes semaphore already acquired. 3114 **/ 3115static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3116 u16 *data, bool read) 3117{ 3118 s32 ret_val; 3119 u16 reg = BM_PHY_REG_NUM(offset); 3120 u16 phy_reg = 0; 3121 3122 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3123 3124 /* Gig must be disabled for MDIO accesses to page 800 */ 3125 if ((hw->mac.type == e1000_pchlan) && 3126 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3127 DEBUGOUT("Attempting to access page 800 while gig enabled.\n"); 3128 3129 /* All operations in this function are phy address 1 */ 3130 hw->phy.addr = 1; 3131 3132 /* Set page 769 */ 3133 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3134 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3135 3136 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 3137 if (ret_val) { 3138 DEBUGOUT("Could not read PHY page 769\n"); 3139 goto out; 3140 } 3141 3142 /* First clear bit 4 to avoid a power state change */ 3143 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 3144 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3145 if (ret_val) { 3146 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 3147 goto out; 3148 } 3149 3150 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 3151 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 3152 phy_reg | BM_WUC_ENABLE_BIT); 3153 if (ret_val) { 3154 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 3155 goto out; 3156 } 3157 3158 /* Select page 800 */ 3159 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3160 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3161 3162 /* Write the page 800 offset value using opcode 0x11 */ 3163 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3164 if (ret_val) { 3165 DEBUGOUT("Could not write address opcode to page 800\n"); 3166 goto out; 3167 } 3168 3169 if (read) { 3170 /* Read the page 800 value using opcode 0x12 */ 3171 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3172 data); 3173 } else { 3174 /* Write the page 800 value using opcode 0x12 */ 3175 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3176 *data); 3177 } 3178 3179 if (ret_val) { 3180 DEBUGOUT("Could not access data value from page 800\n"); 3181 goto out; 3182 } 3183 3184 /* 3185 * Restore 769_17.2 to its original value 3186 * Set page 769 3187 */ 3188 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3189 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3190 3191 /* Clear 769_17.2 */ 3192 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3193 if (ret_val) { 3194 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 3195 goto out; 3196 } 3197 3198out: 3199 return ret_val; 3200} 3201 3202/** 3203 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3204 * @hw: pointer to the HW structure 3205 * 3206 * In the case of a PHY power down to save power, or to turn off link during a 3207 * driver unload, or wake on lan is not enabled, restore the link to previous 3208 * settings. 3209 **/ 3210void e1000_power_up_phy_copper(struct e1000_hw *hw) 3211{ 3212 u16 mii_reg = 0; 3213 3214 /* The PHY will retain its settings across a power down/up cycle */ 3215 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3216 mii_reg &= ~MII_CR_POWER_DOWN; 3217 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3218} 3219 3220/** 3221 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3222 * @hw: pointer to the HW structure 3223 * 3224 * In the case of a PHY power down to save power, or to turn off link during a 3225 * driver unload, or wake on lan is not enabled, restore the link to previous 3226 * settings. 3227 **/ 3228void e1000_power_down_phy_copper(struct e1000_hw *hw) 3229{ 3230 u16 mii_reg = 0; 3231 3232 /* The PHY will retain its settings across a power down/up cycle */ 3233 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3234 mii_reg |= MII_CR_POWER_DOWN; 3235 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3236 msec_delay(1); 3237} 3238 3239/** 3240 * __e1000_read_phy_reg_hv - Read HV PHY register 3241 * @hw: pointer to the HW structure 3242 * @offset: register offset to be read 3243 * @data: pointer to the read data 3244 * @locked: semaphore has already been acquired or not 3245 * 3246 * Acquires semaphore, if necessary, then reads the PHY register at offset 3247 * and stores the retrieved information in data. Release any acquired 3248 * semaphore before exiting. 3249 **/ 3250static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3251 bool locked) 3252{ 3253 s32 ret_val; 3254 u16 page = BM_PHY_REG_PAGE(offset); 3255 u16 reg = BM_PHY_REG_NUM(offset); 3256 3257 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3258 3259 if (!locked) { 3260 ret_val = hw->phy.ops.acquire(hw); 3261 if (ret_val) 3262 return ret_val; 3263 } 3264 3265 /* Page 800 works differently than the rest so it has its own func */ 3266 if (page == BM_WUC_PAGE) { 3267 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3268 data, TRUE); 3269 goto out; 3270 } 3271 3272 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3273 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3274 data, TRUE); 3275 goto out; 3276 } 3277 3278 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3279 3280 if (page == HV_INTC_FC_PAGE_START) 3281 page = 0; 3282 3283 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3284 u32 phy_addr = hw->phy.addr; 3285 3286 hw->phy.addr = 1; 3287 3288 /* Page is shifted left, PHY expects (page x 32) */ 3289 ret_val = e1000_write_phy_reg_mdic(hw, 3290 IGP01E1000_PHY_PAGE_SELECT, 3291 (page << IGP_PAGE_SHIFT)); 3292 hw->phy.addr = phy_addr; 3293 3294 if (ret_val) 3295 goto out; 3296 } 3297 3298 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3299 data); 3300out: 3301 if (!locked) 3302 hw->phy.ops.release(hw); 3303 3304 return ret_val; 3305} 3306 3307/** 3308 * e1000_read_phy_reg_hv - Read HV PHY register 3309 * @hw: pointer to the HW structure 3310 * @offset: register offset to be read 3311 * @data: pointer to the read data 3312 * 3313 * Acquires semaphore then reads the PHY register at offset and stores 3314 * the retrieved information in data. Release the acquired semaphore 3315 * before exiting. 3316 **/ 3317s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3318{ 3319 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE); 3320} 3321 3322/** 3323 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3324 * @hw: pointer to the HW structure 3325 * @offset: register offset to be read 3326 * @data: pointer to the read data 3327 * 3328 * Reads the PHY register at offset and stores the retrieved information 3329 * in data. Assumes semaphore already acquired. 3330 **/ 3331s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3332{ 3333 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE); 3334} 3335 3336/** 3337 * __e1000_write_phy_reg_hv - Write HV PHY register 3338 * @hw: pointer to the HW structure 3339 * @offset: register offset to write to 3340 * @data: data to write at register offset 3341 * @locked: semaphore has already been acquired or not 3342 * 3343 * Acquires semaphore, if necessary, then writes the data to PHY register 3344 * at the offset. Release any acquired semaphores before exiting. 3345 **/ 3346static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3347 bool locked) 3348{ 3349 s32 ret_val; 3350 u16 page = BM_PHY_REG_PAGE(offset); 3351 u16 reg = BM_PHY_REG_NUM(offset); 3352 3353 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3354 3355 if (!locked) { 3356 ret_val = hw->phy.ops.acquire(hw); 3357 if (ret_val) 3358 return ret_val; 3359 } 3360 3361 /* Page 800 works differently than the rest so it has its own func */ 3362 if (page == BM_WUC_PAGE) { 3363 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3364 &data, FALSE); 3365 goto out; 3366 } 3367 3368 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3369 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3370 &data, FALSE); 3371 goto out; 3372 } 3373 3374 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3375 3376 if (page == HV_INTC_FC_PAGE_START) 3377 page = 0; 3378 3379 /* 3380 * Workaround MDIO accesses being disabled after entering IEEE Power 3381 * Down (whenever bit 11 of the PHY Control register is set) 3382 */ 3383 if ((hw->phy.type == e1000_phy_82578) && 3384 (hw->phy.revision >= 1) && 3385 (hw->phy.addr == 2) && 3386 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 3387 (data & (1 << 11))) { 3388 u16 data2 = 0x7EFF; 3389 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 3390 &data2, FALSE); 3391 if (ret_val) 3392 goto out; 3393 } 3394 3395 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3396 u32 phy_addr = hw->phy.addr; 3397 3398 hw->phy.addr = 1; 3399 3400 /* Page is shifted left, PHY expects (page x 32) */ 3401 ret_val = e1000_write_phy_reg_mdic(hw, 3402 IGP01E1000_PHY_PAGE_SELECT, 3403 (page << IGP_PAGE_SHIFT)); 3404 hw->phy.addr = phy_addr; 3405 3406 if (ret_val) 3407 goto out; 3408 } 3409 3410 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3411 data); 3412 3413out: 3414 if (!locked) 3415 hw->phy.ops.release(hw); 3416 3417 return ret_val; 3418} 3419 3420/** 3421 * e1000_write_phy_reg_hv - Write HV PHY register 3422 * @hw: pointer to the HW structure 3423 * @offset: register offset to write to 3424 * @data: data to write at register offset 3425 * 3426 * Acquires semaphore then writes the data to PHY register at the offset. 3427 * Release the acquired semaphores before exiting. 3428 **/ 3429s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3430{ 3431 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE); 3432} 3433 3434/** 3435 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3436 * @hw: pointer to the HW structure 3437 * @offset: register offset to write to 3438 * @data: data to write at register offset 3439 * 3440 * Writes the data to PHY register at the offset. Assumes semaphore 3441 * already acquired. 3442 **/ 3443s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3444{ 3445 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE); 3446} 3447 3448/** 3449 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3450 * @page: page to be accessed 3451 **/ 3452static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3453{ 3454 u32 phy_addr = 2; 3455 3456 if (page >= HV_INTC_FC_PAGE_START) 3457 phy_addr = 1; 3458 3459 return phy_addr; 3460} 3461 3462/** 3463 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3464 * @hw: pointer to the HW structure 3465 * @offset: register offset to be read or written 3466 * @data: pointer to the data to be read or written 3467 * @read: determines if operation is read or written 3468 * 3469 * Reads the PHY register at offset and stores the retreived information 3470 * in data. Assumes semaphore already acquired. Note that the procedure 3471 * to read these regs uses the address port and data port to read/write. 3472 **/ 3473static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3474 u16 *data, bool read) 3475{ 3476 s32 ret_val; 3477 u32 addr_reg = 0; 3478 u32 data_reg = 0; 3479 3480 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3481 3482 /* This takes care of the difference with desktop vs mobile phy */ 3483 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3484 I82578_ADDR_REG : I82577_ADDR_REG; 3485 data_reg = addr_reg + 1; 3486 3487 /* All operations in this function are phy address 2 */ 3488 hw->phy.addr = 2; 3489 3490 /* masking with 0x3F to remove the page from offset */ 3491 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3492 if (ret_val) { 3493 DEBUGOUT("Could not write PHY the HV address register\n"); 3494 goto out; 3495 } 3496 3497 /* Read or write the data value next */ 3498 if (read) 3499 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3500 else 3501 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3502 3503 if (ret_val) { 3504 DEBUGOUT("Could not read data value from HV data register\n"); 3505 goto out; 3506 } 3507 3508out: 3509 return ret_val; 3510} 3511 3512/** 3513 * e1000_link_stall_workaround_hv - Si workaround 3514 * @hw: pointer to the HW structure 3515 * 3516 * This function works around a Si bug where the link partner can get 3517 * a link up indication before the PHY does. If small packets are sent 3518 * by the link partner they can be placed in the packet buffer without 3519 * being properly accounted for by the PHY and will stall preventing 3520 * further packets from being received. The workaround is to clear the 3521 * packet buffer after the PHY detects link up. 3522 **/ 3523s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3524{ 3525 s32 ret_val = E1000_SUCCESS; 3526 u16 data; 3527 3528 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3529 3530 if (hw->phy.type != e1000_phy_82578) 3531 goto out; 3532 3533 /* Do not apply workaround if in PHY loopback bit 14 set */ 3534 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3535 if (data & PHY_CONTROL_LB) 3536 goto out; 3537 3538 /* check if link is up and at 1Gbps */ 3539 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3540 if (ret_val) 3541 goto out; 3542 3543 data &= BM_CS_STATUS_LINK_UP | 3544 BM_CS_STATUS_RESOLVED | 3545 BM_CS_STATUS_SPEED_MASK; 3546 3547 if (data != (BM_CS_STATUS_LINK_UP | 3548 BM_CS_STATUS_RESOLVED | 3549 BM_CS_STATUS_SPEED_1000)) 3550 goto out; 3551 3552 msec_delay(200); 3553 3554 /* flush the packets in the fifo buffer */ 3555 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3556 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3557 HV_MUX_DATA_CTRL_FORCE_SPEED); 3558 if (ret_val) 3559 goto out; 3560 3561 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3562 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3563 3564out: 3565 return ret_val; 3566} 3567 3568/** 3569 * e1000_check_polarity_82577 - Checks the polarity. 3570 * @hw: pointer to the HW structure 3571 * 3572 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3573 * 3574 * Polarity is determined based on the PHY specific status register. 3575 **/ 3576s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3577{ 3578 struct e1000_phy_info *phy = &hw->phy; 3579 s32 ret_val; 3580 u16 data; 3581 3582 DEBUGFUNC("e1000_check_polarity_82577"); 3583 3584 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3585 3586 if (!ret_val) 3587 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3588 ? e1000_rev_polarity_reversed 3589 : e1000_rev_polarity_normal; 3590 3591 return ret_val; 3592} 3593 3594/** 3595 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3596 * @hw: pointer to the HW structure 3597 * 3598 * Calls the PHY setup function to force speed and duplex. 3599 **/ 3600s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3601{ 3602 struct e1000_phy_info *phy = &hw->phy; 3603 s32 ret_val; 3604 u16 phy_data; 3605 bool link; 3606 3607 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3608 3609 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3610 if (ret_val) 3611 goto out; 3612 3613 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3614 3615 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3616 if (ret_val) 3617 goto out; 3618 3619 usec_delay(1); 3620 3621 if (phy->autoneg_wait_to_complete) { 3622 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3623 3624 ret_val = e1000_phy_has_link_generic(hw, 3625 PHY_FORCE_LIMIT, 3626 100000, 3627 &link); 3628 if (ret_val) 3629 goto out; 3630 3631 if (!link) 3632 DEBUGOUT("Link taking longer than expected.\n"); 3633 3634 /* Try once more */ 3635 ret_val = e1000_phy_has_link_generic(hw, 3636 PHY_FORCE_LIMIT, 3637 100000, 3638 &link); 3639 if (ret_val) 3640 goto out; 3641 } 3642 3643out: 3644 return ret_val; 3645} 3646 3647/** 3648 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3649 * @hw: pointer to the HW structure 3650 * 3651 * Read PHY status to determine if link is up. If link is up, then 3652 * set/determine 10base-T extended distance and polarity correction. Read 3653 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3654 * determine on the cable length, local and remote receiver. 3655 **/ 3656s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3657{ 3658 struct e1000_phy_info *phy = &hw->phy; 3659 s32 ret_val; 3660 u16 data; 3661 bool link; 3662 3663 DEBUGFUNC("e1000_get_phy_info_82577"); 3664 3665 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3666 if (ret_val) 3667 goto out; 3668 3669 if (!link) { 3670 DEBUGOUT("Phy info is only valid if link is up\n"); 3671 ret_val = -E1000_ERR_CONFIG; 3672 goto out; 3673 } 3674 3675 phy->polarity_correction = TRUE; 3676 3677 ret_val = e1000_check_polarity_82577(hw); 3678 if (ret_val) 3679 goto out; 3680 3681 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3682 if (ret_val) 3683 goto out; 3684 3685 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE; 3686 3687 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3688 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3689 ret_val = hw->phy.ops.get_cable_length(hw); 3690 if (ret_val) 3691 goto out; 3692 3693 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3694 if (ret_val) 3695 goto out; 3696 3697 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3698 ? e1000_1000t_rx_status_ok 3699 : e1000_1000t_rx_status_not_ok; 3700 3701 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3702 ? e1000_1000t_rx_status_ok 3703 : e1000_1000t_rx_status_not_ok; 3704 } else { 3705 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3706 phy->local_rx = e1000_1000t_rx_status_undefined; 3707 phy->remote_rx = e1000_1000t_rx_status_undefined; 3708 } 3709 3710out: 3711 return ret_val; 3712} 3713 3714/** 3715 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3716 * @hw: pointer to the HW structure 3717 * 3718 * Reads the diagnostic status register and verifies result is valid before 3719 * placing it in the phy_cable_length field. 3720 **/ 3721s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3722{ 3723 struct e1000_phy_info *phy = &hw->phy; 3724 s32 ret_val; 3725 u16 phy_data, length; 3726 3727 DEBUGFUNC("e1000_get_cable_length_82577"); 3728 3729 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3730 if (ret_val) 3731 goto out; 3732 3733 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3734 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3735 3736 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3737 ret_val = -E1000_ERR_PHY; 3738 3739 phy->cable_length = length; 3740 3741out: 3742 return ret_val; 3743} 3744