e1000_phy.c revision 169248
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/em/e1000_phy.c 169248 2007-05-04 13:30:44Z rwatson $"); 36 37 38#include "e1000_phy.h" 39 40static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 41static void e1000_release_phy(struct e1000_hw *hw); 42static s32 e1000_acquire_phy(struct e1000_hw *hw); 43 44/* Cable length tables */ 45static const 46u16 e1000_m88_cable_length_table[] = 47 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 48#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 49 (sizeof(e1000_m88_cable_length_table) / \ 50 sizeof(e1000_m88_cable_length_table[0])) 51 52static const 53u16 e1000_igp_2_cable_length_table[] = 54 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 55 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 56 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 57 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 58 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 59 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 60 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 61 104, 109, 114, 118, 121, 124}; 62#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 63 (sizeof(e1000_igp_2_cable_length_table) / \ 64 sizeof(e1000_igp_2_cable_length_table[0])) 65 66/** 67 * e1000_check_reset_block_generic - Check if PHY reset is blocked 68 * @hw - pointer to the HW structure 69 * 70 * Read the PHY management control register and check whether a PHY reset 71 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 72 * return E1000_BLK_PHY_RESET (12). 73 **/ 74s32 75e1000_check_reset_block_generic(struct e1000_hw *hw) 76{ 77 u32 manc; 78 79 DEBUGFUNC("e1000_check_reset_block"); 80 81 manc = E1000_READ_REG(hw, E1000_MANC); 82 83 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 84 E1000_BLK_PHY_RESET : E1000_SUCCESS; 85} 86 87/** 88 * e1000_get_phy_id - Retrieve the PHY ID and revision 89 * @hw - pointer to the HW structure 90 * 91 * Reads the PHY registers and stores the PHY ID and possibly the PHY 92 * revision in the hardware structure. 93 **/ 94s32 95e1000_get_phy_id(struct e1000_hw *hw) 96{ 97 struct e1000_phy_info *phy = &hw->phy; 98 s32 ret_val = E1000_SUCCESS; 99 u16 phy_id; 100 101 DEBUGFUNC("e1000_get_phy_id"); 102 103 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id); 104 if (ret_val) 105 goto out; 106 107 phy->id = (u32)(phy_id << 16); 108 usec_delay(20); 109 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id); 110 if (ret_val) 111 goto out; 112 113 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 114 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 115 116out: 117 return ret_val; 118} 119 120/** 121 * e1000_phy_reset_dsp_generic - Reset PHY DSP 122 * @hw - pointer to the HW structure 123 * 124 * Reset the digital signal processor. 125 **/ 126s32 127e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 128{ 129 s32 ret_val; 130 131 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 132 133 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 134 if (ret_val) 135 goto out; 136 137 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 138 139out: 140 return ret_val; 141} 142 143/** 144 * e1000_read_phy_reg_mdic - Read MDI control register 145 * @hw - pointer to the HW structure 146 * @offset - register offset to be read 147 * @data - pointer to the read data 148 * 149 * Reads the MDI control regsiter in the PHY at offset and stores the 150 * information read to data. 151 **/ 152static s32 153e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 154{ 155 struct e1000_phy_info *phy = &hw->phy; 156 u32 i, mdic = 0; 157 s32 ret_val = E1000_SUCCESS; 158 159 DEBUGFUNC("e1000_read_phy_reg_mdic"); 160 161 if (offset > MAX_PHY_REG_ADDRESS) { 162 DEBUGOUT1("PHY Address %d is out of range\n", offset); 163 ret_val = -E1000_ERR_PARAM; 164 goto out; 165 } 166 167 /* Set up Op-code, Phy Address, and register offset in the MDI 168 * Control register. The MAC will take care of interfacing with the 169 * PHY to retrieve the desired data. 170 */ 171 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 172 (phy->addr << E1000_MDIC_PHY_SHIFT) | 173 (E1000_MDIC_OP_READ)); 174 175 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 176 177 /* Poll the ready bit to see if the MDI read completed */ 178 for (i = 0; i < 64; i++) { 179 usec_delay(50); 180 mdic = E1000_READ_REG(hw, E1000_MDIC); 181 if (mdic & E1000_MDIC_READY) 182 break; 183 } 184 if (!(mdic & E1000_MDIC_READY)) { 185 DEBUGOUT("MDI Read did not complete\n"); 186 ret_val = -E1000_ERR_PHY; 187 goto out; 188 } 189 if (mdic & E1000_MDIC_ERROR) { 190 DEBUGOUT("MDI Error\n"); 191 ret_val = -E1000_ERR_PHY; 192 goto out; 193 } 194 *data = (u16) mdic; 195 196out: 197 return ret_val; 198} 199 200/** 201 * e1000_write_phy_reg_mdic - Write MDI control register 202 * @hw - pointer to the HW structure 203 * @offset - register offset to write to 204 * @data - data to write to register at offset 205 * 206 * Writes data to MDI control register in the PHY at offset. 207 **/ 208static s32 209e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 210{ 211 struct e1000_phy_info *phy = &hw->phy; 212 u32 i, mdic = 0; 213 s32 ret_val = E1000_SUCCESS; 214 215 DEBUGFUNC("e1000_write_phy_reg_mdic"); 216 217 if (offset > MAX_PHY_REG_ADDRESS) { 218 DEBUGOUT1("PHY Address %d is out of range\n", offset); 219 ret_val = -E1000_ERR_PARAM; 220 goto out; 221 } 222 223 /* Set up Op-code, Phy Address, and register offset in the MDI 224 * Control register. The MAC will take care of interfacing with the 225 * PHY to retrieve the desired data. 226 */ 227 mdic = (((u32)data) | 228 (offset << E1000_MDIC_REG_SHIFT) | 229 (phy->addr << E1000_MDIC_PHY_SHIFT) | 230 (E1000_MDIC_OP_WRITE)); 231 232 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 233 234 /* Poll the ready bit to see if the MDI read completed */ 235 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 236 usec_delay(5); 237 mdic = E1000_READ_REG(hw, E1000_MDIC); 238 if (mdic & E1000_MDIC_READY) 239 break; 240 } 241 if (!(mdic & E1000_MDIC_READY)) { 242 DEBUGOUT("MDI Write did not complete\n"); 243 ret_val = -E1000_ERR_PHY; 244 goto out; 245 } 246 247out: 248 return ret_val; 249} 250 251/** 252 * e1000_read_phy_reg_m88 - Read m88 PHY register 253 * @hw - pointer to the HW structure 254 * @offset - register offset to be read 255 * @data - pointer to the read data 256 * 257 * Acquires semaphore, if necessary, then reads the PHY register at offset 258 * and storing the retrieved information in data. Release any acquired 259 * semaphores before exiting. 260 **/ 261s32 262e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 263{ 264 s32 ret_val; 265 266 DEBUGFUNC("e1000_read_phy_reg_m88"); 267 268 ret_val = e1000_acquire_phy(hw); 269 if (ret_val) 270 goto out; 271 272 ret_val = e1000_read_phy_reg_mdic(hw, 273 MAX_PHY_REG_ADDRESS & offset, 274 data); 275 276 e1000_release_phy(hw); 277 278out: 279 return ret_val; 280} 281 282/** 283 * e1000_write_phy_reg_m88 - Write m88 PHY register 284 * @hw - pointer to the HW structure 285 * @offset - register offset to write to 286 * @data - data to write at register offset 287 * 288 * Acquires semaphore, if necessary, then writes the data to PHY register 289 * at the offset. Release any acquired semaphores before exiting. 290 **/ 291s32 292e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 293{ 294 s32 ret_val; 295 296 DEBUGFUNC("e1000_write_phy_reg_m88"); 297 298 ret_val = e1000_acquire_phy(hw); 299 if (ret_val) 300 goto out; 301 302 ret_val = e1000_write_phy_reg_mdic(hw, 303 MAX_PHY_REG_ADDRESS & offset, 304 data); 305 306 e1000_release_phy(hw); 307 308out: 309 return ret_val; 310} 311 312/** 313 * e1000_read_phy_reg_igp - Read igp PHY register 314 * @hw - pointer to the HW structure 315 * @offset - register offset to be read 316 * @data - pointer to the read data 317 * 318 * Acquires semaphore, if necessary, then reads the PHY register at offset 319 * and storing the retrieved information in data. Release any acquired 320 * semaphores before exiting. 321 **/ 322s32 323e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 324{ 325 s32 ret_val; 326 327 DEBUGFUNC("e1000_read_phy_reg_igp"); 328 329 ret_val = e1000_acquire_phy(hw); 330 if (ret_val) 331 goto out; 332 333 if (offset > MAX_PHY_MULTI_PAGE_REG) { 334 ret_val = e1000_write_phy_reg_mdic(hw, 335 IGP01E1000_PHY_PAGE_SELECT, 336 (u16)offset); 337 if (ret_val) { 338 e1000_release_phy(hw); 339 goto out; 340 } 341 } 342 343 ret_val = e1000_read_phy_reg_mdic(hw, 344 MAX_PHY_REG_ADDRESS & offset, 345 data); 346 347 e1000_release_phy(hw); 348 349out: 350 return ret_val; 351} 352 353/** 354 * e1000_write_phy_reg_igp - Write igp PHY register 355 * @hw - pointer to the HW structure 356 * @offset - register offset to write to 357 * @data - data to write at register offset 358 * 359 * Acquires semaphore, if necessary, then writes the data to PHY register 360 * at the offset. Release any acquired semaphores before exiting. 361 **/ 362s32 363e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 364{ 365 s32 ret_val; 366 367 DEBUGFUNC("e1000_write_phy_reg_igp"); 368 369 ret_val = e1000_acquire_phy(hw); 370 if (ret_val) 371 goto out; 372 373 if (offset > MAX_PHY_MULTI_PAGE_REG) { 374 ret_val = e1000_write_phy_reg_mdic(hw, 375 IGP01E1000_PHY_PAGE_SELECT, 376 (u16)offset); 377 if (ret_val) { 378 e1000_release_phy(hw); 379 goto out; 380 } 381 } 382 383 ret_val = e1000_write_phy_reg_mdic(hw, 384 MAX_PHY_REG_ADDRESS & offset, 385 data); 386 387 e1000_release_phy(hw); 388 389out: 390 return ret_val; 391} 392 393/** 394 * e1000_read_kmrn_reg_generic - Read kumeran register 395 * @hw - pointer to the HW structure 396 * @offset - register offset to be read 397 * @data - pointer to the read data 398 * 399 * Acquires semaphore, if necessary. Then reads the PHY register at offset 400 * using the kumeran interface. The information retrieved is stored in data. 401 * Release any acquired semaphores before exiting. 402 **/ 403s32 404e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 405{ 406 u32 kmrnctrlsta; 407 s32 ret_val; 408 409 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 410 411 ret_val = e1000_acquire_phy(hw); 412 if (ret_val) 413 goto out; 414 415 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 416 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 417 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 418 419 usec_delay(2); 420 421 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 422 *data = (u16)kmrnctrlsta; 423 424 e1000_release_phy(hw); 425 426out: 427 return ret_val; 428} 429 430/** 431 * e1000_write_kmrn_reg_generic - Write kumeran register 432 * @hw - pointer to the HW structure 433 * @offset - register offset to write to 434 * @data - data to write at register offset 435 * 436 * Acquires semaphore, if necessary. Then write the data to PHY register 437 * at the offset using the kumeran interface. Release any acquired semaphores 438 * before exiting. 439 **/ 440s32 441e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 442{ 443 u32 kmrnctrlsta; 444 s32 ret_val; 445 446 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 447 448 ret_val = e1000_acquire_phy(hw); 449 if (ret_val) 450 goto out; 451 452 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 453 E1000_KMRNCTRLSTA_OFFSET) | data; 454 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 455 456 usec_delay(2); 457 e1000_release_phy(hw); 458 459out: 460 return ret_val; 461} 462 463/** 464 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 465 * @hw - pointer to the HW structure 466 * 467 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 468 * and downshift values are set also. 469 **/ 470s32 471e1000_copper_link_setup_m88(struct e1000_hw *hw) 472{ 473 struct e1000_phy_info *phy = &hw->phy; 474 s32 ret_val; 475 u16 phy_data; 476 477 DEBUGFUNC("e1000_copper_link_setup_m88"); 478 479 if (phy->reset_disable) { 480 ret_val = E1000_SUCCESS; 481 goto out; 482 } 483 484 /* Enable CRS on TX. This must be set for half-duplex operation. */ 485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 486 if (ret_val) 487 goto out; 488 489 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 490 491 /* Options: 492 * MDI/MDI-X = 0 (default) 493 * 0 - Auto for all speeds 494 * 1 - MDI mode 495 * 2 - MDI-X mode 496 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 497 */ 498 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 499 500 switch (phy->mdix) { 501 case 1: 502 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 503 break; 504 case 2: 505 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 506 break; 507 case 3: 508 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 509 break; 510 case 0: 511 default: 512 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 513 break; 514 } 515 516 /* Options: 517 * disable_polarity_correction = 0 (default) 518 * Automatic Correction for Reversed Cable Polarity 519 * 0 - Disabled 520 * 1 - Enabled 521 */ 522 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 523 if (phy->disable_polarity_correction == 1) 524 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 525 526 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 527 if (ret_val) 528 goto out; 529 530 if (phy->revision < E1000_REVISION_4) { 531 /* Force TX_CLK in the Extended PHY Specific Control Register 532 * to 25MHz clock. 533 */ 534 ret_val = e1000_read_phy_reg(hw, 535 M88E1000_EXT_PHY_SPEC_CTRL, 536 &phy_data); 537 if (ret_val) 538 goto out; 539 540 phy_data |= M88E1000_EPSCR_TX_CLK_25; 541 542 if ((phy->revision == E1000_REVISION_2) && 543 (phy->id == M88E1111_I_PHY_ID)) { 544 /* 82573L PHY - set the downshift counter to 5x. */ 545 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 546 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 547 } else { 548 /* Configure Master and Slave downshift values */ 549 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 550 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 551 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 552 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 553 } 554 ret_val = e1000_write_phy_reg(hw, 555 M88E1000_EXT_PHY_SPEC_CTRL, 556 phy_data); 557 if (ret_val) 558 goto out; 559 } 560 561 /* Commit the changes. */ 562 ret_val = e1000_phy_commit(hw); 563 if (ret_val) { 564 DEBUGOUT("Error committing the PHY changes\n"); 565 goto out; 566 } 567 568out: 569 return ret_val; 570} 571 572/** 573 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 574 * @hw - pointer to the HW structure 575 * 576 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 577 * igp PHY's. 578 **/ 579s32 580e1000_copper_link_setup_igp(struct e1000_hw *hw) 581{ 582 struct e1000_phy_info *phy = &hw->phy; 583 s32 ret_val; 584 u16 data; 585 586 DEBUGFUNC("e1000_copper_link_setup_igp"); 587 588 if (phy->reset_disable) { 589 ret_val = E1000_SUCCESS; 590 goto out; 591 } 592 593 ret_val = e1000_phy_hw_reset(hw); 594 if (ret_val) { 595 DEBUGOUT("Error resetting the PHY.\n"); 596 goto out; 597 } 598 599 /* Wait 15ms for MAC to configure PHY from NVM settings. */ 600 msec_delay(15); 601 602 /* The NVM settings will configure LPLU in D3 for 603 * non-IGP1 PHYs. */ 604 if (phy->type == e1000_phy_igp) { 605 /* disable lplu d3 during driver init */ 606 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 607 if (ret_val) { 608 DEBUGOUT("Error Disabling LPLU D3\n"); 609 goto out; 610 } 611 } 612 613 /* disable lplu d0 during driver init */ 614 ret_val = e1000_set_d0_lplu_state(hw, FALSE); 615 if (ret_val) { 616 DEBUGOUT("Error Disabling LPLU D0\n"); 617 goto out; 618 } 619 /* Configure mdi-mdix settings */ 620 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 621 if (ret_val) 622 goto out; 623 624 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 625 626 switch (phy->mdix) { 627 case 1: 628 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 629 break; 630 case 2: 631 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 632 break; 633 case 0: 634 default: 635 data |= IGP01E1000_PSCR_AUTO_MDIX; 636 break; 637 } 638 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 639 if (ret_val) 640 goto out; 641 642 /* set auto-master slave resolution settings */ 643 if (hw->mac.autoneg) { 644 /* when autonegotiation advertisement is only 1000Mbps then we 645 * should disable SmartSpeed and enable Auto MasterSlave 646 * resolution as hardware default. */ 647 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 648 /* Disable SmartSpeed */ 649 ret_val = e1000_read_phy_reg(hw, 650 IGP01E1000_PHY_PORT_CONFIG, 651 &data); 652 if (ret_val) 653 goto out; 654 655 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 656 ret_val = e1000_write_phy_reg(hw, 657 IGP01E1000_PHY_PORT_CONFIG, 658 data); 659 if (ret_val) 660 goto out; 661 662 /* Set auto Master/Slave resolution process */ 663 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); 664 if (ret_val) 665 goto out; 666 667 data &= ~CR_1000T_MS_ENABLE; 668 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); 669 if (ret_val) 670 goto out; 671 } 672 673 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data); 674 if (ret_val) 675 goto out; 676 677 /* load defaults for future use */ 678 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 679 ((data & CR_1000T_MS_VALUE) ? 680 e1000_ms_force_master : 681 e1000_ms_force_slave) : 682 e1000_ms_auto; 683 684 switch (phy->ms_type) { 685 case e1000_ms_force_master: 686 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 687 break; 688 case e1000_ms_force_slave: 689 data |= CR_1000T_MS_ENABLE; 690 data &= ~(CR_1000T_MS_VALUE); 691 break; 692 case e1000_ms_auto: 693 data &= ~CR_1000T_MS_ENABLE; 694 default: 695 break; 696 } 697 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data); 698 if (ret_val) 699 goto out; 700 } 701 702out: 703 return ret_val; 704} 705 706/** 707 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 708 * @hw - pointer to the HW structure 709 * 710 * Performs initial bounds checking on autoneg advertisement parameter, then 711 * configure to advertise the full capability. Setup the PHY to autoneg 712 * and restart the negotiation process between the link partner. If 713 * wait_for_link, then wait for autoneg to complete before exiting. 714 **/ 715s32 716e1000_copper_link_autoneg(struct e1000_hw *hw) 717{ 718 struct e1000_phy_info *phy = &hw->phy; 719 s32 ret_val; 720 u16 phy_ctrl; 721 722 DEBUGFUNC("e1000_copper_link_autoneg"); 723 724 /* Perform some bounds checking on the autoneg advertisement 725 * parameter. 726 */ 727 phy->autoneg_advertised &= phy->autoneg_mask; 728 729 /* If autoneg_advertised is zero, we assume it was not defaulted 730 * by the calling code so we set to advertise full capability. 731 */ 732 if (phy->autoneg_advertised == 0) 733 phy->autoneg_advertised = phy->autoneg_mask; 734 735 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 736 ret_val = e1000_phy_setup_autoneg(hw); 737 if (ret_val) { 738 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 739 goto out; 740 } 741 DEBUGOUT("Restarting Auto-Neg\n"); 742 743 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 744 * the Auto Neg Restart bit in the PHY control register. 745 */ 746 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 747 if (ret_val) 748 goto out; 749 750 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 751 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 752 if (ret_val) 753 goto out; 754 755 /* Does the user want to wait for Auto-Neg to complete here, or 756 * check at a later time (for example, callback routine). 757 */ 758 if (phy->wait_for_link) { 759 ret_val = e1000_wait_autoneg(hw); 760 if (ret_val) { 761 DEBUGOUT("Error while waiting for " 762 "autoneg to complete\n"); 763 goto out; 764 } 765 } 766 767 hw->mac.get_link_status = TRUE; 768 769out: 770 return ret_val; 771} 772 773/** 774 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 775 * @hw - pointer to the HW structure 776 * 777 * Reads the MII auto-neg advertisement register and/or the 1000T control 778 * register and if the PHY is already setup for auto-negotiation, then 779 * return successful. Otherwise, setup advertisement and flow control to 780 * the appropriate values for the wanted auto-negotiation. 781 **/ 782s32 783e1000_phy_setup_autoneg(struct e1000_hw *hw) 784{ 785 struct e1000_phy_info *phy = &hw->phy; 786 s32 ret_val; 787 u16 mii_autoneg_adv_reg; 788 u16 mii_1000t_ctrl_reg = 0; 789 790 DEBUGFUNC("e1000_phy_setup_autoneg"); 791 792 phy->autoneg_advertised &= phy->autoneg_mask; 793 794 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 795 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 796 if (ret_val) 797 goto out; 798 799 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 800 /* Read the MII 1000Base-T Control Register (Address 9). */ 801 ret_val = e1000_read_phy_reg(hw, 802 PHY_1000T_CTRL, 803 &mii_1000t_ctrl_reg); 804 if (ret_val) 805 goto out; 806 } 807 808 /* Need to parse both autoneg_advertised and fc and set up 809 * the appropriate PHY registers. First we will parse for 810 * autoneg_advertised software override. Since we can advertise 811 * a plethora of combinations, we need to check each bit 812 * individually. 813 */ 814 815 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 816 * Advertisement Register (Address 4) and the 1000 mb speed bits in 817 * the 1000Base-T Control Register (Address 9). 818 */ 819 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 820 NWAY_AR_100TX_HD_CAPS | 821 NWAY_AR_10T_FD_CAPS | 822 NWAY_AR_10T_HD_CAPS); 823 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 824 825 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 826 827 /* Do we want to advertise 10 Mb Half Duplex? */ 828 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 829 DEBUGOUT("Advertise 10mb Half duplex\n"); 830 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 831 } 832 833 /* Do we want to advertise 10 Mb Full Duplex? */ 834 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 835 DEBUGOUT("Advertise 10mb Full duplex\n"); 836 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 837 } 838 839 /* Do we want to advertise 100 Mb Half Duplex? */ 840 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 841 DEBUGOUT("Advertise 100mb Half duplex\n"); 842 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 843 } 844 845 /* Do we want to advertise 100 Mb Full Duplex? */ 846 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 847 DEBUGOUT("Advertise 100mb Full duplex\n"); 848 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 849 } 850 851 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 852 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) { 853 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 854 } 855 856 /* Do we want to advertise 1000 Mb Full Duplex? */ 857 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 858 DEBUGOUT("Advertise 1000mb Full duplex\n"); 859 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 860 } 861 862 /* Check for a software override of the flow control settings, and 863 * setup the PHY advertisement registers accordingly. If 864 * auto-negotiation is enabled, then software will have to set the 865 * "PAUSE" bits to the correct value in the Auto-Negotiation 866 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 867 * negotiation. 868 * 869 * The possible values of the "fc" parameter are: 870 * 0: Flow control is completely disabled 871 * 1: Rx flow control is enabled (we can receive pause frames 872 * but not send pause frames). 873 * 2: Tx flow control is enabled (we can send pause frames 874 * but we do not support receiving pause frames). 875 * 3: Both Rx and TX flow control (symmetric) are enabled. 876 * other: No software override. The flow control configuration 877 * in the EEPROM is used. 878 */ 879 switch (hw->mac.fc) { 880 case e1000_fc_none: 881 /* Flow control (RX & TX) is completely disabled by a 882 * software over-ride. 883 */ 884 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 885 break; 886 case e1000_fc_rx_pause: 887 /* RX Flow control is enabled, and TX Flow control is 888 * disabled, by a software over-ride. 889 */ 890 /* Since there really isn't a way to advertise that we are 891 * capable of RX Pause ONLY, we will advertise that we 892 * support both symmetric and asymmetric RX PAUSE. Later 893 * (in e1000_config_fc_after_link_up) we will disable the 894 * hw's ability to send PAUSE frames. 895 */ 896 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 897 break; 898 case e1000_fc_tx_pause: 899 /* TX Flow control is enabled, and RX Flow control is 900 * disabled, by a software over-ride. 901 */ 902 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 903 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 904 break; 905 case e1000_fc_full: 906 /* Flow control (both RX and TX) is enabled by a software 907 * over-ride. 908 */ 909 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 910 break; 911 default: 912 DEBUGOUT("Flow control param set incorrectly\n"); 913 ret_val = -E1000_ERR_CONFIG; 914 goto out; 915 } 916 917 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 918 if (ret_val) 919 goto out; 920 921 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 922 923 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 924 ret_val = e1000_write_phy_reg(hw, 925 PHY_1000T_CTRL, 926 mii_1000t_ctrl_reg); 927 if (ret_val) 928 goto out; 929 } 930 931out: 932 return ret_val; 933} 934 935/** 936 * e1000_setup_copper_link_generic - Configure copper link settings 937 * @hw - pointer to the HW structure 938 * 939 * Calls the appropriate function to configure the link for auto-neg or forced 940 * speed and duplex. Then we check for link, once link is established calls 941 * to configure collision distance and flow control are called. If link is 942 * not established, we return -E1000_ERR_PHY (-2). 943 **/ 944s32 945e1000_setup_copper_link_generic(struct e1000_hw *hw) 946{ 947 s32 ret_val; 948 boolean_t link; 949 950 DEBUGFUNC("e1000_setup_copper_link_generic"); 951 952 if (hw->mac.autoneg) { 953 /* Setup autoneg and flow control advertisement and perform 954 * autonegotiation. */ 955 ret_val = e1000_copper_link_autoneg(hw); 956 if (ret_val) 957 goto out; 958 } else { 959 /* PHY will be set to 10H, 10F, 100H or 100F 960 * depending on user settings. */ 961 DEBUGOUT("Forcing Speed and Duplex\n"); 962 ret_val = e1000_phy_force_speed_duplex(hw); 963 if (ret_val) { 964 DEBUGOUT("Error Forcing Speed and Duplex\n"); 965 goto out; 966 } 967 } 968 969 /* Check link status. Wait up to 100 microseconds for link to become 970 * valid. 971 */ 972 ret_val = e1000_phy_has_link_generic(hw, 973 COPPER_LINK_UP_LIMIT, 974 10, 975 &link); 976 if (ret_val) 977 goto out; 978 979 if (link) { 980 DEBUGOUT("Valid link established!!!\n"); 981 e1000_config_collision_dist_generic(hw); 982 ret_val = e1000_config_fc_after_link_up_generic(hw); 983 } else { 984 DEBUGOUT("Unable to establish link!!!\n"); 985 } 986 987out: 988 return ret_val; 989} 990 991/** 992 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 993 * @hw - pointer to the HW structure 994 * 995 * Calls the PHY setup function to force speed and duplex. Clears the 996 * auto-crossover to force MDI manually. Waits for link and returns 997 * successful if link up is successful, else -E1000_ERR_PHY (-2). 998 **/ 999s32 1000e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1001{ 1002 struct e1000_phy_info *phy = &hw->phy; 1003 s32 ret_val; 1004 u16 phy_data; 1005 boolean_t link; 1006 1007 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1008 1009 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 1010 if (ret_val) 1011 goto out; 1012 1013 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1014 1015 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 1016 if (ret_val) 1017 goto out; 1018 1019 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1020 * forced whenever speed and duplex are forced. 1021 */ 1022 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1023 if (ret_val) 1024 goto out; 1025 1026 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1027 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1028 1029 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1030 if (ret_val) 1031 goto out; 1032 1033 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1034 1035 usec_delay(1); 1036 1037 if (phy->wait_for_link) { 1038 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1039 1040 ret_val = e1000_phy_has_link_generic(hw, 1041 PHY_FORCE_LIMIT, 1042 100000, 1043 &link); 1044 if (ret_val) 1045 goto out; 1046 1047 if (!link) { 1048 DEBUGOUT("Link taking longer than expected.\n"); 1049 } 1050 1051 /* Try once more */ 1052 ret_val = e1000_phy_has_link_generic(hw, 1053 PHY_FORCE_LIMIT, 1054 100000, 1055 &link); 1056 if (ret_val) 1057 goto out; 1058 } 1059 1060out: 1061 return ret_val; 1062} 1063 1064/** 1065 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1066 * @hw - pointer to the HW structure 1067 * 1068 * Calls the PHY setup function to force speed and duplex. Clears the 1069 * auto-crossover to force MDI manually. Resets the PHY to commit the 1070 * changes. If time expires while waiting for link up, we reset the DSP. 1071 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1072 * successful completion, else return corresponding error code. 1073 **/ 1074s32 1075e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1076{ 1077 struct e1000_phy_info *phy = &hw->phy; 1078 s32 ret_val; 1079 u16 phy_data; 1080 boolean_t link; 1081 1082 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1083 1084 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1085 * forced whenever speed and duplex are forced. 1086 */ 1087 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1088 if (ret_val) 1089 goto out; 1090 1091 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1092 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1093 if (ret_val) 1094 goto out; 1095 1096 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1097 1098 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 1099 if (ret_val) 1100 goto out; 1101 1102 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1103 1104 /* Reset the phy to commit changes. */ 1105 phy_data |= MII_CR_RESET; 1106 1107 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 1108 if (ret_val) 1109 goto out; 1110 1111 usec_delay(1); 1112 1113 if (phy->wait_for_link) { 1114 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1115 1116 ret_val = e1000_phy_has_link_generic(hw, 1117 PHY_FORCE_LIMIT, 1118 100000, 1119 &link); 1120 if (ret_val) 1121 goto out; 1122 1123 if (!link) { 1124 /* We didn't get link. 1125 * Reset the DSP and cross our fingers. 1126 */ 1127 ret_val = e1000_write_phy_reg(hw, 1128 M88E1000_PHY_PAGE_SELECT, 1129 0x001d); 1130 if (ret_val) 1131 goto out; 1132 ret_val = e1000_phy_reset_dsp_generic(hw); 1133 if (ret_val) 1134 goto out; 1135 } 1136 1137 /* Try once more */ 1138 ret_val = e1000_phy_has_link_generic(hw, 1139 PHY_FORCE_LIMIT, 1140 100000, 1141 &link); 1142 if (ret_val) 1143 goto out; 1144 } 1145 1146 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1147 if (ret_val) 1148 goto out; 1149 1150 /* Resetting the phy means we need to re-force TX_CLK in the 1151 * Extended PHY Specific Control Register to 25MHz clock from 1152 * the reset value of 2.5MHz. 1153 */ 1154 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1155 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1156 if (ret_val) 1157 goto out; 1158 1159 /* In addition, we must re-enable CRS on Tx for both half and full 1160 * duplex. 1161 */ 1162 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1163 if (ret_val) 1164 goto out; 1165 1166 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1167 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1168 1169out: 1170 return ret_val; 1171} 1172 1173/** 1174 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1175 * @hw - pointer to the HW structure 1176 * @phy_ctrl - pointer to current value of PHY_CONTROL 1177 * 1178 * Forces speed and duplex on the PHY by doing the following: disable flow 1179 * control, force speed/duplex on the MAC, disable auto speed detection, 1180 * disable auto-negotiation, configure duplex, configure speed, configure 1181 * the collision distance, write configuration to CTRL register. The 1182 * caller must write to the PHY_CONTROL register for these settings to 1183 * take affect. 1184 **/ 1185void 1186e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1187{ 1188 struct e1000_mac_info *mac = &hw->mac; 1189 u32 ctrl; 1190 1191 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1192 1193 /* Turn off flow control when forcing speed/duplex */ 1194 mac->fc = e1000_fc_none; 1195 1196 /* Force speed/duplex on the mac */ 1197 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1198 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1199 ctrl &= ~E1000_CTRL_SPD_SEL; 1200 1201 /* Disable Auto Speed Detection */ 1202 ctrl &= ~E1000_CTRL_ASDE; 1203 1204 /* Disable autoneg on the phy */ 1205 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1206 1207 /* Forcing Full or Half Duplex? */ 1208 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1209 ctrl &= ~E1000_CTRL_FD; 1210 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1211 DEBUGOUT("Half Duplex\n"); 1212 } else { 1213 ctrl |= E1000_CTRL_FD; 1214 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1215 DEBUGOUT("Full Duplex\n"); 1216 } 1217 1218 /* Forcing 10mb or 100mb? */ 1219 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1220 ctrl |= E1000_CTRL_SPD_100; 1221 *phy_ctrl |= MII_CR_SPEED_100; 1222 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1223 DEBUGOUT("Forcing 100mb\n"); 1224 } else { 1225 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1226 *phy_ctrl |= MII_CR_SPEED_10; 1227 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1228 DEBUGOUT("Forcing 10mb\n"); 1229 } 1230 1231 e1000_config_collision_dist_generic(hw); 1232 1233 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1234} 1235 1236/** 1237 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1238 * @hw - pointer to the HW structure 1239 * @active boolean used to enable/disable lplu 1240 * 1241 * Success returns 0, Failure returns 1 1242 * 1243 * The low power link up (lplu) state is set to the power management level D3 1244 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1245 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1246 * is used during Dx states where the power conservation is most important. 1247 * During driver activity, SmartSpeed should be enabled so performance is 1248 * maintained. 1249 **/ 1250s32 1251e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active) 1252{ 1253 struct e1000_phy_info *phy = &hw->phy; 1254 s32 ret_val; 1255 u16 data; 1256 1257 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1258 1259 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1260 if (ret_val) 1261 goto out; 1262 1263 if (!active) { 1264 data &= ~IGP02E1000_PM_D3_LPLU; 1265 ret_val = e1000_write_phy_reg(hw, 1266 IGP02E1000_PHY_POWER_MGMT, 1267 data); 1268 if (ret_val) 1269 goto out; 1270 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1271 * during Dx states where the power conservation is most 1272 * important. During driver activity we should enable 1273 * SmartSpeed, so performance is maintained. */ 1274 if (phy->smart_speed == e1000_smart_speed_on) { 1275 ret_val = e1000_read_phy_reg(hw, 1276 IGP01E1000_PHY_PORT_CONFIG, 1277 &data); 1278 if (ret_val) 1279 goto out; 1280 1281 data |= IGP01E1000_PSCFR_SMART_SPEED; 1282 ret_val = e1000_write_phy_reg(hw, 1283 IGP01E1000_PHY_PORT_CONFIG, 1284 data); 1285 if (ret_val) 1286 goto out; 1287 } else if (phy->smart_speed == e1000_smart_speed_off) { 1288 ret_val = e1000_read_phy_reg(hw, 1289 IGP01E1000_PHY_PORT_CONFIG, 1290 &data); 1291 if (ret_val) 1292 goto out; 1293 1294 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1295 ret_val = e1000_write_phy_reg(hw, 1296 IGP01E1000_PHY_PORT_CONFIG, 1297 data); 1298 if (ret_val) 1299 goto out; 1300 } 1301 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1302 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1303 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1304 data |= IGP02E1000_PM_D3_LPLU; 1305 ret_val = e1000_write_phy_reg(hw, 1306 IGP02E1000_PHY_POWER_MGMT, 1307 data); 1308 if (ret_val) 1309 goto out; 1310 1311 /* When LPLU is enabled, we should disable SmartSpeed */ 1312 ret_val = e1000_read_phy_reg(hw, 1313 IGP01E1000_PHY_PORT_CONFIG, 1314 &data); 1315 if (ret_val) 1316 goto out; 1317 1318 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1319 ret_val = e1000_write_phy_reg(hw, 1320 IGP01E1000_PHY_PORT_CONFIG, 1321 data); 1322 } 1323 1324out: 1325 return ret_val; 1326} 1327 1328/** 1329 * e1000_check_downshift_generic - Checks whether a downshift in speed occured 1330 * @hw - pointer to the HW structure 1331 * 1332 * Success returns 0, Failure returns 1 1333 * 1334 * A downshift is detected by querying the PHY link health. 1335 **/ 1336s32 1337e1000_check_downshift_generic(struct e1000_hw *hw) 1338{ 1339 struct e1000_phy_info *phy = &hw->phy; 1340 s32 ret_val; 1341 u16 phy_data, offset, mask; 1342 1343 DEBUGFUNC("e1000_check_downshift_generic"); 1344 1345 switch (phy->type) { 1346 case e1000_phy_m88: 1347 case e1000_phy_gg82563: 1348 offset = M88E1000_PHY_SPEC_STATUS; 1349 mask = M88E1000_PSSR_DOWNSHIFT; 1350 break; 1351 case e1000_phy_igp_2: 1352 case e1000_phy_igp: 1353 case e1000_phy_igp_3: 1354 offset = IGP01E1000_PHY_LINK_HEALTH; 1355 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1356 break; 1357 default: 1358 /* speed downshift not supported */ 1359 phy->speed_downgraded = FALSE; 1360 ret_val = E1000_SUCCESS; 1361 goto out; 1362 } 1363 1364 ret_val = e1000_read_phy_reg(hw, offset, &phy_data); 1365 1366 if (!ret_val) 1367 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1368 1369out: 1370 return ret_val; 1371} 1372 1373/** 1374 * e1000_check_polarity_m88 - Checks the polarity. 1375 * @hw - pointer to the HW structure 1376 * 1377 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1378 * 1379 * Polarity is determined based on the PHY specific status register. 1380 **/ 1381s32 1382e1000_check_polarity_m88(struct e1000_hw *hw) 1383{ 1384 struct e1000_phy_info *phy = &hw->phy; 1385 s32 ret_val; 1386 u16 data; 1387 1388 DEBUGFUNC("e1000_check_polarity_m88"); 1389 1390 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1391 1392 if (!ret_val) 1393 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1394 ? e1000_rev_polarity_reversed 1395 : e1000_rev_polarity_normal; 1396 1397 return ret_val; 1398} 1399 1400/** 1401 * e1000_check_polarity_igp - Checks the polarity. 1402 * @hw - pointer to the HW structure 1403 * 1404 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1405 * 1406 * Polarity is determined based on the PHY port status register, and the 1407 * current speed (since there is no polarity at 100Mbps). 1408 **/ 1409s32 1410e1000_check_polarity_igp(struct e1000_hw *hw) 1411{ 1412 struct e1000_phy_info *phy = &hw->phy; 1413 s32 ret_val; 1414 u16 data, offset, mask; 1415 1416 DEBUGFUNC("e1000_check_polarity_igp"); 1417 1418 /* Polarity is determined based on the speed of 1419 * our connection. */ 1420 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1421 if (ret_val) 1422 goto out; 1423 1424 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1425 IGP01E1000_PSSR_SPEED_1000MBPS) { 1426 offset = IGP01E1000_PHY_PCS_INIT_REG; 1427 mask = IGP01E1000_PHY_POLARITY_MASK; 1428 } else { 1429 /* This really only applies to 10Mbps since 1430 * there is no polarity for 100Mbps (always 0). 1431 */ 1432 offset = IGP01E1000_PHY_PORT_STATUS; 1433 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1434 } 1435 1436 ret_val = e1000_read_phy_reg(hw, offset, &data); 1437 1438 if (!ret_val) 1439 phy->cable_polarity = (data & mask) 1440 ? e1000_rev_polarity_reversed 1441 : e1000_rev_polarity_normal; 1442 1443out: 1444 return ret_val; 1445} 1446 1447/** 1448 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion 1449 * @hw - pointer to the HW structure 1450 * 1451 * Waits for auto-negotiation to complete or for the auto-negotiation time 1452 * limit to expire, which ever happens first. 1453 **/ 1454s32 1455e1000_wait_autoneg_generic(struct e1000_hw *hw) 1456{ 1457 s32 ret_val = E1000_SUCCESS; 1458 u16 i, phy_status; 1459 1460 DEBUGFUNC("e1000_wait_autoneg_generic"); 1461 1462 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1463 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1464 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1465 if (ret_val) 1466 break; 1467 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1468 if (ret_val) 1469 break; 1470 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1471 break; 1472 msec_delay(100); 1473 } 1474 1475 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1476 * has completed. 1477 */ 1478 return ret_val; 1479} 1480 1481/** 1482 * e1000_phy_has_link_generic - Polls PHY for link 1483 * @hw - pointer to the HW structure 1484 * @iterations - number of times to poll for link 1485 * @usec_interval - delay between polling attempts 1486 * @success - pointer to whether polling was successful or not 1487 * 1488 * Polls the PHY status register for link, 'iterations' number of times. 1489 **/ 1490s32 1491e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1492 u32 usec_interval, boolean_t *success) 1493{ 1494 s32 ret_val = E1000_SUCCESS; 1495 u16 i, phy_status; 1496 1497 DEBUGFUNC("e1000_phy_has_link_generic"); 1498 1499 for (i = 0; i < iterations; i++) { 1500 /* Some PHYs require the PHY_STATUS register to be read 1501 * twice due to the link bit being sticky. No harm doing 1502 * it across the board. 1503 */ 1504 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1505 if (ret_val) 1506 break; 1507 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 1508 if (ret_val) 1509 break; 1510 if (phy_status & MII_SR_LINK_STATUS) 1511 break; 1512 if (usec_interval >= 1000) 1513 msec_delay_irq(usec_interval/1000); 1514 else 1515 usec_delay(usec_interval); 1516 } 1517 1518 *success = (i < iterations) ? TRUE : FALSE; 1519 1520 return ret_val; 1521} 1522 1523/** 1524 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1525 * @hw - pointer to the HW structure 1526 * 1527 * Reads the PHY specific status register to retrieve the cable length 1528 * information. The cable length is determined by averaging the minimum and 1529 * maximum values to get the "average" cable length. The m88 PHY has four 1530 * possible cable length values, which are: 1531 * Register Value Cable Length 1532 * 0 < 50 meters 1533 * 1 50 - 80 meters 1534 * 2 80 - 110 meters 1535 * 3 110 - 140 meters 1536 * 4 > 140 meters 1537 **/ 1538s32 1539e1000_get_cable_length_m88(struct e1000_hw *hw) 1540{ 1541 struct e1000_phy_info *phy = &hw->phy; 1542 s32 ret_val; 1543 u16 phy_data, index; 1544 1545 DEBUGFUNC("e1000_get_cable_length_m88"); 1546 1547 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1548 if (ret_val) 1549 goto out; 1550 1551 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1552 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1553 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1554 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1555 1556 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1557 1558out: 1559 return ret_val; 1560} 1561 1562/** 1563 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1564 * @hw - pointer to the HW structure 1565 * 1566 * The automatic gain control (agc) normalizes the amplitude of the 1567 * received signal, adjusting for the attenuation produced by the 1568 * cable. By reading the AGC registers, which reperesent the 1569 * cobination of course and fine gain value, the value can be put 1570 * into a lookup table to obtain the approximate cable length 1571 * for each channel. 1572 **/ 1573s32 1574e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1575{ 1576 struct e1000_phy_info *phy = &hw->phy; 1577 s32 ret_val; 1578 u16 phy_data, i, agc_value = 0; 1579 u16 cur_agc_index, max_agc_index = 0; 1580 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1581 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1582 {IGP02E1000_PHY_AGC_A, 1583 IGP02E1000_PHY_AGC_B, 1584 IGP02E1000_PHY_AGC_C, 1585 IGP02E1000_PHY_AGC_D}; 1586 1587 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1588 1589 /* Read the AGC registers for all channels */ 1590 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1591 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 1592 if (ret_val) 1593 goto out; 1594 1595 /* Getting bits 15:9, which represent the combination of 1596 * course and fine gain values. The result is a number 1597 * that can be put into the lookup table to obtain the 1598 * approximate cable length. */ 1599 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1600 IGP02E1000_AGC_LENGTH_MASK; 1601 1602 /* Array index bound check. */ 1603 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1604 (cur_agc_index == 0)) { 1605 ret_val = -E1000_ERR_PHY; 1606 goto out; 1607 } 1608 1609 /* Remove min & max AGC values from calculation. */ 1610 if (e1000_igp_2_cable_length_table[min_agc_index] > 1611 e1000_igp_2_cable_length_table[cur_agc_index]) 1612 min_agc_index = cur_agc_index; 1613 if (e1000_igp_2_cable_length_table[max_agc_index] < 1614 e1000_igp_2_cable_length_table[cur_agc_index]) 1615 max_agc_index = cur_agc_index; 1616 1617 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1618 } 1619 1620 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1621 e1000_igp_2_cable_length_table[max_agc_index]); 1622 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1623 1624 /* Calculate cable length with the error range of +/- 10 meters. */ 1625 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1626 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1627 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1628 1629 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1630 1631out: 1632 return ret_val; 1633} 1634 1635/** 1636 * e1000_get_phy_info_m88 - Retrieve PHY information 1637 * @hw - pointer to the HW structure 1638 * 1639 * Valid for only copper links. Read the PHY status register (sticky read) 1640 * to verify that link is up. Read the PHY special control register to 1641 * determine the polarity and 10base-T extended distance. Read the PHY 1642 * special status register to determine MDI/MDIx and current speed. If 1643 * speed is 1000, then determine cable length, local and remote receiver. 1644 **/ 1645s32 1646e1000_get_phy_info_m88(struct e1000_hw *hw) 1647{ 1648 struct e1000_phy_info *phy = &hw->phy; 1649 s32 ret_val; 1650 u16 phy_data; 1651 boolean_t link; 1652 1653 DEBUGFUNC("e1000_get_phy_info_m88"); 1654 1655 if (hw->media_type != e1000_media_type_copper) { 1656 DEBUGOUT("Phy info is only valid for copper media\n"); 1657 ret_val = -E1000_ERR_CONFIG; 1658 goto out; 1659 } 1660 1661 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1662 if (ret_val) 1663 goto out; 1664 1665 if (!link) { 1666 DEBUGOUT("Phy info is only valid if link is up\n"); 1667 ret_val = -E1000_ERR_CONFIG; 1668 goto out; 1669 } 1670 1671 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1672 if (ret_val) 1673 goto out; 1674 1675 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1676 ? TRUE 1677 : FALSE; 1678 1679 ret_val = e1000_check_polarity_m88(hw); 1680 if (ret_val) 1681 goto out; 1682 1683 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1684 if (ret_val) 1685 goto out; 1686 1687 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 1688 1689 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1690 ret_val = e1000_get_cable_length(hw); 1691 if (ret_val) 1692 goto out; 1693 1694 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 1695 if (ret_val) 1696 goto out; 1697 1698 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1699 ? e1000_1000t_rx_status_ok 1700 : e1000_1000t_rx_status_not_ok; 1701 1702 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1703 ? e1000_1000t_rx_status_ok 1704 : e1000_1000t_rx_status_not_ok; 1705 } else { 1706 /* Set values to "undefined" */ 1707 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1708 phy->local_rx = e1000_1000t_rx_status_undefined; 1709 phy->remote_rx = e1000_1000t_rx_status_undefined; 1710 } 1711 1712out: 1713 return ret_val; 1714} 1715 1716/** 1717 * e1000_get_phy_info_igp - Retrieve igp PHY information 1718 * @hw - pointer to the HW structure 1719 * 1720 * Read PHY status to determine if link is up. If link is up, then 1721 * set/determine 10base-T extended distance and polarity correction. Read 1722 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1723 * determine on the cable length, local and remote receiver. 1724 **/ 1725s32 1726e1000_get_phy_info_igp(struct e1000_hw *hw) 1727{ 1728 struct e1000_phy_info *phy = &hw->phy; 1729 s32 ret_val; 1730 u16 data; 1731 boolean_t link; 1732 1733 DEBUGFUNC("e1000_get_phy_info_igp"); 1734 1735 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1736 if (ret_val) 1737 goto out; 1738 1739 if (!link) { 1740 DEBUGOUT("Phy info is only valid if link is up\n"); 1741 ret_val = -E1000_ERR_CONFIG; 1742 goto out; 1743 } 1744 1745 phy->polarity_correction = TRUE; 1746 1747 ret_val = e1000_check_polarity_igp(hw); 1748 if (ret_val) 1749 goto out; 1750 1751 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1752 if (ret_val) 1753 goto out; 1754 1755 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 1756 1757 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1758 IGP01E1000_PSSR_SPEED_1000MBPS) { 1759 ret_val = e1000_get_cable_length(hw); 1760 if (ret_val) 1761 goto out; 1762 1763 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &data); 1764 if (ret_val) 1765 goto out; 1766 1767 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1768 ? e1000_1000t_rx_status_ok 1769 : e1000_1000t_rx_status_not_ok; 1770 1771 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1772 ? e1000_1000t_rx_status_ok 1773 : e1000_1000t_rx_status_not_ok; 1774 } else { 1775 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1776 phy->local_rx = e1000_1000t_rx_status_undefined; 1777 phy->remote_rx = e1000_1000t_rx_status_undefined; 1778 } 1779 1780out: 1781 return ret_val; 1782} 1783 1784/** 1785 * e1000_phy_sw_reset_generic - PHY software reset 1786 * @hw - pointer to the HW structure 1787 * 1788 * Does a software reset of the PHY by reading the PHY control register and 1789 * setting/write the control register reset bit to the PHY. 1790 **/ 1791s32 1792e1000_phy_sw_reset_generic(struct e1000_hw *hw) 1793{ 1794 s32 ret_val; 1795 u16 phy_ctrl; 1796 1797 DEBUGFUNC("e1000_phy_sw_reset_generic"); 1798 1799 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 1800 if (ret_val) 1801 goto out; 1802 1803 phy_ctrl |= MII_CR_RESET; 1804 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 1805 if (ret_val) 1806 goto out; 1807 1808 usec_delay(1); 1809 1810out: 1811 return ret_val; 1812} 1813 1814/** 1815 * e1000_phy_hw_reset_generic - PHY hardware reset 1816 * @hw - pointer to the HW structure 1817 * 1818 * Verify the reset block is not blocking us from resetting. Acquire 1819 * semaphore (if necessary) and read/set/write the device control reset 1820 * bit in the PHY. Wait the appropriate delay time for the device to 1821 * reset and relase the semaphore (if necessary). 1822 **/ 1823s32 1824e1000_phy_hw_reset_generic(struct e1000_hw *hw) 1825{ 1826 struct e1000_phy_info *phy = &hw->phy; 1827 s32 ret_val; 1828 u32 ctrl; 1829 1830 DEBUGFUNC("e1000_phy_hw_reset_generic"); 1831 1832 ret_val = e1000_check_reset_block(hw); 1833 if (ret_val) { 1834 ret_val = E1000_SUCCESS; 1835 goto out; 1836 } 1837 1838 ret_val = e1000_acquire_phy(hw); 1839 if (ret_val) 1840 goto out; 1841 1842 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1843 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 1844 E1000_WRITE_FLUSH(hw); 1845 1846 usec_delay(phy->reset_delay_us); 1847 1848 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1849 E1000_WRITE_FLUSH(hw); 1850 1851 usec_delay(150); 1852 1853 e1000_release_phy(hw); 1854 1855 ret_val = e1000_get_phy_cfg_done(hw); 1856 1857out: 1858 return ret_val; 1859} 1860 1861/** 1862 * e1000_get_cfg_done_generic - Generic configuration done 1863 * @hw - pointer to the HW structure 1864 * 1865 * Generic function to wait 10 milli-seconds for configuration to complete 1866 * and return success. 1867 **/ 1868s32 1869e1000_get_cfg_done_generic(struct e1000_hw *hw) 1870{ 1871 DEBUGFUNC("e1000_get_cfg_done_generic"); 1872 1873 msec_delay_irq(10); 1874 1875 return E1000_SUCCESS; 1876} 1877 1878/* Internal function pointers */ 1879 1880/** 1881 * e1000_get_phy_cfg_done - Generic PHY configuration done 1882 * @hw - pointer to the HW structure 1883 * 1884 * Return success if silicon family did not implement a family specific 1885 * get_cfg_done function. 1886 **/ 1887s32 1888e1000_get_phy_cfg_done(struct e1000_hw *hw) 1889{ 1890 if (hw->func.get_cfg_done != NULL) 1891 return hw->func.get_cfg_done(hw); 1892 else 1893 return E1000_SUCCESS; 1894} 1895 1896/** 1897 * e1000_release_phy - Generic release PHY 1898 * @hw - pointer to the HW structure 1899 * 1900 * Return if silicon family does not require a semaphore when accessing the 1901 * PHY. 1902 **/ 1903void 1904e1000_release_phy(struct e1000_hw *hw) 1905{ 1906 if (hw->func.release_phy != NULL) 1907 hw->func.release_phy(hw); 1908} 1909 1910/** 1911 * e1000_acquire_phy - Generic acquire PHY 1912 * @hw - pointer to the HW structure 1913 * 1914 * Return success if silicon family does not require a semaphore when 1915 * accessing the PHY. 1916 **/ 1917s32 1918e1000_acquire_phy(struct e1000_hw *hw) 1919{ 1920 if (hw->func.acquire_phy != NULL) 1921 return hw->func.acquire_phy(hw); 1922 else 1923 return E1000_SUCCESS; 1924} 1925 1926/** 1927 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 1928 * @hw - pointer to the HW structure 1929 * 1930 * When the silicon family has not implemented a forced speed/duplex 1931 * function for the PHY, simply return E1000_SUCCESS. 1932 **/ 1933s32 1934e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1935{ 1936 if (hw->func.force_speed_duplex != NULL) 1937 return hw->func.force_speed_duplex(hw); 1938 else 1939 return E1000_SUCCESS; 1940} 1941 1942/** 1943 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 1944 * @hw - pointer to the HW structure 1945 * 1946 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 1947 **/ 1948s32 1949e1000_phy_init_script_igp3(struct e1000_hw *hw) 1950{ 1951 DEBUGOUT("Running IGP 3 PHY init script\n"); 1952 1953 /* PHY init IGP 3 */ 1954 /* Enable rise/fall, 10-mode work in class-A */ 1955 e1000_write_phy_reg(hw, 0x2F5B, 0x9018); 1956 /* Remove all caps from Replica path filter */ 1957 e1000_write_phy_reg(hw, 0x2F52, 0x0000); 1958 /* Bias trimming for ADC, AFE and Driver (Default) */ 1959 e1000_write_phy_reg(hw, 0x2FB1, 0x8B24); 1960 /* Increase Hybrid poly bias */ 1961 e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0); 1962 /* Add 4% to TX amplitude in Giga mode */ 1963 e1000_write_phy_reg(hw, 0x2010, 0x10B0); 1964 /* Disable trimming (TTT) */ 1965 e1000_write_phy_reg(hw, 0x2011, 0x0000); 1966 /* Poly DC correction to 94.6% + 2% for all channels */ 1967 e1000_write_phy_reg(hw, 0x20DD, 0x249A); 1968 /* ABS DC correction to 95.9% */ 1969 e1000_write_phy_reg(hw, 0x20DE, 0x00D3); 1970 /* BG temp curve trim */ 1971 e1000_write_phy_reg(hw, 0x28B4, 0x04CE); 1972 /* Increasing ADC OPAMP stage 1 currents to max */ 1973 e1000_write_phy_reg(hw, 0x2F70, 0x29E4); 1974 /* Force 1000 ( required for enabling PHY regs configuration) */ 1975 e1000_write_phy_reg(hw, 0x0000, 0x0140); 1976 /* Set upd_freq to 6 */ 1977 e1000_write_phy_reg(hw, 0x1F30, 0x1606); 1978 /* Disable NPDFE */ 1979 e1000_write_phy_reg(hw, 0x1F31, 0xB814); 1980 /* Disable adaptive fixed FFE (Default) */ 1981 e1000_write_phy_reg(hw, 0x1F35, 0x002A); 1982 /* Enable FFE hysteresis */ 1983 e1000_write_phy_reg(hw, 0x1F3E, 0x0067); 1984 /* Fixed FFE for short cable lengths */ 1985 e1000_write_phy_reg(hw, 0x1F54, 0x0065); 1986 /* Fixed FFE for medium cable lengths */ 1987 e1000_write_phy_reg(hw, 0x1F55, 0x002A); 1988 /* Fixed FFE for long cable lengths */ 1989 e1000_write_phy_reg(hw, 0x1F56, 0x002A); 1990 /* Enable Adaptive Clip Threshold */ 1991 e1000_write_phy_reg(hw, 0x1F72, 0x3FB0); 1992 /* AHT reset limit to 1 */ 1993 e1000_write_phy_reg(hw, 0x1F76, 0xC0FF); 1994 /* Set AHT master delay to 127 msec */ 1995 e1000_write_phy_reg(hw, 0x1F77, 0x1DEC); 1996 /* Set scan bits for AHT */ 1997 e1000_write_phy_reg(hw, 0x1F78, 0xF9EF); 1998 /* Set AHT Preset bits */ 1999 e1000_write_phy_reg(hw, 0x1F79, 0x0210); 2000 /* Change integ_factor of channel A to 3 */ 2001 e1000_write_phy_reg(hw, 0x1895, 0x0003); 2002 /* Change prop_factor of channels BCD to 8 */ 2003 e1000_write_phy_reg(hw, 0x1796, 0x0008); 2004 /* Change cg_icount + enable integbp for channels BCD */ 2005 e1000_write_phy_reg(hw, 0x1798, 0xD008); 2006 /* Change cg_icount + enable integbp + change prop_factor_master 2007 * to 8 for channel A 2008 */ 2009 e1000_write_phy_reg(hw, 0x1898, 0xD918); 2010 /* Disable AHT in Slave mode on channel A */ 2011 e1000_write_phy_reg(hw, 0x187A, 0x0800); 2012 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2013 * Enable SPD+B2B 2014 */ 2015 e1000_write_phy_reg(hw, 0x0019, 0x008D); 2016 /* Enable restart AN on an1000_dis change */ 2017 e1000_write_phy_reg(hw, 0x001B, 0x2080); 2018 /* Enable wh_fifo read clock in 10/100 modes */ 2019 e1000_write_phy_reg(hw, 0x0014, 0x0045); 2020 /* Restart AN, Speed selection is 1000 */ 2021 e1000_write_phy_reg(hw, 0x0000, 0x1340); 2022 2023 return E1000_SUCCESS; 2024} 2025