1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: releng/11.0/sys/dev/e1000/e1000_ich8lan.c 304493 2016-08-19 19:02:18Z sbruno $*/ 34 35/* 82562G 10/100 Network Connection 36 * 82562G-2 10/100 Network Connection 37 * 82562GT 10/100 Network Connection 38 * 82562GT-2 10/100 Network Connection 39 * 82562V 10/100 Network Connection 40 * 82562V-2 10/100 Network Connection 41 * 82566DC-2 Gigabit Network Connection 42 * 82566DC Gigabit Network Connection 43 * 82566DM-2 Gigabit Network Connection 44 * 82566DM Gigabit Network Connection 45 * 82566MC Gigabit Network Connection 46 * 82566MM Gigabit Network Connection 47 * 82567LM Gigabit Network Connection 48 * 82567LF Gigabit Network Connection 49 * 82567V Gigabit Network Connection 50 * 82567LM-2 Gigabit Network Connection 51 * 82567LF-2 Gigabit Network Connection 52 * 82567V-2 Gigabit Network Connection 53 * 82567LF-3 Gigabit Network Connection 54 * 82567LM-3 Gigabit Network Connection 55 * 82567LM-4 Gigabit Network Connection 56 * 82577LM Gigabit Network Connection 57 * 82577LC Gigabit Network Connection 58 * 82578DM Gigabit Network Connection 59 * 82578DC Gigabit Network Connection 60 * 82579LM Gigabit Network Connection 61 * 82579V Gigabit Network Connection 62 * Ethernet Connection I217-LM 63 * Ethernet Connection I217-V 64 * Ethernet Connection I218-V 65 * Ethernet Connection I218-LM 66 * Ethernet Connection (2) I218-LM 67 * Ethernet Connection (2) I218-V 68 * Ethernet Connection (3) I218-LM 69 * Ethernet Connection (3) I218-V 70 */ 71 72#include "e1000_api.h" 73 74static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 75static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 76static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 77static void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 78static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 79static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 80static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 81static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 82static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 83static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 84 u8 *mc_addr_list, 85 u32 mc_addr_count); 86static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 87static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 88static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 89static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 90 bool active); 91static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 92 bool active); 93static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 94 u16 words, u16 *data); 95static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 96 u16 *data); 97static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 98 u16 words, u16 *data); 99static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 100static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 101static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw); 102static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 103 u16 *data); 104static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 105static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 106static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 107static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 108static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 109static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 110static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 111static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 112 u16 *speed, u16 *duplex); 113static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 114static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 115static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 116static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 117static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 118static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 119static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 120static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 121static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 122static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 123static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 124static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 125static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 126 u32 offset, u8 *data); 127static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 128 u8 size, u16 *data); 129static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 130 u32 *data); 131static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 132 u32 offset, u32 *data); 133static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 134 u32 offset, u32 data); 135static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 136 u32 offset, u32 dword); 137static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 138 u32 offset, u16 *data); 139static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 140 u32 offset, u8 byte); 141static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 142static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 143static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 144static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 145static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 146static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 147static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); 148 149/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 150/* Offset 04h HSFSTS */ 151union ich8_hws_flash_status { 152 struct ich8_hsfsts { 153 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 154 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 155 u16 dael:1; /* bit 2 Direct Access error Log */ 156 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 157 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 158 u16 reserved1:2; /* bit 13:6 Reserved */ 159 u16 reserved2:6; /* bit 13:6 Reserved */ 160 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 161 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 162 } hsf_status; 163 u16 regval; 164}; 165 166/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 167/* Offset 06h FLCTL */ 168union ich8_hws_flash_ctrl { 169 struct ich8_hsflctl { 170 u16 flcgo:1; /* 0 Flash Cycle Go */ 171 u16 flcycle:2; /* 2:1 Flash Cycle */ 172 u16 reserved:5; /* 7:3 Reserved */ 173 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 174 u16 flockdn:6; /* 15:10 Reserved */ 175 } hsf_ctrl; 176 u16 regval; 177}; 178 179/* ICH Flash Region Access Permissions */ 180union ich8_hws_flash_regacc { 181 struct ich8_flracc { 182 u32 grra:8; /* 0:7 GbE region Read Access */ 183 u32 grwa:8; /* 8:15 GbE region Write Access */ 184 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 185 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 186 } hsf_flregacc; 187 u16 regval; 188}; 189 190/** 191 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 192 * @hw: pointer to the HW structure 193 * 194 * Test access to the PHY registers by reading the PHY ID registers. If 195 * the PHY ID is already known (e.g. resume path) compare it with known ID, 196 * otherwise assume the read PHY ID is correct if it is valid. 197 * 198 * Assumes the sw/fw/hw semaphore is already acquired. 199 **/ 200static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 201{ 202 u16 phy_reg = 0; 203 u32 phy_id = 0; 204 s32 ret_val = 0; 205 u16 retry_count; 206 u32 mac_reg = 0; 207 208 for (retry_count = 0; retry_count < 2; retry_count++) { 209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); 210 if (ret_val || (phy_reg == 0xFFFF)) 211 continue; 212 phy_id = (u32)(phy_reg << 16); 213 214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); 215 if (ret_val || (phy_reg == 0xFFFF)) { 216 phy_id = 0; 217 continue; 218 } 219 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 220 break; 221 } 222 223 if (hw->phy.id) { 224 if (hw->phy.id == phy_id) 225 goto out; 226 } else if (phy_id) { 227 hw->phy.id = phy_id; 228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 229 goto out; 230 } 231 232 /* In case the PHY needs to be in mdio slow mode, 233 * set slow mode and try to get the PHY id again. 234 */ 235 if (hw->mac.type < e1000_pch_lpt) { 236 hw->phy.ops.release(hw); 237 ret_val = e1000_set_mdio_slow_mode_hv(hw); 238 if (!ret_val) 239 ret_val = e1000_get_phy_id(hw); 240 hw->phy.ops.acquire(hw); 241 } 242 243 if (ret_val) 244 return FALSE; 245out: 246 if ((hw->mac.type == e1000_pch_lpt) || 247 (hw->mac.type == e1000_pch_spt)) { 248 /* Only unforce SMBus if ME is not active */ 249 if (!(E1000_READ_REG(hw, E1000_FWSM) & 250 E1000_ICH_FWSM_FW_VALID)) { 251 /* Unforce SMBus mode in PHY */ 252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); 253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); 255 256 /* Unforce SMBus mode in MAC */ 257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 260 } 261 } 262 263 return TRUE; 264} 265 266/** 267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 268 * @hw: pointer to the HW structure 269 * 270 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 271 * used to reset the PHY to a quiescent state when necessary. 272 **/ 273static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 274{ 275 u32 mac_reg; 276 277 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 278 279 /* Set Phy Config Counter to 50msec */ 280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 281 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 282 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); 284 285 /* Toggle LANPHYPC Value bit */ 286 mac_reg = E1000_READ_REG(hw, E1000_CTRL); 287 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 288 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 290 E1000_WRITE_FLUSH(hw); 291 msec_delay(1); 292 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); 294 E1000_WRITE_FLUSH(hw); 295 296 if (hw->mac.type < e1000_pch_lpt) { 297 msec_delay(50); 298 } else { 299 u16 count = 20; 300 301 do { 302 msec_delay(5); 303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & 304 E1000_CTRL_EXT_LPCD) && count--); 305 306 msec_delay(30); 307 } 308} 309 310/** 311 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 312 * @hw: pointer to the HW structure 313 * 314 * Workarounds/flow necessary for PHY initialization during driver load 315 * and resume paths. 316 **/ 317static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 318{ 319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); 320 s32 ret_val; 321 322 DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); 323 324 /* Gate automatic PHY configuration by hardware on managed and 325 * non-managed 82579 and newer adapters. 326 */ 327 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 328 329 /* It is not possible to be certain of the current state of ULP 330 * so forcibly disable it. 331 */ 332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 333 e1000_disable_ulp_lpt_lp(hw, TRUE); 334 335 ret_val = hw->phy.ops.acquire(hw); 336 if (ret_val) { 337 DEBUGOUT("Failed to initialize PHY flow\n"); 338 goto out; 339 } 340 341 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 342 * inaccessible and resetting the PHY is not blocked, toggle the 343 * LANPHYPC Value bit to force the interconnect to PCIe mode. 344 */ 345 switch (hw->mac.type) { 346 case e1000_pch_lpt: 347 case e1000_pch_spt: 348 if (e1000_phy_is_accessible_pchlan(hw)) 349 break; 350 351 /* Before toggling LANPHYPC, see if PHY is accessible by 352 * forcing MAC to SMBus mode first. 353 */ 354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 355 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 357 358 /* Wait 50 milliseconds for MAC to finish any retries 359 * that it might be trying to perform from previous 360 * attempts to acknowledge any phy read requests. 361 */ 362 msec_delay(50); 363 364 /* fall-through */ 365 case e1000_pch2lan: 366 if (e1000_phy_is_accessible_pchlan(hw)) 367 break; 368 369 /* fall-through */ 370 case e1000_pchlan: 371 if ((hw->mac.type == e1000_pchlan) && 372 (fwsm & E1000_ICH_FWSM_FW_VALID)) 373 break; 374 375 if (hw->phy.ops.check_reset_block(hw)) { 376 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); 377 ret_val = -E1000_ERR_PHY; 378 break; 379 } 380 381 /* Toggle LANPHYPC Value bit */ 382 e1000_toggle_lanphypc_pch_lpt(hw); 383 if (hw->mac.type >= e1000_pch_lpt) { 384 if (e1000_phy_is_accessible_pchlan(hw)) 385 break; 386 387 /* Toggling LANPHYPC brings the PHY out of SMBus mode 388 * so ensure that the MAC is also out of SMBus mode 389 */ 390 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 391 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 392 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 393 394 if (e1000_phy_is_accessible_pchlan(hw)) 395 break; 396 397 ret_val = -E1000_ERR_PHY; 398 } 399 break; 400 default: 401 break; 402 } 403 404 hw->phy.ops.release(hw); 405 if (!ret_val) { 406 407 /* Check to see if able to reset PHY. Print error if not */ 408 if (hw->phy.ops.check_reset_block(hw)) { 409 ERROR_REPORT("Reset blocked by ME\n"); 410 goto out; 411 } 412 413 /* Reset the PHY before any access to it. Doing so, ensures 414 * that the PHY is in a known good state before we read/write 415 * PHY registers. The generic reset is sufficient here, 416 * because we haven't determined the PHY type yet. 417 */ 418 ret_val = e1000_phy_hw_reset_generic(hw); 419 if (ret_val) 420 goto out; 421 422 /* On a successful reset, possibly need to wait for the PHY 423 * to quiesce to an accessible state before returning control 424 * to the calling function. If the PHY does not quiesce, then 425 * return E1000E_BLK_PHY_RESET, as this is the condition that 426 * the PHY is in. 427 */ 428 ret_val = hw->phy.ops.check_reset_block(hw); 429 if (ret_val) 430 ERROR_REPORT("ME blocked access to PHY after reset\n"); 431 } 432 433out: 434 /* Ungate automatic PHY configuration on non-managed 82579 */ 435 if ((hw->mac.type == e1000_pch2lan) && 436 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 437 msec_delay(10); 438 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 439 } 440 441 return ret_val; 442} 443 444/** 445 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 446 * @hw: pointer to the HW structure 447 * 448 * Initialize family-specific PHY parameters and function pointers. 449 **/ 450static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 451{ 452 struct e1000_phy_info *phy = &hw->phy; 453 s32 ret_val; 454 455 DEBUGFUNC("e1000_init_phy_params_pchlan"); 456 457 phy->addr = 1; 458 phy->reset_delay_us = 100; 459 460 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 461 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 462 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 463 phy->ops.set_page = e1000_set_page_igp; 464 phy->ops.read_reg = e1000_read_phy_reg_hv; 465 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 466 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 467 phy->ops.release = e1000_release_swflag_ich8lan; 468 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 469 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 470 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 471 phy->ops.write_reg = e1000_write_phy_reg_hv; 472 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 473 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 474 phy->ops.power_up = e1000_power_up_phy_copper; 475 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 476 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 477 478 phy->id = e1000_phy_unknown; 479 480 ret_val = e1000_init_phy_workarounds_pchlan(hw); 481 if (ret_val) 482 return ret_val; 483 484 if (phy->id == e1000_phy_unknown) 485 switch (hw->mac.type) { 486 default: 487 ret_val = e1000_get_phy_id(hw); 488 if (ret_val) 489 return ret_val; 490 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 491 break; 492 /* fall-through */ 493 case e1000_pch2lan: 494 case e1000_pch_lpt: 495 case e1000_pch_spt: 496 /* In case the PHY needs to be in mdio slow mode, 497 * set slow mode and try to get the PHY id again. 498 */ 499 ret_val = e1000_set_mdio_slow_mode_hv(hw); 500 if (ret_val) 501 return ret_val; 502 ret_val = e1000_get_phy_id(hw); 503 if (ret_val) 504 return ret_val; 505 break; 506 } 507 phy->type = e1000_get_phy_type_from_id(phy->id); 508 509 switch (phy->type) { 510 case e1000_phy_82577: 511 case e1000_phy_82579: 512 case e1000_phy_i217: 513 phy->ops.check_polarity = e1000_check_polarity_82577; 514 phy->ops.force_speed_duplex = 515 e1000_phy_force_speed_duplex_82577; 516 phy->ops.get_cable_length = e1000_get_cable_length_82577; 517 phy->ops.get_info = e1000_get_phy_info_82577; 518 phy->ops.commit = e1000_phy_sw_reset_generic; 519 break; 520 case e1000_phy_82578: 521 phy->ops.check_polarity = e1000_check_polarity_m88; 522 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 523 phy->ops.get_cable_length = e1000_get_cable_length_m88; 524 phy->ops.get_info = e1000_get_phy_info_m88; 525 break; 526 default: 527 ret_val = -E1000_ERR_PHY; 528 break; 529 } 530 531 return ret_val; 532} 533 534/** 535 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 536 * @hw: pointer to the HW structure 537 * 538 * Initialize family-specific PHY parameters and function pointers. 539 **/ 540static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 541{ 542 struct e1000_phy_info *phy = &hw->phy; 543 s32 ret_val; 544 u16 i = 0; 545 546 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 547 548 phy->addr = 1; 549 phy->reset_delay_us = 100; 550 551 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 552 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 553 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 554 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 555 phy->ops.read_reg = e1000_read_phy_reg_igp; 556 phy->ops.release = e1000_release_swflag_ich8lan; 557 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 558 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 559 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 560 phy->ops.write_reg = e1000_write_phy_reg_igp; 561 phy->ops.power_up = e1000_power_up_phy_copper; 562 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 563 564 /* We may need to do this twice - once for IGP and if that fails, 565 * we'll set BM func pointers and try again 566 */ 567 ret_val = e1000_determine_phy_address(hw); 568 if (ret_val) { 569 phy->ops.write_reg = e1000_write_phy_reg_bm; 570 phy->ops.read_reg = e1000_read_phy_reg_bm; 571 ret_val = e1000_determine_phy_address(hw); 572 if (ret_val) { 573 DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 574 return ret_val; 575 } 576 } 577 578 phy->id = 0; 579 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 580 (i++ < 100)) { 581 msec_delay(1); 582 ret_val = e1000_get_phy_id(hw); 583 if (ret_val) 584 return ret_val; 585 } 586 587 /* Verify phy id */ 588 switch (phy->id) { 589 case IGP03E1000_E_PHY_ID: 590 phy->type = e1000_phy_igp_3; 591 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 592 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 593 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 594 phy->ops.get_info = e1000_get_phy_info_igp; 595 phy->ops.check_polarity = e1000_check_polarity_igp; 596 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 597 break; 598 case IFE_E_PHY_ID: 599 case IFE_PLUS_E_PHY_ID: 600 case IFE_C_E_PHY_ID: 601 phy->type = e1000_phy_ife; 602 phy->autoneg_mask = E1000_ALL_NOT_GIG; 603 phy->ops.get_info = e1000_get_phy_info_ife; 604 phy->ops.check_polarity = e1000_check_polarity_ife; 605 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 606 break; 607 case BME1000_E_PHY_ID: 608 phy->type = e1000_phy_bm; 609 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 610 phy->ops.read_reg = e1000_read_phy_reg_bm; 611 phy->ops.write_reg = e1000_write_phy_reg_bm; 612 phy->ops.commit = e1000_phy_sw_reset_generic; 613 phy->ops.get_info = e1000_get_phy_info_m88; 614 phy->ops.check_polarity = e1000_check_polarity_m88; 615 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 616 break; 617 default: 618 return -E1000_ERR_PHY; 619 break; 620 } 621 622 return E1000_SUCCESS; 623} 624 625/** 626 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 627 * @hw: pointer to the HW structure 628 * 629 * Initialize family-specific NVM parameters and function 630 * pointers. 631 **/ 632static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 633{ 634 struct e1000_nvm_info *nvm = &hw->nvm; 635 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 636 u32 gfpreg, sector_base_addr, sector_end_addr; 637 u16 i; 638 u32 nvm_size; 639 640 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 641 642 nvm->type = e1000_nvm_flash_sw; 643 644 if (hw->mac.type == e1000_pch_spt) { 645 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 646 * STRAP register. This is because in SPT the GbE Flash region 647 * is no longer accessed through the flash registers. Instead, 648 * the mechanism has changed, and the Flash region access 649 * registers are now implemented in GbE memory space. 650 */ 651 nvm->flash_base_addr = 0; 652 nvm_size = 653 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1) 654 * NVM_SIZE_MULTIPLIER; 655 nvm->flash_bank_size = nvm_size / 2; 656 /* Adjust to word count */ 657 nvm->flash_bank_size /= sizeof(u16); 658 /* Set the base address for flash register access */ 659 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 660 } else { 661 /* Can't read flash registers if register set isn't mapped. */ 662 if (!hw->flash_address) { 663 DEBUGOUT("ERROR: Flash registers not mapped\n"); 664 return -E1000_ERR_CONFIG; 665 } 666 667 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 668 669 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 670 * Add 1 to sector_end_addr since this sector is included in 671 * the overall size. 672 */ 673 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 674 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 675 676 /* flash_base_addr is byte-aligned */ 677 nvm->flash_base_addr = sector_base_addr 678 << FLASH_SECTOR_ADDR_SHIFT; 679 680 /* find total size of the NVM, then cut in half since the total 681 * size represents two separate NVM banks. 682 */ 683 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 684 << FLASH_SECTOR_ADDR_SHIFT); 685 nvm->flash_bank_size /= 2; 686 /* Adjust to word count */ 687 nvm->flash_bank_size /= sizeof(u16); 688 } 689 690 nvm->word_size = E1000_SHADOW_RAM_WORDS; 691 692 /* Clear shadow ram */ 693 for (i = 0; i < nvm->word_size; i++) { 694 dev_spec->shadow_ram[i].modified = FALSE; 695 dev_spec->shadow_ram[i].value = 0xFFFF; 696 } 697 698 E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 699 E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 700 701 /* Function Pointers */ 702 nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 703 nvm->ops.release = e1000_release_nvm_ich8lan; 704 if (hw->mac.type == e1000_pch_spt) { 705 nvm->ops.read = e1000_read_nvm_spt; 706 nvm->ops.update = e1000_update_nvm_checksum_spt; 707 } else { 708 nvm->ops.read = e1000_read_nvm_ich8lan; 709 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 710 } 711 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 712 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 713 nvm->ops.write = e1000_write_nvm_ich8lan; 714 715 return E1000_SUCCESS; 716} 717 718/** 719 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 720 * @hw: pointer to the HW structure 721 * 722 * Initialize family-specific MAC parameters and function 723 * pointers. 724 **/ 725static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 726{ 727 struct e1000_mac_info *mac = &hw->mac; 728 729 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 730 731 /* Set media type function pointer */ 732 hw->phy.media_type = e1000_media_type_copper; 733 734 /* Set mta register count */ 735 mac->mta_reg_count = 32; 736 /* Set rar entry count */ 737 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 738 if (mac->type == e1000_ich8lan) 739 mac->rar_entry_count--; 740 /* Set if part includes ASF firmware */ 741 mac->asf_firmware_present = TRUE; 742 /* FWSM register */ 743 mac->has_fwsm = TRUE; 744 /* ARC subsystem not supported */ 745 mac->arc_subsystem_valid = FALSE; 746 /* Adaptive IFS supported */ 747 mac->adaptive_ifs = TRUE; 748 749 /* Function pointers */ 750 751 /* bus type/speed/width */ 752 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 753 /* function id */ 754 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 755 /* reset */ 756 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 757 /* hw initialization */ 758 mac->ops.init_hw = e1000_init_hw_ich8lan; 759 /* link setup */ 760 mac->ops.setup_link = e1000_setup_link_ich8lan; 761 /* physical interface setup */ 762 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 763 /* check for link */ 764 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 765 /* link info */ 766 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 767 /* multicast address update */ 768 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 769 /* clear hardware counters */ 770 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 771 772 /* LED and other operations */ 773 switch (mac->type) { 774 case e1000_ich8lan: 775 case e1000_ich9lan: 776 case e1000_ich10lan: 777 /* check management mode */ 778 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 779 /* ID LED init */ 780 mac->ops.id_led_init = e1000_id_led_init_generic; 781 /* blink LED */ 782 mac->ops.blink_led = e1000_blink_led_generic; 783 /* setup LED */ 784 mac->ops.setup_led = e1000_setup_led_generic; 785 /* cleanup LED */ 786 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 787 /* turn on/off LED */ 788 mac->ops.led_on = e1000_led_on_ich8lan; 789 mac->ops.led_off = e1000_led_off_ich8lan; 790 break; 791 case e1000_pch2lan: 792 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 793 mac->ops.rar_set = e1000_rar_set_pch2lan; 794 /* fall-through */ 795 case e1000_pch_lpt: 796 case e1000_pch_spt: 797 /* multicast address update for pch2 */ 798 mac->ops.update_mc_addr_list = 799 e1000_update_mc_addr_list_pch2lan; 800 /* fall-through */ 801 case e1000_pchlan: 802 /* check management mode */ 803 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 804 /* ID LED init */ 805 mac->ops.id_led_init = e1000_id_led_init_pchlan; 806 /* setup LED */ 807 mac->ops.setup_led = e1000_setup_led_pchlan; 808 /* cleanup LED */ 809 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 810 /* turn on/off LED */ 811 mac->ops.led_on = e1000_led_on_pchlan; 812 mac->ops.led_off = e1000_led_off_pchlan; 813 break; 814 default: 815 break; 816 } 817 818 if ((mac->type == e1000_pch_lpt) || 819 (mac->type == e1000_pch_spt)) { 820 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 821 mac->ops.rar_set = e1000_rar_set_pch_lpt; 822 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; 823 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; 824 } 825 826 /* Enable PCS Lock-loss workaround for ICH8 */ 827 if (mac->type == e1000_ich8lan) 828 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 829 830 return E1000_SUCCESS; 831} 832 833/** 834 * __e1000_access_emi_reg_locked - Read/write EMI register 835 * @hw: pointer to the HW structure 836 * @addr: EMI address to program 837 * @data: pointer to value to read/write from/to the EMI address 838 * @read: boolean flag to indicate read or write 839 * 840 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 841 **/ 842static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 843 u16 *data, bool read) 844{ 845 s32 ret_val; 846 847 DEBUGFUNC("__e1000_access_emi_reg_locked"); 848 849 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); 850 if (ret_val) 851 return ret_val; 852 853 if (read) 854 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, 855 data); 856 else 857 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 858 *data); 859 860 return ret_val; 861} 862 863/** 864 * e1000_read_emi_reg_locked - Read Extended Management Interface register 865 * @hw: pointer to the HW structure 866 * @addr: EMI address to program 867 * @data: value to be read from the EMI address 868 * 869 * Assumes the SW/FW/HW Semaphore is already acquired. 870 **/ 871s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 872{ 873 DEBUGFUNC("e1000_read_emi_reg_locked"); 874 875 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); 876} 877 878/** 879 * e1000_write_emi_reg_locked - Write Extended Management Interface register 880 * @hw: pointer to the HW structure 881 * @addr: EMI address to program 882 * @data: value to be written to the EMI address 883 * 884 * Assumes the SW/FW/HW Semaphore is already acquired. 885 **/ 886s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 887{ 888 DEBUGFUNC("e1000_read_emi_reg_locked"); 889 890 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); 891} 892 893/** 894 * e1000_set_eee_pchlan - Enable/disable EEE support 895 * @hw: pointer to the HW structure 896 * 897 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 898 * the link and the EEE capabilities of the link partner. The LPI Control 899 * register bits will remain set only if/when link is up. 900 * 901 * EEE LPI must not be asserted earlier than one second after link is up. 902 * On 82579, EEE LPI should not be enabled until such time otherwise there 903 * can be link issues with some switches. Other devices can have EEE LPI 904 * enabled immediately upon link up since they have a timer in hardware which 905 * prevents LPI from being asserted too early. 906 **/ 907s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 908{ 909 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 910 s32 ret_val; 911 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 912 913 DEBUGFUNC("e1000_set_eee_pchlan"); 914 915 switch (hw->phy.type) { 916 case e1000_phy_82579: 917 lpa = I82579_EEE_LP_ABILITY; 918 pcs_status = I82579_EEE_PCS_STATUS; 919 adv_addr = I82579_EEE_ADVERTISEMENT; 920 break; 921 case e1000_phy_i217: 922 lpa = I217_EEE_LP_ABILITY; 923 pcs_status = I217_EEE_PCS_STATUS; 924 adv_addr = I217_EEE_ADVERTISEMENT; 925 break; 926 default: 927 return E1000_SUCCESS; 928 } 929 930 ret_val = hw->phy.ops.acquire(hw); 931 if (ret_val) 932 return ret_val; 933 934 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 935 if (ret_val) 936 goto release; 937 938 /* Clear bits that enable EEE in various speeds */ 939 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 940 941 /* Enable EEE if not disabled by user */ 942 if (!dev_spec->eee_disable) { 943 /* Save off link partner's EEE ability */ 944 ret_val = e1000_read_emi_reg_locked(hw, lpa, 945 &dev_spec->eee_lp_ability); 946 if (ret_val) 947 goto release; 948 949 /* Read EEE advertisement */ 950 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 951 if (ret_val) 952 goto release; 953 954 /* Enable EEE only for speeds in which the link partner is 955 * EEE capable and for which we advertise EEE. 956 */ 957 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 958 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 959 960 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 961 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); 962 if (data & NWAY_LPAR_100TX_FD_CAPS) 963 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 964 else 965 /* EEE is not supported in 100Half, so ignore 966 * partner's EEE in 100 ability if full-duplex 967 * is not advertised. 968 */ 969 dev_spec->eee_lp_ability &= 970 ~I82579_EEE_100_SUPPORTED; 971 } 972 } 973 974 if (hw->phy.type == e1000_phy_82579) { 975 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 976 &data); 977 if (ret_val) 978 goto release; 979 980 data &= ~I82579_LPI_100_PLL_SHUT; 981 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 982 data); 983 } 984 985 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 986 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 987 if (ret_val) 988 goto release; 989 990 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 991release: 992 hw->phy.ops.release(hw); 993 994 return ret_val; 995} 996 997/** 998 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 999 * @hw: pointer to the HW structure 1000 * @link: link up bool flag 1001 * 1002 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 1003 * preventing further DMA write requests. Workaround the issue by disabling 1004 * the de-assertion of the clock request when in 1Gpbs mode. 1005 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 1006 * speeds in order to avoid Tx hangs. 1007 **/ 1008static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 1009{ 1010 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1011 u32 status = E1000_READ_REG(hw, E1000_STATUS); 1012 s32 ret_val = E1000_SUCCESS; 1013 u16 reg; 1014 1015 if (link && (status & E1000_STATUS_SPEED_1000)) { 1016 ret_val = hw->phy.ops.acquire(hw); 1017 if (ret_val) 1018 return ret_val; 1019 1020 ret_val = 1021 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1022 ®); 1023 if (ret_val) 1024 goto release; 1025 1026 ret_val = 1027 e1000_write_kmrn_reg_locked(hw, 1028 E1000_KMRNCTRLSTA_K1_CONFIG, 1029 reg & 1030 ~E1000_KMRNCTRLSTA_K1_ENABLE); 1031 if (ret_val) 1032 goto release; 1033 1034 usec_delay(10); 1035 1036 E1000_WRITE_REG(hw, E1000_FEXTNVM6, 1037 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1038 1039 ret_val = 1040 e1000_write_kmrn_reg_locked(hw, 1041 E1000_KMRNCTRLSTA_K1_CONFIG, 1042 reg); 1043release: 1044 hw->phy.ops.release(hw); 1045 } else { 1046 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1047 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1048 1049 if ((hw->phy.revision > 5) || !link || 1050 ((status & E1000_STATUS_SPEED_100) && 1051 (status & E1000_STATUS_FD))) 1052 goto update_fextnvm6; 1053 1054 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); 1055 if (ret_val) 1056 return ret_val; 1057 1058 /* Clear link status transmit timeout */ 1059 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1060 1061 if (status & E1000_STATUS_SPEED_100) { 1062 /* Set inband Tx timeout to 5x10us for 100Half */ 1063 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1064 1065 /* Do not extend the K1 entry latency for 100Half */ 1066 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1067 } else { 1068 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1069 reg |= 50 << 1070 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1071 1072 /* Extend the K1 entry latency for 10 Mbps */ 1073 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1074 } 1075 1076 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); 1077 if (ret_val) 1078 return ret_val; 1079 1080update_fextnvm6: 1081 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1082 } 1083 1084 return ret_val; 1085} 1086 1087static u64 e1000_ltr2ns(u16 ltr) 1088{ 1089 u32 value, scale; 1090 1091 /* Determine the latency in nsec based on the LTR value & scale */ 1092 value = ltr & E1000_LTRV_VALUE_MASK; 1093 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; 1094 1095 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); 1096} 1097 1098/** 1099 * e1000_platform_pm_pch_lpt - Set platform power management values 1100 * @hw: pointer to the HW structure 1101 * @link: bool indicating link status 1102 * 1103 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1104 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1105 * when link is up (which must not exceed the maximum latency supported 1106 * by the platform), otherwise specify there is no LTR requirement. 1107 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop 1108 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1109 * Capability register set, on this device LTR is set by writing the 1110 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1111 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1112 * message to the PMC. 1113 * 1114 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) 1115 * high-water mark. 1116 **/ 1117static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1118{ 1119 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1120 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1121 u16 lat_enc = 0; /* latency encoded */ 1122 s32 obff_hwm = 0; 1123 1124 DEBUGFUNC("e1000_platform_pm_pch_lpt"); 1125 1126 if (link) { 1127 u16 speed, duplex, scale = 0; 1128 u16 max_snoop, max_nosnoop; 1129 u16 max_ltr_enc; /* max LTR latency encoded */ 1130 s64 lat_ns; 1131 s64 value; 1132 u32 rxa; 1133 1134 if (!hw->mac.max_frame_size) { 1135 DEBUGOUT("max_frame_size not set.\n"); 1136 return -E1000_ERR_CONFIG; 1137 } 1138 1139 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1140 if (!speed) { 1141 DEBUGOUT("Speed not set.\n"); 1142 return -E1000_ERR_CONFIG; 1143 } 1144 1145 /* Rx Packet Buffer Allocation size (KB) */ 1146 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; 1147 1148 /* Determine the maximum latency tolerated by the device. 1149 * 1150 * Per the PCIe spec, the tolerated latencies are encoded as 1151 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1152 * a 10-bit value (0-1023) to provide a range from 1 ns to 1153 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1154 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1155 */ 1156 lat_ns = ((s64)rxa * 1024 - 1157 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; 1158 if (lat_ns < 0) 1159 lat_ns = 0; 1160 else 1161 lat_ns /= speed; 1162 value = lat_ns; 1163 1164 while (value > E1000_LTRV_VALUE_MASK) { 1165 scale++; 1166 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); 1167 } 1168 if (scale > E1000_LTRV_SCALE_MAX) { 1169 DEBUGOUT1("Invalid LTR latency scale %d\n", scale); 1170 return -E1000_ERR_CONFIG; 1171 } 1172 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); 1173 1174 /* Determine the maximum latency tolerated by the platform */ 1175 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); 1176 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1177 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); 1178 1179 if (lat_enc > max_ltr_enc) { 1180 lat_enc = max_ltr_enc; 1181 lat_ns = e1000_ltr2ns(max_ltr_enc); 1182 } 1183 1184 if (lat_ns) { 1185 lat_ns *= speed * 1000; 1186 lat_ns /= 8; 1187 lat_ns /= 1000000000; 1188 obff_hwm = (s32)(rxa - lat_ns); 1189 } 1190 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { 1191 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); 1192 return -E1000_ERR_CONFIG; 1193 } 1194 } 1195 1196 /* Set Snoop and No-Snoop latencies the same */ 1197 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1198 E1000_WRITE_REG(hw, E1000_LTRV, reg); 1199 1200 /* Set OBFF high water mark */ 1201 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; 1202 reg |= obff_hwm; 1203 E1000_WRITE_REG(hw, E1000_SVT, reg); 1204 1205 /* Enable OBFF */ 1206 reg = E1000_READ_REG(hw, E1000_SVCR); 1207 reg |= E1000_SVCR_OFF_EN; 1208 /* Always unblock interrupts to the CPU even when the system is 1209 * in OBFF mode. This ensures that small round-robin traffic 1210 * (like ping) does not get dropped or experience long latency. 1211 */ 1212 reg |= E1000_SVCR_OFF_MASKINT; 1213 E1000_WRITE_REG(hw, E1000_SVCR, reg); 1214 1215 return E1000_SUCCESS; 1216} 1217 1218/** 1219 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer 1220 * @hw: pointer to the HW structure 1221 * @itr: interrupt throttling rate 1222 * 1223 * Configure OBFF with the updated interrupt rate. 1224 **/ 1225static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) 1226{ 1227 u32 svcr; 1228 s32 timer; 1229 1230 DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); 1231 1232 /* Convert ITR value into microseconds for OBFF timer */ 1233 timer = itr & E1000_ITR_MASK; 1234 timer = (timer * E1000_ITR_MULT) / 1000; 1235 1236 if ((timer < 0) || (timer > E1000_ITR_MASK)) { 1237 DEBUGOUT1("Invalid OBFF timer %d\n", timer); 1238 return -E1000_ERR_CONFIG; 1239 } 1240 1241 svcr = E1000_READ_REG(hw, E1000_SVCR); 1242 svcr &= ~E1000_SVCR_OFF_TIMER_MASK; 1243 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; 1244 E1000_WRITE_REG(hw, E1000_SVCR, svcr); 1245 1246 return E1000_SUCCESS; 1247} 1248 1249/** 1250 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1251 * @hw: pointer to the HW structure 1252 * @to_sx: boolean indicating a system power state transition to Sx 1253 * 1254 * When link is down, configure ULP mode to significantly reduce the power 1255 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1256 * ME firmware to start the ULP configuration. If not on an ME enabled 1257 * system, configure the ULP mode by software. 1258 */ 1259s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1260{ 1261 u32 mac_reg; 1262 s32 ret_val = E1000_SUCCESS; 1263 u16 phy_reg; 1264 u16 oem_reg = 0; 1265 1266 if ((hw->mac.type < e1000_pch_lpt) || 1267 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1268 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1269 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1270 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1271 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1272 return 0; 1273 1274 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1275 /* Request ME configure ULP mode in the PHY */ 1276 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1277 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1278 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1279 1280 goto out; 1281 } 1282 1283 if (!to_sx) { 1284 int i = 0; 1285 1286 /* Poll up to 5 seconds for Cable Disconnected indication */ 1287 while (!(E1000_READ_REG(hw, E1000_FEXT) & 1288 E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1289 /* Bail if link is re-acquired */ 1290 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) 1291 return -E1000_ERR_PHY; 1292 1293 if (i++ == 100) 1294 break; 1295 1296 msec_delay(50); 1297 } 1298 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n", 1299 (E1000_READ_REG(hw, E1000_FEXT) & 1300 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", 1301 i * 50); 1302 } 1303 1304 ret_val = hw->phy.ops.acquire(hw); 1305 if (ret_val) 1306 goto out; 1307 1308 /* Force SMBus mode in PHY */ 1309 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1310 if (ret_val) 1311 goto release; 1312 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1313 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1314 1315 /* Force SMBus mode in MAC */ 1316 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1317 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1318 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1319 1320 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1321 * LPLU and disable Gig speed when entering ULP 1322 */ 1323 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1324 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1325 &oem_reg); 1326 if (ret_val) 1327 goto release; 1328 1329 phy_reg = oem_reg; 1330 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1331 1332 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1333 phy_reg); 1334 1335 if (ret_val) 1336 goto release; 1337 } 1338 1339 /* Set Inband ULP Exit, Reset to SMBus mode and 1340 * Disable SMBus Release on PERST# in PHY 1341 */ 1342 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1343 if (ret_val) 1344 goto release; 1345 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1346 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1347 if (to_sx) { 1348 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC) 1349 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1350 else 1351 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1352 1353 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1354 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1355 } else { 1356 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1357 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1358 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1359 } 1360 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1361 1362 /* Set Disable SMBus Release on PERST# in MAC */ 1363 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1364 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1365 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1366 1367 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1368 phy_reg |= I218_ULP_CONFIG1_START; 1369 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1370 1371 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1372 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 1373 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1374 oem_reg); 1375 if (ret_val) 1376 goto release; 1377 } 1378 1379release: 1380 hw->phy.ops.release(hw); 1381out: 1382 if (ret_val) 1383 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val); 1384 else 1385 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1386 1387 return ret_val; 1388} 1389 1390/** 1391 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1392 * @hw: pointer to the HW structure 1393 * @force: boolean indicating whether or not to force disabling ULP 1394 * 1395 * Un-configure ULP mode when link is up, the system is transitioned from 1396 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1397 * system, poll for an indication from ME that ULP has been un-configured. 1398 * If not on an ME enabled system, un-configure the ULP mode by software. 1399 * 1400 * During nominal operation, this function is called when link is acquired 1401 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1402 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1403 * to forcibly disable ULP. 1404 */ 1405s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1406{ 1407 s32 ret_val = E1000_SUCCESS; 1408 u32 mac_reg; 1409 u16 phy_reg; 1410 int i = 0; 1411 1412 if ((hw->mac.type < e1000_pch_lpt) || 1413 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1414 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1415 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1416 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || 1417 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1418 return 0; 1419 1420 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { 1421 if (force) { 1422 /* Request ME un-configure ULP mode in the PHY */ 1423 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1424 mac_reg &= ~E1000_H2ME_ULP; 1425 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1426 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1427 } 1428 1429 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1430 while (E1000_READ_REG(hw, E1000_FWSM) & 1431 E1000_FWSM_ULP_CFG_DONE) { 1432 if (i++ == 30) { 1433 ret_val = -E1000_ERR_PHY; 1434 goto out; 1435 } 1436 1437 msec_delay(10); 1438 } 1439 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1440 1441 if (force) { 1442 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1443 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1444 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1445 } else { 1446 /* Clear H2ME.ULP after ME ULP configuration */ 1447 mac_reg = E1000_READ_REG(hw, E1000_H2ME); 1448 mac_reg &= ~E1000_H2ME_ULP; 1449 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); 1450 } 1451 1452 goto out; 1453 } 1454 1455 ret_val = hw->phy.ops.acquire(hw); 1456 if (ret_val) 1457 goto out; 1458 1459 if (force) 1460 /* Toggle LANPHYPC Value bit */ 1461 e1000_toggle_lanphypc_pch_lpt(hw); 1462 1463 /* Unforce SMBus mode in PHY */ 1464 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1465 if (ret_val) { 1466 /* The MAC might be in PCIe mode, so temporarily force to 1467 * SMBus mode in order to access the PHY. 1468 */ 1469 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1470 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1471 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1472 1473 msec_delay(50); 1474 1475 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1476 &phy_reg); 1477 if (ret_val) 1478 goto release; 1479 } 1480 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1481 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1482 1483 /* Unforce SMBus mode in MAC */ 1484 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1485 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1486 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); 1487 1488 /* When ULP mode was previously entered, K1 was disabled by the 1489 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1490 */ 1491 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1492 if (ret_val) 1493 goto release; 1494 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1495 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1496 1497 /* Clear ULP enabled configuration */ 1498 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1499 if (ret_val) 1500 goto release; 1501 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1502 I218_ULP_CONFIG1_STICKY_ULP | 1503 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1504 I218_ULP_CONFIG1_WOL_HOST | 1505 I218_ULP_CONFIG1_INBAND_EXIT | 1506 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1507 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1508 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1509 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1510 1511 /* Commit ULP changes by starting auto ULP configuration */ 1512 phy_reg |= I218_ULP_CONFIG1_START; 1513 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1514 1515 /* Clear Disable SMBus Release on PERST# in MAC */ 1516 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); 1517 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1518 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); 1519 1520release: 1521 hw->phy.ops.release(hw); 1522 if (force) { 1523 hw->phy.ops.reset(hw); 1524 msec_delay(50); 1525 } 1526out: 1527 if (ret_val) 1528 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1529 else 1530 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1531 1532 return ret_val; 1533} 1534 1535/** 1536 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1537 * @hw: pointer to the HW structure 1538 * 1539 * Checks to see of the link status of the hardware has changed. If a 1540 * change in link status has been detected, then we read the PHY registers 1541 * to get the current speed/duplex if link exists. 1542 **/ 1543static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1544{ 1545 struct e1000_mac_info *mac = &hw->mac; 1546 s32 ret_val, tipg_reg = 0; 1547 u16 emi_addr, emi_val = 0; 1548 bool link; 1549 u16 phy_reg; 1550 1551 DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 1552 1553 /* We only want to go out to the PHY registers to see if Auto-Neg 1554 * has completed and/or if our link status has changed. The 1555 * get_link_status flag is set upon receiving a Link Status 1556 * Change or Rx Sequence Error interrupt. 1557 */ 1558 if (!mac->get_link_status) 1559 return E1000_SUCCESS; 1560 1561 /* First we want to see if the MII Status Register reports 1562 * link. If so, then we want to get the current speed/duplex 1563 * of the PHY. 1564 */ 1565 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1566 if (ret_val) 1567 return ret_val; 1568 1569 if (hw->mac.type == e1000_pchlan) { 1570 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1571 if (ret_val) 1572 return ret_val; 1573 } 1574 1575 /* When connected at 10Mbps half-duplex, some parts are excessively 1576 * aggressive resulting in many collisions. To avoid this, increase 1577 * the IPG and reduce Rx latency in the PHY. 1578 */ 1579 if (((hw->mac.type == e1000_pch2lan) || 1580 (hw->mac.type == e1000_pch_lpt) || 1581 (hw->mac.type == e1000_pch_spt)) && link) { 1582 u16 speed, duplex; 1583 1584 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex); 1585 tipg_reg = E1000_READ_REG(hw, E1000_TIPG); 1586 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1587 1588 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1589 tipg_reg |= 0xFF; 1590 /* Reduce Rx latency in analog PHY */ 1591 emi_val = 0; 1592 } else if (hw->mac.type == e1000_pch_spt && 1593 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1594 tipg_reg |= 0xC; 1595 emi_val = 1; 1596 } else { 1597 /* Roll back the default values */ 1598 tipg_reg |= 0x08; 1599 emi_val = 1; 1600 } 1601 1602 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg); 1603 1604 ret_val = hw->phy.ops.acquire(hw); 1605 if (ret_val) 1606 return ret_val; 1607 1608 if (hw->mac.type == e1000_pch2lan) 1609 emi_addr = I82579_RX_CONFIG; 1610 else 1611 emi_addr = I217_RX_CONFIG; 1612 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1613 1614 if (hw->mac.type == e1000_pch_lpt || 1615 hw->mac.type == e1000_pch_spt) { 1616 u16 phy_reg; 1617 1618 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, 1619 &phy_reg); 1620 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1621 if (speed == SPEED_100 || speed == SPEED_10) 1622 phy_reg |= 0x3E8; 1623 else 1624 phy_reg |= 0xFA; 1625 hw->phy.ops.write_reg_locked(hw, 1626 I217_PLL_CLOCK_GATE_REG, 1627 phy_reg); 1628 1629 if (speed == SPEED_1000) { 1630 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1631 &phy_reg); 1632 1633 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1634 1635 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1636 phy_reg); 1637 } 1638 } 1639 hw->phy.ops.release(hw); 1640 1641 if (ret_val) 1642 return ret_val; 1643 1644 if (hw->mac.type == e1000_pch_spt) { 1645 u16 data; 1646 u16 ptr_gap; 1647 1648 if (speed == SPEED_1000) { 1649 ret_val = hw->phy.ops.acquire(hw); 1650 if (ret_val) 1651 return ret_val; 1652 1653 ret_val = hw->phy.ops.read_reg_locked(hw, 1654 PHY_REG(776, 20), 1655 &data); 1656 if (ret_val) { 1657 hw->phy.ops.release(hw); 1658 return ret_val; 1659 } 1660 1661 ptr_gap = (data & (0x3FF << 2)) >> 2; 1662 if (ptr_gap < 0x18) { 1663 data &= ~(0x3FF << 2); 1664 data |= (0x18 << 2); 1665 ret_val = 1666 hw->phy.ops.write_reg_locked(hw, 1667 PHY_REG(776, 20), data); 1668 } 1669 hw->phy.ops.release(hw); 1670 if (ret_val) 1671 return ret_val; 1672 } else { 1673 ret_val = hw->phy.ops.acquire(hw); 1674 if (ret_val) 1675 return ret_val; 1676 1677 ret_val = hw->phy.ops.write_reg_locked(hw, 1678 PHY_REG(776, 20), 1679 0xC023); 1680 hw->phy.ops.release(hw); 1681 if (ret_val) 1682 return ret_val; 1683 1684 } 1685 } 1686 } 1687 1688 /* I217 Packet Loss issue: 1689 * ensure that FEXTNVM4 Beacon Duration is set correctly 1690 * on power up. 1691 * Set the Beacon Duration for I217 to 8 usec 1692 */ 1693 if ((hw->mac.type == e1000_pch_lpt) || 1694 (hw->mac.type == e1000_pch_spt)) { 1695 u32 mac_reg; 1696 1697 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 1698 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1699 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1700 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 1701 } 1702 1703 /* Work-around I218 hang issue */ 1704 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1705 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1706 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 1707 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 1708 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1709 if (ret_val) 1710 return ret_val; 1711 } 1712 if ((hw->mac.type == e1000_pch_lpt) || 1713 (hw->mac.type == e1000_pch_spt)) { 1714 /* Set platform power management values for 1715 * Latency Tolerance Reporting (LTR) 1716 * Optimized Buffer Flush/Fill (OBFF) 1717 */ 1718 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1719 if (ret_val) 1720 return ret_val; 1721 } 1722 1723 /* Clear link partner's EEE ability */ 1724 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1725 1726 /* FEXTNVM6 K1-off workaround */ 1727 if (hw->mac.type == e1000_pch_spt) { 1728 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG); 1729 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 1730 1731 if ((pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) && 1732 (hw->dev_spec.ich8lan.disable_k1_off == FALSE)) 1733 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1734 else 1735 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1736 1737 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); 1738 } 1739 1740 if (!link) 1741 return E1000_SUCCESS; /* No link detected */ 1742 1743 mac->get_link_status = FALSE; 1744 1745 switch (hw->mac.type) { 1746 case e1000_pch2lan: 1747 ret_val = e1000_k1_workaround_lv(hw); 1748 if (ret_val) 1749 return ret_val; 1750 /* fall-thru */ 1751 case e1000_pchlan: 1752 if (hw->phy.type == e1000_phy_82578) { 1753 ret_val = e1000_link_stall_workaround_hv(hw); 1754 if (ret_val) 1755 return ret_val; 1756 } 1757 1758 /* Workaround for PCHx parts in half-duplex: 1759 * Set the number of preambles removed from the packet 1760 * when it is passed from the PHY to the MAC to prevent 1761 * the MAC from misinterpreting the packet type. 1762 */ 1763 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1764 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1765 1766 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != 1767 E1000_STATUS_FD) 1768 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1769 1770 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1771 break; 1772 default: 1773 break; 1774 } 1775 1776 /* Check if there was DownShift, must be checked 1777 * immediately after link-up 1778 */ 1779 e1000_check_downshift_generic(hw); 1780 1781 /* Enable/Disable EEE after link up */ 1782 if (hw->phy.type > e1000_phy_82579) { 1783 ret_val = e1000_set_eee_pchlan(hw); 1784 if (ret_val) 1785 return ret_val; 1786 } 1787 1788 /* If we are forcing speed/duplex, then we simply return since 1789 * we have already determined whether we have link or not. 1790 */ 1791 if (!mac->autoneg) 1792 return -E1000_ERR_CONFIG; 1793 1794 /* Auto-Neg is enabled. Auto Speed Detection takes care 1795 * of MAC speed/duplex configuration. So we only need to 1796 * configure Collision Distance in the MAC. 1797 */ 1798 mac->ops.config_collision_dist(hw); 1799 1800 /* Configure Flow Control now that Auto-Neg has completed. 1801 * First, we need to restore the desired flow control 1802 * settings because we may have had to re-autoneg with a 1803 * different link partner. 1804 */ 1805 ret_val = e1000_config_fc_after_link_up_generic(hw); 1806 if (ret_val) 1807 DEBUGOUT("Error configuring flow control\n"); 1808 1809 return ret_val; 1810} 1811 1812/** 1813 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 1814 * @hw: pointer to the HW structure 1815 * 1816 * Initialize family-specific function pointers for PHY, MAC, and NVM. 1817 **/ 1818void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 1819{ 1820 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 1821 1822 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 1823 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 1824 switch (hw->mac.type) { 1825 case e1000_ich8lan: 1826 case e1000_ich9lan: 1827 case e1000_ich10lan: 1828 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 1829 break; 1830 case e1000_pchlan: 1831 case e1000_pch2lan: 1832 case e1000_pch_lpt: 1833 case e1000_pch_spt: 1834 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 1835 break; 1836 default: 1837 break; 1838 } 1839} 1840 1841/** 1842 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1843 * @hw: pointer to the HW structure 1844 * 1845 * Acquires the mutex for performing NVM operations. 1846 **/ 1847static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 1848{ 1849 DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 1850 1851 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1852 1853 return E1000_SUCCESS; 1854} 1855 1856/** 1857 * e1000_release_nvm_ich8lan - Release NVM mutex 1858 * @hw: pointer to the HW structure 1859 * 1860 * Releases the mutex used while performing NVM operations. 1861 **/ 1862static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 1863{ 1864 DEBUGFUNC("e1000_release_nvm_ich8lan"); 1865 1866 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 1867 1868 return; 1869} 1870 1871/** 1872 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1873 * @hw: pointer to the HW structure 1874 * 1875 * Acquires the software control flag for performing PHY and select 1876 * MAC CSR accesses. 1877 **/ 1878static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1879{ 1880 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1881 s32 ret_val = E1000_SUCCESS; 1882 1883 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 1884 1885 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1886 1887 while (timeout) { 1888 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1889 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1890 break; 1891 1892 msec_delay_irq(1); 1893 timeout--; 1894 } 1895 1896 if (!timeout) { 1897 DEBUGOUT("SW has already locked the resource.\n"); 1898 ret_val = -E1000_ERR_CONFIG; 1899 goto out; 1900 } 1901 1902 timeout = SW_FLAG_TIMEOUT; 1903 1904 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1905 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1906 1907 while (timeout) { 1908 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1909 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1910 break; 1911 1912 msec_delay_irq(1); 1913 timeout--; 1914 } 1915 1916 if (!timeout) { 1917 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1918 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); 1919 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1920 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1921 ret_val = -E1000_ERR_CONFIG; 1922 goto out; 1923 } 1924 1925out: 1926 if (ret_val) 1927 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1928 1929 return ret_val; 1930} 1931 1932/** 1933 * e1000_release_swflag_ich8lan - Release software control flag 1934 * @hw: pointer to the HW structure 1935 * 1936 * Releases the software control flag for performing PHY and select 1937 * MAC CSR accesses. 1938 **/ 1939static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1940{ 1941 u32 extcnf_ctrl; 1942 1943 DEBUGFUNC("e1000_release_swflag_ich8lan"); 1944 1945 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1946 1947 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1948 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1949 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1950 } else { 1951 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); 1952 } 1953 1954 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 1955 1956 return; 1957} 1958 1959/** 1960 * e1000_check_mng_mode_ich8lan - Checks management mode 1961 * @hw: pointer to the HW structure 1962 * 1963 * This checks if the adapter has any manageability enabled. 1964 * This is a function pointer entry point only called by read/write 1965 * routines for the PHY and NVM parts. 1966 **/ 1967static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1968{ 1969 u32 fwsm; 1970 1971 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 1972 1973 fwsm = E1000_READ_REG(hw, E1000_FWSM); 1974 1975 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1976 ((fwsm & E1000_FWSM_MODE_MASK) == 1977 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1978} 1979 1980/** 1981 * e1000_check_mng_mode_pchlan - Checks management mode 1982 * @hw: pointer to the HW structure 1983 * 1984 * This checks if the adapter has iAMT enabled. 1985 * This is a function pointer entry point only called by read/write 1986 * routines for the PHY and NVM parts. 1987 **/ 1988static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1989{ 1990 u32 fwsm; 1991 1992 DEBUGFUNC("e1000_check_mng_mode_pchlan"); 1993 1994 fwsm = E1000_READ_REG(hw, E1000_FWSM); 1995 1996 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1997 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1998} 1999 2000/** 2001 * e1000_rar_set_pch2lan - Set receive address register 2002 * @hw: pointer to the HW structure 2003 * @addr: pointer to the receive address 2004 * @index: receive address array register 2005 * 2006 * Sets the receive address array register at index to the address passed 2007 * in by addr. For 82579, RAR[0] is the base address register that is to 2008 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 2009 * Use SHRA[0-3] in place of those reserved for ME. 2010 **/ 2011static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 2012{ 2013 u32 rar_low, rar_high; 2014 2015 DEBUGFUNC("e1000_rar_set_pch2lan"); 2016 2017 /* HW expects these in little endian so we reverse the byte order 2018 * from network order (big endian) to little endian 2019 */ 2020 rar_low = ((u32) addr[0] | 2021 ((u32) addr[1] << 8) | 2022 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2023 2024 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2025 2026 /* If MAC address zero, no need to set the AV bit */ 2027 if (rar_low || rar_high) 2028 rar_high |= E1000_RAH_AV; 2029 2030 if (index == 0) { 2031 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2032 E1000_WRITE_FLUSH(hw); 2033 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2034 E1000_WRITE_FLUSH(hw); 2035 return E1000_SUCCESS; 2036 } 2037 2038 /* RAR[1-6] are owned by manageability. Skip those and program the 2039 * next address into the SHRA register array. 2040 */ 2041 if (index < (u32) (hw->mac.rar_entry_count)) { 2042 s32 ret_val; 2043 2044 ret_val = e1000_acquire_swflag_ich8lan(hw); 2045 if (ret_val) 2046 goto out; 2047 2048 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 2049 E1000_WRITE_FLUSH(hw); 2050 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 2051 E1000_WRITE_FLUSH(hw); 2052 2053 e1000_release_swflag_ich8lan(hw); 2054 2055 /* verify the register updates */ 2056 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 2057 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 2058 return E1000_SUCCESS; 2059 2060 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2061 (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 2062 } 2063 2064out: 2065 DEBUGOUT1("Failed to write receive address at index %d\n", index); 2066 return -E1000_ERR_CONFIG; 2067} 2068 2069/** 2070 * e1000_rar_set_pch_lpt - Set receive address registers 2071 * @hw: pointer to the HW structure 2072 * @addr: pointer to the receive address 2073 * @index: receive address array register 2074 * 2075 * Sets the receive address register array at index to the address passed 2076 * in by addr. For LPT, RAR[0] is the base address register that is to 2077 * contain the MAC address. SHRA[0-10] are the shared receive address 2078 * registers that are shared between the Host and manageability engine (ME). 2079 **/ 2080static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2081{ 2082 u32 rar_low, rar_high; 2083 u32 wlock_mac; 2084 2085 DEBUGFUNC("e1000_rar_set_pch_lpt"); 2086 2087 /* HW expects these in little endian so we reverse the byte order 2088 * from network order (big endian) to little endian 2089 */ 2090 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 2091 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 2092 2093 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 2094 2095 /* If MAC address zero, no need to set the AV bit */ 2096 if (rar_low || rar_high) 2097 rar_high |= E1000_RAH_AV; 2098 2099 if (index == 0) { 2100 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 2101 E1000_WRITE_FLUSH(hw); 2102 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 2103 E1000_WRITE_FLUSH(hw); 2104 return E1000_SUCCESS; 2105 } 2106 2107 /* The manageability engine (ME) can lock certain SHRAR registers that 2108 * it is using - those registers are unavailable for use. 2109 */ 2110 if (index < hw->mac.rar_entry_count) { 2111 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & 2112 E1000_FWSM_WLOCK_MAC_MASK; 2113 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2114 2115 /* Check if all SHRAR registers are locked */ 2116 if (wlock_mac == 1) 2117 goto out; 2118 2119 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2120 s32 ret_val; 2121 2122 ret_val = e1000_acquire_swflag_ich8lan(hw); 2123 2124 if (ret_val) 2125 goto out; 2126 2127 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), 2128 rar_low); 2129 E1000_WRITE_FLUSH(hw); 2130 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), 2131 rar_high); 2132 E1000_WRITE_FLUSH(hw); 2133 2134 e1000_release_swflag_ich8lan(hw); 2135 2136 /* verify the register updates */ 2137 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && 2138 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) 2139 return E1000_SUCCESS; 2140 } 2141 } 2142 2143out: 2144 DEBUGOUT1("Failed to write receive address at index %d\n", index); 2145 return -E1000_ERR_CONFIG; 2146} 2147 2148/** 2149 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses 2150 * @hw: pointer to the HW structure 2151 * @mc_addr_list: array of multicast addresses to program 2152 * @mc_addr_count: number of multicast addresses to program 2153 * 2154 * Updates entire Multicast Table Array of the PCH2 MAC and PHY. 2155 * The caller must have a packed mc_addr_list of multicast addresses. 2156 **/ 2157static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, 2158 u8 *mc_addr_list, 2159 u32 mc_addr_count) 2160{ 2161 u16 phy_reg = 0; 2162 int i; 2163 s32 ret_val; 2164 2165 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); 2166 2167 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); 2168 2169 ret_val = hw->phy.ops.acquire(hw); 2170 if (ret_val) 2171 return; 2172 2173 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2174 if (ret_val) 2175 goto release; 2176 2177 for (i = 0; i < hw->mac.mta_reg_count; i++) { 2178 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 2179 (u16)(hw->mac.mta_shadow[i] & 2180 0xFFFF)); 2181 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), 2182 (u16)((hw->mac.mta_shadow[i] >> 16) & 2183 0xFFFF)); 2184 } 2185 2186 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2187 2188release: 2189 hw->phy.ops.release(hw); 2190} 2191 2192/** 2193 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2194 * @hw: pointer to the HW structure 2195 * 2196 * Checks if firmware is blocking the reset of the PHY. 2197 * This is a function pointer entry point only called by 2198 * reset routines. 2199 **/ 2200static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2201{ 2202 u32 fwsm; 2203 bool blocked = FALSE; 2204 int i = 0; 2205 2206 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 2207 2208 do { 2209 fwsm = E1000_READ_REG(hw, E1000_FWSM); 2210 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) { 2211 blocked = TRUE; 2212 msec_delay(10); 2213 continue; 2214 } 2215 blocked = FALSE; 2216 } while (blocked && (i++ < 30)); 2217 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 2218} 2219 2220/** 2221 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2222 * @hw: pointer to the HW structure 2223 * 2224 * Assumes semaphore already acquired. 2225 * 2226 **/ 2227static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2228{ 2229 u16 phy_data; 2230 u32 strap = E1000_READ_REG(hw, E1000_STRAP); 2231 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2232 E1000_STRAP_SMT_FREQ_SHIFT; 2233 s32 ret_val; 2234 2235 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2236 2237 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2238 if (ret_val) 2239 return ret_val; 2240 2241 phy_data &= ~HV_SMB_ADDR_MASK; 2242 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2243 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2244 2245 if (hw->phy.type == e1000_phy_i217) { 2246 /* Restore SMBus frequency */ 2247 if (freq--) { 2248 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2249 phy_data |= (freq & (1 << 0)) << 2250 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2251 phy_data |= (freq & (1 << 1)) << 2252 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2253 } else { 2254 DEBUGOUT("Unsupported SMB frequency in PHY\n"); 2255 } 2256 } 2257 2258 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2259} 2260 2261/** 2262 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2263 * @hw: pointer to the HW structure 2264 * 2265 * SW should configure the LCD from the NVM extended configuration region 2266 * as a workaround for certain parts. 2267 **/ 2268static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2269{ 2270 struct e1000_phy_info *phy = &hw->phy; 2271 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2272 s32 ret_val = E1000_SUCCESS; 2273 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2274 2275 DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 2276 2277 /* Initialize the PHY from the NVM on ICH platforms. This 2278 * is needed due to an issue where the NVM configuration is 2279 * not properly autoloaded after power transitions. 2280 * Therefore, after each PHY reset, we will load the 2281 * configuration data out of the NVM manually. 2282 */ 2283 switch (hw->mac.type) { 2284 case e1000_ich8lan: 2285 if (phy->type != e1000_phy_igp_3) 2286 return ret_val; 2287 2288 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 2289 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 2290 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2291 break; 2292 } 2293 /* Fall-thru */ 2294 case e1000_pchlan: 2295 case e1000_pch2lan: 2296 case e1000_pch_lpt: 2297 case e1000_pch_spt: 2298 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2299 break; 2300 default: 2301 return ret_val; 2302 } 2303 2304 ret_val = hw->phy.ops.acquire(hw); 2305 if (ret_val) 2306 return ret_val; 2307 2308 data = E1000_READ_REG(hw, E1000_FEXTNVM); 2309 if (!(data & sw_cfg_mask)) 2310 goto release; 2311 2312 /* Make sure HW does not configure LCD from PHY 2313 * extended configuration before SW configuration 2314 */ 2315 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2316 if ((hw->mac.type < e1000_pch2lan) && 2317 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2318 goto release; 2319 2320 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 2321 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2322 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2323 if (!cnf_size) 2324 goto release; 2325 2326 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2327 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2328 2329 if (((hw->mac.type == e1000_pchlan) && 2330 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2331 (hw->mac.type > e1000_pchlan)) { 2332 /* HW configures the SMBus address and LEDs when the 2333 * OEM and LCD Write Enable bits are set in the NVM. 2334 * When both NVM bits are cleared, SW will configure 2335 * them instead. 2336 */ 2337 ret_val = e1000_write_smbus_addr(hw); 2338 if (ret_val) 2339 goto release; 2340 2341 data = E1000_READ_REG(hw, E1000_LEDCTL); 2342 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2343 (u16)data); 2344 if (ret_val) 2345 goto release; 2346 } 2347 2348 /* Configure LCD from extended configuration region. */ 2349 2350 /* cnf_base_addr is in DWORD */ 2351 word_addr = (u16)(cnf_base_addr << 1); 2352 2353 for (i = 0; i < cnf_size; i++) { 2354 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 2355 ®_data); 2356 if (ret_val) 2357 goto release; 2358 2359 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 2360 1, ®_addr); 2361 if (ret_val) 2362 goto release; 2363 2364 /* Save off the PHY page for future writes. */ 2365 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2366 phy_page = reg_data; 2367 continue; 2368 } 2369 2370 reg_addr &= PHY_REG_MASK; 2371 reg_addr |= phy_page; 2372 2373 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 2374 reg_data); 2375 if (ret_val) 2376 goto release; 2377 } 2378 2379release: 2380 hw->phy.ops.release(hw); 2381 return ret_val; 2382} 2383 2384/** 2385 * e1000_k1_gig_workaround_hv - K1 Si workaround 2386 * @hw: pointer to the HW structure 2387 * @link: link up bool flag 2388 * 2389 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2390 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2391 * If link is down, the function will restore the default K1 setting located 2392 * in the NVM. 2393 **/ 2394static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2395{ 2396 s32 ret_val = E1000_SUCCESS; 2397 u16 status_reg = 0; 2398 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2399 2400 DEBUGFUNC("e1000_k1_gig_workaround_hv"); 2401 2402 if (hw->mac.type != e1000_pchlan) 2403 return E1000_SUCCESS; 2404 2405 /* Wrap the whole flow with the sw flag */ 2406 ret_val = hw->phy.ops.acquire(hw); 2407 if (ret_val) 2408 return ret_val; 2409 2410 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2411 if (link) { 2412 if (hw->phy.type == e1000_phy_82578) { 2413 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 2414 &status_reg); 2415 if (ret_val) 2416 goto release; 2417 2418 status_reg &= (BM_CS_STATUS_LINK_UP | 2419 BM_CS_STATUS_RESOLVED | 2420 BM_CS_STATUS_SPEED_MASK); 2421 2422 if (status_reg == (BM_CS_STATUS_LINK_UP | 2423 BM_CS_STATUS_RESOLVED | 2424 BM_CS_STATUS_SPEED_1000)) 2425 k1_enable = FALSE; 2426 } 2427 2428 if (hw->phy.type == e1000_phy_82577) { 2429 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 2430 &status_reg); 2431 if (ret_val) 2432 goto release; 2433 2434 status_reg &= (HV_M_STATUS_LINK_UP | 2435 HV_M_STATUS_AUTONEG_COMPLETE | 2436 HV_M_STATUS_SPEED_MASK); 2437 2438 if (status_reg == (HV_M_STATUS_LINK_UP | 2439 HV_M_STATUS_AUTONEG_COMPLETE | 2440 HV_M_STATUS_SPEED_1000)) 2441 k1_enable = FALSE; 2442 } 2443 2444 /* Link stall fix for link up */ 2445 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2446 0x0100); 2447 if (ret_val) 2448 goto release; 2449 2450 } else { 2451 /* Link stall fix for link down */ 2452 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 2453 0x4100); 2454 if (ret_val) 2455 goto release; 2456 } 2457 2458 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2459 2460release: 2461 hw->phy.ops.release(hw); 2462 2463 return ret_val; 2464} 2465 2466/** 2467 * e1000_configure_k1_ich8lan - Configure K1 power state 2468 * @hw: pointer to the HW structure 2469 * @enable: K1 state to configure 2470 * 2471 * Configure the K1 power state based on the provided parameter. 2472 * Assumes semaphore already acquired. 2473 * 2474 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2475 **/ 2476s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2477{ 2478 s32 ret_val; 2479 u32 ctrl_reg = 0; 2480 u32 ctrl_ext = 0; 2481 u32 reg = 0; 2482 u16 kmrn_reg = 0; 2483 2484 DEBUGFUNC("e1000_configure_k1_ich8lan"); 2485 2486 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2487 &kmrn_reg); 2488 if (ret_val) 2489 return ret_val; 2490 2491 if (k1_enable) 2492 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2493 else 2494 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2495 2496 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2497 kmrn_reg); 2498 if (ret_val) 2499 return ret_val; 2500 2501 usec_delay(20); 2502 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2503 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 2504 2505 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2506 reg |= E1000_CTRL_FRCSPD; 2507 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2508 2509 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2510 E1000_WRITE_FLUSH(hw); 2511 usec_delay(20); 2512 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 2513 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2514 E1000_WRITE_FLUSH(hw); 2515 usec_delay(20); 2516 2517 return E1000_SUCCESS; 2518} 2519 2520/** 2521 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2522 * @hw: pointer to the HW structure 2523 * @d0_state: boolean if entering d0 or d3 device state 2524 * 2525 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2526 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2527 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2528 **/ 2529static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2530{ 2531 s32 ret_val = 0; 2532 u32 mac_reg; 2533 u16 oem_reg; 2534 2535 DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 2536 2537 if (hw->mac.type < e1000_pchlan) 2538 return ret_val; 2539 2540 ret_val = hw->phy.ops.acquire(hw); 2541 if (ret_val) 2542 return ret_val; 2543 2544 if (hw->mac.type == e1000_pchlan) { 2545 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 2546 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2547 goto release; 2548 } 2549 2550 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 2551 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2552 goto release; 2553 2554 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2555 2556 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 2557 if (ret_val) 2558 goto release; 2559 2560 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2561 2562 if (d0_state) { 2563 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2564 oem_reg |= HV_OEM_BITS_GBE_DIS; 2565 2566 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2567 oem_reg |= HV_OEM_BITS_LPLU; 2568 } else { 2569 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2570 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2571 oem_reg |= HV_OEM_BITS_GBE_DIS; 2572 2573 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2574 E1000_PHY_CTRL_NOND0A_LPLU)) 2575 oem_reg |= HV_OEM_BITS_LPLU; 2576 } 2577 2578 /* Set Restart auto-neg to activate the bits */ 2579 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2580 !hw->phy.ops.check_reset_block(hw)) 2581 oem_reg |= HV_OEM_BITS_RESTART_AN; 2582 2583 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 2584 2585release: 2586 hw->phy.ops.release(hw); 2587 2588 return ret_val; 2589} 2590 2591 2592/** 2593 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2594 * @hw: pointer to the HW structure 2595 **/ 2596static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2597{ 2598 s32 ret_val; 2599 u16 data; 2600 2601 DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 2602 2603 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 2604 if (ret_val) 2605 return ret_val; 2606 2607 data |= HV_KMRN_MDIO_SLOW; 2608 2609 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 2610 2611 return ret_val; 2612} 2613 2614/** 2615 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2616 * done after every PHY reset. 2617 **/ 2618static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2619{ 2620 s32 ret_val = E1000_SUCCESS; 2621 u16 phy_data; 2622 2623 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 2624 2625 if (hw->mac.type != e1000_pchlan) 2626 return E1000_SUCCESS; 2627 2628 /* Set MDIO slow mode before any other MDIO access */ 2629 if (hw->phy.type == e1000_phy_82577) { 2630 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2631 if (ret_val) 2632 return ret_val; 2633 } 2634 2635 if (((hw->phy.type == e1000_phy_82577) && 2636 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2637 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2638 /* Disable generation of early preamble */ 2639 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 2640 if (ret_val) 2641 return ret_val; 2642 2643 /* Preamble tuning for SSC */ 2644 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 2645 0xA204); 2646 if (ret_val) 2647 return ret_val; 2648 } 2649 2650 if (hw->phy.type == e1000_phy_82578) { 2651 /* Return registers to default by doing a soft reset then 2652 * writing 0x3140 to the control register. 2653 */ 2654 if (hw->phy.revision < 2) { 2655 e1000_phy_sw_reset_generic(hw); 2656 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 2657 0x3140); 2658 } 2659 } 2660 2661 /* Select page 0 */ 2662 ret_val = hw->phy.ops.acquire(hw); 2663 if (ret_val) 2664 return ret_val; 2665 2666 hw->phy.addr = 1; 2667 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2668 hw->phy.ops.release(hw); 2669 if (ret_val) 2670 return ret_val; 2671 2672 /* Configure the K1 Si workaround during phy reset assuming there is 2673 * link so that it disables K1 if link is in 1Gbps. 2674 */ 2675 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 2676 if (ret_val) 2677 return ret_val; 2678 2679 /* Workaround for link disconnects on a busy hub in half duplex */ 2680 ret_val = hw->phy.ops.acquire(hw); 2681 if (ret_val) 2682 return ret_val; 2683 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2684 if (ret_val) 2685 goto release; 2686 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, 2687 phy_data & 0x00FF); 2688 if (ret_val) 2689 goto release; 2690 2691 /* set MSE higher to enable link to stay up when noise is high */ 2692 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2693release: 2694 hw->phy.ops.release(hw); 2695 2696 return ret_val; 2697} 2698 2699/** 2700 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2701 * @hw: pointer to the HW structure 2702 **/ 2703void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2704{ 2705 u32 mac_reg; 2706 u16 i, phy_reg = 0; 2707 s32 ret_val; 2708 2709 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 2710 2711 ret_val = hw->phy.ops.acquire(hw); 2712 if (ret_val) 2713 return; 2714 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2715 if (ret_val) 2716 goto release; 2717 2718 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2719 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2720 mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 2721 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2722 (u16)(mac_reg & 0xFFFF)); 2723 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2724 (u16)((mac_reg >> 16) & 0xFFFF)); 2725 2726 mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 2727 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2728 (u16)(mac_reg & 0xFFFF)); 2729 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2730 (u16)((mac_reg & E1000_RAH_AV) 2731 >> 16)); 2732 } 2733 2734 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2735 2736release: 2737 hw->phy.ops.release(hw); 2738} 2739 2740static u32 e1000_calc_rx_da_crc(u8 mac[]) 2741{ 2742 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 2743 u32 i, j, mask, crc; 2744 2745 DEBUGFUNC("e1000_calc_rx_da_crc"); 2746 2747 crc = 0xffffffff; 2748 for (i = 0; i < 6; i++) { 2749 crc = crc ^ mac[i]; 2750 for (j = 8; j > 0; j--) { 2751 mask = (crc & 1) * (-1); 2752 crc = (crc >> 1) ^ (poly & mask); 2753 } 2754 } 2755 return ~crc; 2756} 2757 2758/** 2759 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2760 * with 82579 PHY 2761 * @hw: pointer to the HW structure 2762 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2763 **/ 2764s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2765{ 2766 s32 ret_val = E1000_SUCCESS; 2767 u16 phy_reg, data; 2768 u32 mac_reg; 2769 u16 i; 2770 2771 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 2772 2773 if (hw->mac.type < e1000_pch2lan) 2774 return E1000_SUCCESS; 2775 2776 /* disable Rx path while enabling/disabling workaround */ 2777 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 2778 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), 2779 phy_reg | (1 << 14)); 2780 if (ret_val) 2781 return ret_val; 2782 2783 if (enable) { 2784 /* Write Rx addresses (rar_entry_count for RAL/H, and 2785 * SHRAL/H) and initial CRC values to the MAC 2786 */ 2787 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2788 u8 mac_addr[ETH_ADDR_LEN] = {0}; 2789 u32 addr_high, addr_low; 2790 2791 addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 2792 if (!(addr_high & E1000_RAH_AV)) 2793 continue; 2794 addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 2795 mac_addr[0] = (addr_low & 0xFF); 2796 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2797 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2798 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2799 mac_addr[4] = (addr_high & 0xFF); 2800 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2801 2802 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 2803 e1000_calc_rx_da_crc(mac_addr)); 2804 } 2805 2806 /* Write Rx addresses to the PHY */ 2807 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2808 2809 /* Enable jumbo frame workaround in the MAC */ 2810 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2811 mac_reg &= ~(1 << 14); 2812 mac_reg |= (7 << 15); 2813 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2814 2815 mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2816 mac_reg |= E1000_RCTL_SECRC; 2817 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2818 2819 ret_val = e1000_read_kmrn_reg_generic(hw, 2820 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2821 &data); 2822 if (ret_val) 2823 return ret_val; 2824 ret_val = e1000_write_kmrn_reg_generic(hw, 2825 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2826 data | (1 << 0)); 2827 if (ret_val) 2828 return ret_val; 2829 ret_val = e1000_read_kmrn_reg_generic(hw, 2830 E1000_KMRNCTRLSTA_HD_CTRL, 2831 &data); 2832 if (ret_val) 2833 return ret_val; 2834 data &= ~(0xF << 8); 2835 data |= (0xB << 8); 2836 ret_val = e1000_write_kmrn_reg_generic(hw, 2837 E1000_KMRNCTRLSTA_HD_CTRL, 2838 data); 2839 if (ret_val) 2840 return ret_val; 2841 2842 /* Enable jumbo frame workaround in the PHY */ 2843 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2844 data &= ~(0x7F << 5); 2845 data |= (0x37 << 5); 2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2847 if (ret_val) 2848 return ret_val; 2849 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2850 data &= ~(1 << 13); 2851 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2852 if (ret_val) 2853 return ret_val; 2854 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2855 data &= ~(0x3FF << 2); 2856 data |= (E1000_TX_PTR_GAP << 2); 2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2858 if (ret_val) 2859 return ret_val; 2860 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); 2861 if (ret_val) 2862 return ret_val; 2863 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2864 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | 2865 (1 << 10)); 2866 if (ret_val) 2867 return ret_val; 2868 } else { 2869 /* Write MAC register values back to h/w defaults */ 2870 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 2871 mac_reg &= ~(0xF << 14); 2872 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 2873 2874 mac_reg = E1000_READ_REG(hw, E1000_RCTL); 2875 mac_reg &= ~E1000_RCTL_SECRC; 2876 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 2877 2878 ret_val = e1000_read_kmrn_reg_generic(hw, 2879 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2880 &data); 2881 if (ret_val) 2882 return ret_val; 2883 ret_val = e1000_write_kmrn_reg_generic(hw, 2884 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2885 data & ~(1 << 0)); 2886 if (ret_val) 2887 return ret_val; 2888 ret_val = e1000_read_kmrn_reg_generic(hw, 2889 E1000_KMRNCTRLSTA_HD_CTRL, 2890 &data); 2891 if (ret_val) 2892 return ret_val; 2893 data &= ~(0xF << 8); 2894 data |= (0xB << 8); 2895 ret_val = e1000_write_kmrn_reg_generic(hw, 2896 E1000_KMRNCTRLSTA_HD_CTRL, 2897 data); 2898 if (ret_val) 2899 return ret_val; 2900 2901 /* Write PHY register values back to h/w defaults */ 2902 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 2903 data &= ~(0x7F << 5); 2904 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 2905 if (ret_val) 2906 return ret_val; 2907 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 2908 data |= (1 << 13); 2909 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 2910 if (ret_val) 2911 return ret_val; 2912 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 2913 data &= ~(0x3FF << 2); 2914 data |= (0x8 << 2); 2915 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 2916 if (ret_val) 2917 return ret_val; 2918 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 2919 if (ret_val) 2920 return ret_val; 2921 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 2922 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & 2923 ~(1 << 10)); 2924 if (ret_val) 2925 return ret_val; 2926 } 2927 2928 /* re-enable Rx path after enabling/disabling workaround */ 2929 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & 2930 ~(1 << 14)); 2931} 2932 2933/** 2934 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2935 * done after every PHY reset. 2936 **/ 2937static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2938{ 2939 s32 ret_val = E1000_SUCCESS; 2940 2941 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 2942 2943 if (hw->mac.type != e1000_pch2lan) 2944 return E1000_SUCCESS; 2945 2946 /* Set MDIO slow mode before any other MDIO access */ 2947 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2948 if (ret_val) 2949 return ret_val; 2950 2951 ret_val = hw->phy.ops.acquire(hw); 2952 if (ret_val) 2953 return ret_val; 2954 /* set MSE higher to enable link to stay up when noise is high */ 2955 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2956 if (ret_val) 2957 goto release; 2958 /* drop link after 5 times MSE threshold was reached */ 2959 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2960release: 2961 hw->phy.ops.release(hw); 2962 2963 return ret_val; 2964} 2965 2966/** 2967 * e1000_k1_gig_workaround_lv - K1 Si workaround 2968 * @hw: pointer to the HW structure 2969 * 2970 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2971 * Disable K1 for 1000 and 100 speeds 2972 **/ 2973static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2974{ 2975 s32 ret_val = E1000_SUCCESS; 2976 u16 status_reg = 0; 2977 2978 DEBUGFUNC("e1000_k1_workaround_lv"); 2979 2980 if (hw->mac.type != e1000_pch2lan) 2981 return E1000_SUCCESS; 2982 2983 /* Set K1 beacon duration based on 10Mbs speed */ 2984 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 2985 if (ret_val) 2986 return ret_val; 2987 2988 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2989 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2990 if (status_reg & 2991 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2992 u16 pm_phy_reg; 2993 2994 /* LV 1G/100 Packet drop issue wa */ 2995 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, 2996 &pm_phy_reg); 2997 if (ret_val) 2998 return ret_val; 2999 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 3000 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, 3001 pm_phy_reg); 3002 if (ret_val) 3003 return ret_val; 3004 } else { 3005 u32 mac_reg; 3006 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 3007 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 3008 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 3009 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 3010 } 3011 } 3012 3013 return ret_val; 3014} 3015 3016/** 3017 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 3018 * @hw: pointer to the HW structure 3019 * @gate: boolean set to TRUE to gate, FALSE to ungate 3020 * 3021 * Gate/ungate the automatic PHY configuration via hardware; perform 3022 * the configuration via software instead. 3023 **/ 3024static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 3025{ 3026 u32 extcnf_ctrl; 3027 3028 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 3029 3030 if (hw->mac.type < e1000_pch2lan) 3031 return; 3032 3033 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 3034 3035 if (gate) 3036 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3037 else 3038 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 3039 3040 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 3041} 3042 3043/** 3044 * e1000_lan_init_done_ich8lan - Check for PHY config completion 3045 * @hw: pointer to the HW structure 3046 * 3047 * Check the appropriate indication the MAC has finished configuring the 3048 * PHY after a software reset. 3049 **/ 3050static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 3051{ 3052 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 3053 3054 DEBUGFUNC("e1000_lan_init_done_ich8lan"); 3055 3056 /* Wait for basic configuration completes before proceeding */ 3057 do { 3058 data = E1000_READ_REG(hw, E1000_STATUS); 3059 data &= E1000_STATUS_LAN_INIT_DONE; 3060 usec_delay(100); 3061 } while ((!data) && --loop); 3062 3063 /* If basic configuration is incomplete before the above loop 3064 * count reaches 0, loading the configuration from NVM will 3065 * leave the PHY in a bad state possibly resulting in no link. 3066 */ 3067 if (loop == 0) 3068 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 3069 3070 /* Clear the Init Done bit for the next init event */ 3071 data = E1000_READ_REG(hw, E1000_STATUS); 3072 data &= ~E1000_STATUS_LAN_INIT_DONE; 3073 E1000_WRITE_REG(hw, E1000_STATUS, data); 3074} 3075 3076/** 3077 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 3078 * @hw: pointer to the HW structure 3079 **/ 3080static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 3081{ 3082 s32 ret_val = E1000_SUCCESS; 3083 u16 reg; 3084 3085 DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 3086 3087 if (hw->phy.ops.check_reset_block(hw)) 3088 return E1000_SUCCESS; 3089 3090 /* Allow time for h/w to get to quiescent state after reset */ 3091 msec_delay(10); 3092 3093 /* Perform any necessary post-reset workarounds */ 3094 switch (hw->mac.type) { 3095 case e1000_pchlan: 3096 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3097 if (ret_val) 3098 return ret_val; 3099 break; 3100 case e1000_pch2lan: 3101 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3102 if (ret_val) 3103 return ret_val; 3104 break; 3105 default: 3106 break; 3107 } 3108 3109 /* Clear the host wakeup bit after lcd reset */ 3110 if (hw->mac.type >= e1000_pchlan) { 3111 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); 3112 reg &= ~BM_WUC_HOST_WU_BIT; 3113 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); 3114 } 3115 3116 /* Configure the LCD with the extended configuration region in NVM */ 3117 ret_val = e1000_sw_lcd_config_ich8lan(hw); 3118 if (ret_val) 3119 return ret_val; 3120 3121 /* Configure the LCD with the OEM bits in NVM */ 3122 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 3123 3124 if (hw->mac.type == e1000_pch2lan) { 3125 /* Ungate automatic PHY configuration on non-managed 82579 */ 3126 if (!(E1000_READ_REG(hw, E1000_FWSM) & 3127 E1000_ICH_FWSM_FW_VALID)) { 3128 msec_delay(10); 3129 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 3130 } 3131 3132 /* Set EEE LPI Update Timer to 200usec */ 3133 ret_val = hw->phy.ops.acquire(hw); 3134 if (ret_val) 3135 return ret_val; 3136 ret_val = e1000_write_emi_reg_locked(hw, 3137 I82579_LPI_UPDATE_TIMER, 3138 0x1387); 3139 hw->phy.ops.release(hw); 3140 } 3141 3142 return ret_val; 3143} 3144 3145/** 3146 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3147 * @hw: pointer to the HW structure 3148 * 3149 * Resets the PHY 3150 * This is a function pointer entry point called by drivers 3151 * or other shared routines. 3152 **/ 3153static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3154{ 3155 s32 ret_val = E1000_SUCCESS; 3156 3157 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 3158 3159 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3160 if ((hw->mac.type == e1000_pch2lan) && 3161 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3162 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3163 3164 ret_val = e1000_phy_hw_reset_generic(hw); 3165 if (ret_val) 3166 return ret_val; 3167 3168 return e1000_post_phy_reset_ich8lan(hw); 3169} 3170 3171/** 3172 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3173 * @hw: pointer to the HW structure 3174 * @active: TRUE to enable LPLU, FALSE to disable 3175 * 3176 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3177 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3178 * the phy speed. This function will manually set the LPLU bit and restart 3179 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3180 * since it configures the same bit. 3181 **/ 3182static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3183{ 3184 s32 ret_val; 3185 u16 oem_reg; 3186 3187 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 3188 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 3189 if (ret_val) 3190 return ret_val; 3191 3192 if (active) 3193 oem_reg |= HV_OEM_BITS_LPLU; 3194 else 3195 oem_reg &= ~HV_OEM_BITS_LPLU; 3196 3197 if (!hw->phy.ops.check_reset_block(hw)) 3198 oem_reg |= HV_OEM_BITS_RESTART_AN; 3199 3200 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 3201} 3202 3203/** 3204 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3205 * @hw: pointer to the HW structure 3206 * @active: TRUE to enable LPLU, FALSE to disable 3207 * 3208 * Sets the LPLU D0 state according to the active flag. When 3209 * activating LPLU this function also disables smart speed 3210 * and vice versa. LPLU will not be activated unless the 3211 * device autonegotiation advertisement meets standards of 3212 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3213 * This is a function pointer entry point only called by 3214 * PHY setup routines. 3215 **/ 3216static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3217{ 3218 struct e1000_phy_info *phy = &hw->phy; 3219 u32 phy_ctrl; 3220 s32 ret_val = E1000_SUCCESS; 3221 u16 data; 3222 3223 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 3224 3225 if (phy->type == e1000_phy_ife) 3226 return E1000_SUCCESS; 3227 3228 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3229 3230 if (active) { 3231 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3232 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3233 3234 if (phy->type != e1000_phy_igp_3) 3235 return E1000_SUCCESS; 3236 3237 /* Call gig speed drop workaround on LPLU before accessing 3238 * any PHY registers 3239 */ 3240 if (hw->mac.type == e1000_ich8lan) 3241 e1000_gig_downshift_workaround_ich8lan(hw); 3242 3243 /* When LPLU is enabled, we should disable SmartSpeed */ 3244 ret_val = phy->ops.read_reg(hw, 3245 IGP01E1000_PHY_PORT_CONFIG, 3246 &data); 3247 if (ret_val) 3248 return ret_val; 3249 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3250 ret_val = phy->ops.write_reg(hw, 3251 IGP01E1000_PHY_PORT_CONFIG, 3252 data); 3253 if (ret_val) 3254 return ret_val; 3255 } else { 3256 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3257 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3258 3259 if (phy->type != e1000_phy_igp_3) 3260 return E1000_SUCCESS; 3261 3262 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3263 * during Dx states where the power conservation is most 3264 * important. During driver activity we should enable 3265 * SmartSpeed, so performance is maintained. 3266 */ 3267 if (phy->smart_speed == e1000_smart_speed_on) { 3268 ret_val = phy->ops.read_reg(hw, 3269 IGP01E1000_PHY_PORT_CONFIG, 3270 &data); 3271 if (ret_val) 3272 return ret_val; 3273 3274 data |= IGP01E1000_PSCFR_SMART_SPEED; 3275 ret_val = phy->ops.write_reg(hw, 3276 IGP01E1000_PHY_PORT_CONFIG, 3277 data); 3278 if (ret_val) 3279 return ret_val; 3280 } else if (phy->smart_speed == e1000_smart_speed_off) { 3281 ret_val = phy->ops.read_reg(hw, 3282 IGP01E1000_PHY_PORT_CONFIG, 3283 &data); 3284 if (ret_val) 3285 return ret_val; 3286 3287 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3288 ret_val = phy->ops.write_reg(hw, 3289 IGP01E1000_PHY_PORT_CONFIG, 3290 data); 3291 if (ret_val) 3292 return ret_val; 3293 } 3294 } 3295 3296 return E1000_SUCCESS; 3297} 3298 3299/** 3300 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3301 * @hw: pointer to the HW structure 3302 * @active: TRUE to enable LPLU, FALSE to disable 3303 * 3304 * Sets the LPLU D3 state according to the active flag. When 3305 * activating LPLU this function also disables smart speed 3306 * and vice versa. LPLU will not be activated unless the 3307 * device autonegotiation advertisement meets standards of 3308 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3309 * This is a function pointer entry point only called by 3310 * PHY setup routines. 3311 **/ 3312static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3313{ 3314 struct e1000_phy_info *phy = &hw->phy; 3315 u32 phy_ctrl; 3316 s32 ret_val = E1000_SUCCESS; 3317 u16 data; 3318 3319 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 3320 3321 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3322 3323 if (!active) { 3324 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3325 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3326 3327 if (phy->type != e1000_phy_igp_3) 3328 return E1000_SUCCESS; 3329 3330 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3331 * during Dx states where the power conservation is most 3332 * important. During driver activity we should enable 3333 * SmartSpeed, so performance is maintained. 3334 */ 3335 if (phy->smart_speed == e1000_smart_speed_on) { 3336 ret_val = phy->ops.read_reg(hw, 3337 IGP01E1000_PHY_PORT_CONFIG, 3338 &data); 3339 if (ret_val) 3340 return ret_val; 3341 3342 data |= IGP01E1000_PSCFR_SMART_SPEED; 3343 ret_val = phy->ops.write_reg(hw, 3344 IGP01E1000_PHY_PORT_CONFIG, 3345 data); 3346 if (ret_val) 3347 return ret_val; 3348 } else if (phy->smart_speed == e1000_smart_speed_off) { 3349 ret_val = phy->ops.read_reg(hw, 3350 IGP01E1000_PHY_PORT_CONFIG, 3351 &data); 3352 if (ret_val) 3353 return ret_val; 3354 3355 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3356 ret_val = phy->ops.write_reg(hw, 3357 IGP01E1000_PHY_PORT_CONFIG, 3358 data); 3359 if (ret_val) 3360 return ret_val; 3361 } 3362 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3363 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3364 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3365 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3366 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3367 3368 if (phy->type != e1000_phy_igp_3) 3369 return E1000_SUCCESS; 3370 3371 /* Call gig speed drop workaround on LPLU before accessing 3372 * any PHY registers 3373 */ 3374 if (hw->mac.type == e1000_ich8lan) 3375 e1000_gig_downshift_workaround_ich8lan(hw); 3376 3377 /* When LPLU is enabled, we should disable SmartSpeed */ 3378 ret_val = phy->ops.read_reg(hw, 3379 IGP01E1000_PHY_PORT_CONFIG, 3380 &data); 3381 if (ret_val) 3382 return ret_val; 3383 3384 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3385 ret_val = phy->ops.write_reg(hw, 3386 IGP01E1000_PHY_PORT_CONFIG, 3387 data); 3388 } 3389 3390 return ret_val; 3391} 3392 3393/** 3394 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3395 * @hw: pointer to the HW structure 3396 * @bank: pointer to the variable that returns the active bank 3397 * 3398 * Reads signature byte from the NVM using the flash access registers. 3399 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3400 **/ 3401static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3402{ 3403 u32 eecd; 3404 struct e1000_nvm_info *nvm = &hw->nvm; 3405 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3406 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3407 u32 nvm_dword = 0; 3408 u8 sig_byte = 0; 3409 s32 ret_val; 3410 3411 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 3412 3413 switch (hw->mac.type) { 3414 case e1000_pch_spt: 3415 bank1_offset = nvm->flash_bank_size; 3416 act_offset = E1000_ICH_NVM_SIG_WORD; 3417 3418 /* set bank to 0 in case flash read fails */ 3419 *bank = 0; 3420 3421 /* Check bank 0 */ 3422 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3423 &nvm_dword); 3424 if (ret_val) 3425 return ret_val; 3426 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3427 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3428 E1000_ICH_NVM_SIG_VALUE) { 3429 *bank = 0; 3430 return E1000_SUCCESS; 3431 } 3432 3433 /* Check bank 1 */ 3434 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3435 bank1_offset, 3436 &nvm_dword); 3437 if (ret_val) 3438 return ret_val; 3439 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3440 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3441 E1000_ICH_NVM_SIG_VALUE) { 3442 *bank = 1; 3443 return E1000_SUCCESS; 3444 } 3445 3446 DEBUGOUT("ERROR: No valid NVM bank present\n"); 3447 return -E1000_ERR_NVM; 3448 case e1000_ich8lan: 3449 case e1000_ich9lan: 3450 eecd = E1000_READ_REG(hw, E1000_EECD); 3451 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3452 E1000_EECD_SEC1VAL_VALID_MASK) { 3453 if (eecd & E1000_EECD_SEC1VAL) 3454 *bank = 1; 3455 else 3456 *bank = 0; 3457 3458 return E1000_SUCCESS; 3459 } 3460 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3461 /* fall-thru */ 3462 default: 3463 /* set bank to 0 in case flash read fails */ 3464 *bank = 0; 3465 3466 /* Check bank 0 */ 3467 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3468 &sig_byte); 3469 if (ret_val) 3470 return ret_val; 3471 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3472 E1000_ICH_NVM_SIG_VALUE) { 3473 *bank = 0; 3474 return E1000_SUCCESS; 3475 } 3476 3477 /* Check bank 1 */ 3478 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3479 bank1_offset, 3480 &sig_byte); 3481 if (ret_val) 3482 return ret_val; 3483 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3484 E1000_ICH_NVM_SIG_VALUE) { 3485 *bank = 1; 3486 return E1000_SUCCESS; 3487 } 3488 3489 DEBUGOUT("ERROR: No valid NVM bank present\n"); 3490 return -E1000_ERR_NVM; 3491 } 3492} 3493 3494/** 3495 * e1000_read_nvm_spt - NVM access for SPT 3496 * @hw: pointer to the HW structure 3497 * @offset: The offset (in bytes) of the word(s) to read. 3498 * @words: Size of data to read in words. 3499 * @data: pointer to the word(s) to read at offset. 3500 * 3501 * Reads a word(s) from the NVM 3502 **/ 3503static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3504 u16 *data) 3505{ 3506 struct e1000_nvm_info *nvm = &hw->nvm; 3507 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3508 u32 act_offset; 3509 s32 ret_val = E1000_SUCCESS; 3510 u32 bank = 0; 3511 u32 dword = 0; 3512 u16 offset_to_read; 3513 u16 i; 3514 3515 DEBUGFUNC("e1000_read_nvm_spt"); 3516 3517 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3518 (words == 0)) { 3519 DEBUGOUT("nvm parameter(s) out of bounds\n"); 3520 ret_val = -E1000_ERR_NVM; 3521 goto out; 3522 } 3523 3524 nvm->ops.acquire(hw); 3525 3526 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3527 if (ret_val != E1000_SUCCESS) { 3528 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3529 bank = 0; 3530 } 3531 3532 act_offset = (bank) ? nvm->flash_bank_size : 0; 3533 act_offset += offset; 3534 3535 ret_val = E1000_SUCCESS; 3536 3537 for (i = 0; i < words; i += 2) { 3538 if (words - i == 1) { 3539 if (dev_spec->shadow_ram[offset+i].modified) { 3540 data[i] = dev_spec->shadow_ram[offset+i].value; 3541 } else { 3542 offset_to_read = act_offset + i - 3543 ((act_offset + i) % 2); 3544 ret_val = 3545 e1000_read_flash_dword_ich8lan(hw, 3546 offset_to_read, 3547 &dword); 3548 if (ret_val) 3549 break; 3550 if ((act_offset + i) % 2 == 0) 3551 data[i] = (u16)(dword & 0xFFFF); 3552 else 3553 data[i] = (u16)((dword >> 16) & 0xFFFF); 3554 } 3555 } else { 3556 offset_to_read = act_offset + i; 3557 if (!(dev_spec->shadow_ram[offset+i].modified) || 3558 !(dev_spec->shadow_ram[offset+i+1].modified)) { 3559 ret_val = 3560 e1000_read_flash_dword_ich8lan(hw, 3561 offset_to_read, 3562 &dword); 3563 if (ret_val) 3564 break; 3565 } 3566 if (dev_spec->shadow_ram[offset+i].modified) 3567 data[i] = dev_spec->shadow_ram[offset+i].value; 3568 else 3569 data[i] = (u16) (dword & 0xFFFF); 3570 if (dev_spec->shadow_ram[offset+i].modified) 3571 data[i+1] = 3572 dev_spec->shadow_ram[offset+i+1].value; 3573 else 3574 data[i+1] = (u16) (dword >> 16 & 0xFFFF); 3575 } 3576 } 3577 3578 nvm->ops.release(hw); 3579 3580out: 3581 if (ret_val) 3582 DEBUGOUT1("NVM read error: %d\n", ret_val); 3583 3584 return ret_val; 3585} 3586 3587/** 3588 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3589 * @hw: pointer to the HW structure 3590 * @offset: The offset (in bytes) of the word(s) to read. 3591 * @words: Size of data to read in words 3592 * @data: Pointer to the word(s) to read at offset. 3593 * 3594 * Reads a word(s) from the NVM using the flash access registers. 3595 **/ 3596static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3597 u16 *data) 3598{ 3599 struct e1000_nvm_info *nvm = &hw->nvm; 3600 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3601 u32 act_offset; 3602 s32 ret_val = E1000_SUCCESS; 3603 u32 bank = 0; 3604 u16 i, word; 3605 3606 DEBUGFUNC("e1000_read_nvm_ich8lan"); 3607 3608 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3609 (words == 0)) { 3610 DEBUGOUT("nvm parameter(s) out of bounds\n"); 3611 ret_val = -E1000_ERR_NVM; 3612 goto out; 3613 } 3614 3615 nvm->ops.acquire(hw); 3616 3617 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3618 if (ret_val != E1000_SUCCESS) { 3619 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 3620 bank = 0; 3621 } 3622 3623 act_offset = (bank) ? nvm->flash_bank_size : 0; 3624 act_offset += offset; 3625 3626 ret_val = E1000_SUCCESS; 3627 for (i = 0; i < words; i++) { 3628 if (dev_spec->shadow_ram[offset+i].modified) { 3629 data[i] = dev_spec->shadow_ram[offset+i].value; 3630 } else { 3631 ret_val = e1000_read_flash_word_ich8lan(hw, 3632 act_offset + i, 3633 &word); 3634 if (ret_val) 3635 break; 3636 data[i] = word; 3637 } 3638 } 3639 3640 nvm->ops.release(hw); 3641 3642out: 3643 if (ret_val) 3644 DEBUGOUT1("NVM read error: %d\n", ret_val); 3645 3646 return ret_val; 3647} 3648 3649/** 3650 * e1000_flash_cycle_init_ich8lan - Initialize flash 3651 * @hw: pointer to the HW structure 3652 * 3653 * This function does initial flash setup so that a new read/write/erase cycle 3654 * can be started. 3655 **/ 3656static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3657{ 3658 union ich8_hws_flash_status hsfsts; 3659 s32 ret_val = -E1000_ERR_NVM; 3660 3661 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 3662 3663 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3664 3665 /* Check if the flash descriptor is valid */ 3666 if (!hsfsts.hsf_status.fldesvalid) { 3667 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); 3668 return -E1000_ERR_NVM; 3669 } 3670 3671 /* Clear FCERR and DAEL in hw status by writing 1 */ 3672 hsfsts.hsf_status.flcerr = 1; 3673 hsfsts.hsf_status.dael = 1; 3674 if (hw->mac.type == e1000_pch_spt) 3675 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3676 hsfsts.regval & 0xFFFF); 3677 else 3678 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 3679 3680 /* Either we should have a hardware SPI cycle in progress 3681 * bit to check against, in order to start a new cycle or 3682 * FDONE bit should be changed in the hardware so that it 3683 * is 1 after hardware reset, which can then be used as an 3684 * indication whether a cycle is in progress or has been 3685 * completed. 3686 */ 3687 3688 if (!hsfsts.hsf_status.flcinprog) { 3689 /* There is no cycle running at present, 3690 * so we can start a cycle. 3691 * Begin by setting Flash Cycle Done. 3692 */ 3693 hsfsts.hsf_status.flcdone = 1; 3694 if (hw->mac.type == e1000_pch_spt) 3695 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3696 hsfsts.regval & 0xFFFF); 3697 else 3698 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3699 hsfsts.regval); 3700 ret_val = E1000_SUCCESS; 3701 } else { 3702 s32 i; 3703 3704 /* Otherwise poll for sometime so the current 3705 * cycle has a chance to end before giving up. 3706 */ 3707 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3708 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3709 ICH_FLASH_HSFSTS); 3710 if (!hsfsts.hsf_status.flcinprog) { 3711 ret_val = E1000_SUCCESS; 3712 break; 3713 } 3714 usec_delay(1); 3715 } 3716 if (ret_val == E1000_SUCCESS) { 3717 /* Successful in waiting for previous cycle to timeout, 3718 * now set the Flash Cycle Done. 3719 */ 3720 hsfsts.hsf_status.flcdone = 1; 3721 if (hw->mac.type == e1000_pch_spt) 3722 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3723 hsfsts.regval & 0xFFFF); 3724 else 3725 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 3726 hsfsts.regval); 3727 } else { 3728 DEBUGOUT("Flash controller busy, cannot get access\n"); 3729 } 3730 } 3731 3732 return ret_val; 3733} 3734 3735/** 3736 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3737 * @hw: pointer to the HW structure 3738 * @timeout: maximum time to wait for completion 3739 * 3740 * This function starts a flash cycle and waits for its completion. 3741 **/ 3742static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3743{ 3744 union ich8_hws_flash_ctrl hsflctl; 3745 union ich8_hws_flash_status hsfsts; 3746 u32 i = 0; 3747 3748 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 3749 3750 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3751 if (hw->mac.type == e1000_pch_spt) 3752 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3753 else 3754 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3755 hsflctl.hsf_ctrl.flcgo = 1; 3756 3757 if (hw->mac.type == e1000_pch_spt) 3758 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3759 hsflctl.regval << 16); 3760 else 3761 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3762 3763 /* wait till FDONE bit is set to 1 */ 3764 do { 3765 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 3766 if (hsfsts.hsf_status.flcdone) 3767 break; 3768 usec_delay(1); 3769 } while (i++ < timeout); 3770 3771 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3772 return E1000_SUCCESS; 3773 3774 return -E1000_ERR_NVM; 3775} 3776 3777/** 3778 * e1000_read_flash_dword_ich8lan - Read dword from flash 3779 * @hw: pointer to the HW structure 3780 * @offset: offset to data location 3781 * @data: pointer to the location for storing the data 3782 * 3783 * Reads the flash dword at offset into data. Offset is converted 3784 * to bytes before read. 3785 **/ 3786static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3787 u32 *data) 3788{ 3789 DEBUGFUNC("e1000_read_flash_dword_ich8lan"); 3790 3791 if (!data) 3792 return -E1000_ERR_NVM; 3793 3794 /* Must convert word offset into bytes. */ 3795 offset <<= 1; 3796 3797 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3798} 3799 3800/** 3801 * e1000_read_flash_word_ich8lan - Read word from flash 3802 * @hw: pointer to the HW structure 3803 * @offset: offset to data location 3804 * @data: pointer to the location for storing the data 3805 * 3806 * Reads the flash word at offset into data. Offset is converted 3807 * to bytes before read. 3808 **/ 3809static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3810 u16 *data) 3811{ 3812 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 3813 3814 if (!data) 3815 return -E1000_ERR_NVM; 3816 3817 /* Must convert offset into bytes. */ 3818 offset <<= 1; 3819 3820 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3821} 3822 3823/** 3824 * e1000_read_flash_byte_ich8lan - Read byte from flash 3825 * @hw: pointer to the HW structure 3826 * @offset: The offset of the byte to read. 3827 * @data: Pointer to a byte to store the value read. 3828 * 3829 * Reads a single byte from the NVM using the flash access registers. 3830 **/ 3831static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3832 u8 *data) 3833{ 3834 s32 ret_val; 3835 u16 word = 0; 3836 3837 /* In SPT, only 32 bits access is supported, 3838 * so this function should not be called. 3839 */ 3840 if (hw->mac.type == e1000_pch_spt) 3841 return -E1000_ERR_NVM; 3842 else 3843 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3844 3845 if (ret_val) 3846 return ret_val; 3847 3848 *data = (u8)word; 3849 3850 return E1000_SUCCESS; 3851} 3852 3853/** 3854 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3855 * @hw: pointer to the HW structure 3856 * @offset: The offset (in bytes) of the byte or word to read. 3857 * @size: Size of data to read, 1=byte 2=word 3858 * @data: Pointer to the word to store the value read. 3859 * 3860 * Reads a byte or word from the NVM using the flash access registers. 3861 **/ 3862static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3863 u8 size, u16 *data) 3864{ 3865 union ich8_hws_flash_status hsfsts; 3866 union ich8_hws_flash_ctrl hsflctl; 3867 u32 flash_linear_addr; 3868 u32 flash_data = 0; 3869 s32 ret_val = -E1000_ERR_NVM; 3870 u8 count = 0; 3871 3872 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3873 3874 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3875 return -E1000_ERR_NVM; 3876 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3877 hw->nvm.flash_base_addr); 3878 3879 do { 3880 usec_delay(1); 3881 /* Steps */ 3882 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3883 if (ret_val != E1000_SUCCESS) 3884 break; 3885 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 3886 3887 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3888 hsflctl.hsf_ctrl.fldbcount = size - 1; 3889 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3890 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 3891 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3892 3893 ret_val = e1000_flash_cycle_ich8lan(hw, 3894 ICH_FLASH_READ_COMMAND_TIMEOUT); 3895 3896 /* Check if FCERR is set to 1, if set to 1, clear it 3897 * and try the whole sequence a few more times, else 3898 * read in (shift in) the Flash Data0, the order is 3899 * least significant byte first msb to lsb 3900 */ 3901 if (ret_val == E1000_SUCCESS) { 3902 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3903 if (size == 1) 3904 *data = (u8)(flash_data & 0x000000FF); 3905 else if (size == 2) 3906 *data = (u16)(flash_data & 0x0000FFFF); 3907 break; 3908 } else { 3909 /* If we've gotten here, then things are probably 3910 * completely hosed, but if the error condition is 3911 * detected, it won't hurt to give it another try... 3912 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3913 */ 3914 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3915 ICH_FLASH_HSFSTS); 3916 if (hsfsts.hsf_status.flcerr) { 3917 /* Repeat for some time before giving up. */ 3918 continue; 3919 } else if (!hsfsts.hsf_status.flcdone) { 3920 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3921 break; 3922 } 3923 } 3924 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3925 3926 return ret_val; 3927} 3928 3929/** 3930 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3931 * @hw: pointer to the HW structure 3932 * @offset: The offset (in bytes) of the dword to read. 3933 * @data: Pointer to the dword to store the value read. 3934 * 3935 * Reads a byte or word from the NVM using the flash access registers. 3936 **/ 3937static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3938 u32 *data) 3939{ 3940 union ich8_hws_flash_status hsfsts; 3941 union ich8_hws_flash_ctrl hsflctl; 3942 u32 flash_linear_addr; 3943 s32 ret_val = -E1000_ERR_NVM; 3944 u8 count = 0; 3945 3946 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 3947 3948 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || 3949 hw->mac.type != e1000_pch_spt) 3950 return -E1000_ERR_NVM; 3951 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3952 hw->nvm.flash_base_addr); 3953 3954 do { 3955 usec_delay(1); 3956 /* Steps */ 3957 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3958 if (ret_val != E1000_SUCCESS) 3959 break; 3960 /* In SPT, This register is in Lan memory space, not flash. 3961 * Therefore, only 32 bit access is supported 3962 */ 3963 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 3964 3965 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3966 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3967 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3968 /* In SPT, This register is in Lan memory space, not flash. 3969 * Therefore, only 32 bit access is supported 3970 */ 3971 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 3972 (u32)hsflctl.regval << 16); 3973 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 3974 3975 ret_val = e1000_flash_cycle_ich8lan(hw, 3976 ICH_FLASH_READ_COMMAND_TIMEOUT); 3977 3978 /* Check if FCERR is set to 1, if set to 1, clear it 3979 * and try the whole sequence a few more times, else 3980 * read in (shift in) the Flash Data0, the order is 3981 * least significant byte first msb to lsb 3982 */ 3983 if (ret_val == E1000_SUCCESS) { 3984 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 3985 break; 3986 } else { 3987 /* If we've gotten here, then things are probably 3988 * completely hosed, but if the error condition is 3989 * detected, it won't hurt to give it another try... 3990 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3991 */ 3992 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3993 ICH_FLASH_HSFSTS); 3994 if (hsfsts.hsf_status.flcerr) { 3995 /* Repeat for some time before giving up. */ 3996 continue; 3997 } else if (!hsfsts.hsf_status.flcdone) { 3998 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 3999 break; 4000 } 4001 } 4002 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4003 4004 return ret_val; 4005} 4006 4007/** 4008 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 4009 * @hw: pointer to the HW structure 4010 * @offset: The offset (in bytes) of the word(s) to write. 4011 * @words: Size of data to write in words 4012 * @data: Pointer to the word(s) to write at offset. 4013 * 4014 * Writes a byte or word to the NVM using the flash access registers. 4015 **/ 4016static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 4017 u16 *data) 4018{ 4019 struct e1000_nvm_info *nvm = &hw->nvm; 4020 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4021 u16 i; 4022 4023 DEBUGFUNC("e1000_write_nvm_ich8lan"); 4024 4025 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 4026 (words == 0)) { 4027 DEBUGOUT("nvm parameter(s) out of bounds\n"); 4028 return -E1000_ERR_NVM; 4029 } 4030 4031 nvm->ops.acquire(hw); 4032 4033 for (i = 0; i < words; i++) { 4034 dev_spec->shadow_ram[offset+i].modified = TRUE; 4035 dev_spec->shadow_ram[offset+i].value = data[i]; 4036 } 4037 4038 nvm->ops.release(hw); 4039 4040 return E1000_SUCCESS; 4041} 4042 4043/** 4044 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 4045 * @hw: pointer to the HW structure 4046 * 4047 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4048 * which writes the checksum to the shadow ram. The changes in the shadow 4049 * ram are then committed to the EEPROM by processing each bank at a time 4050 * checking for the modified bit and writing only the pending changes. 4051 * After a successful commit, the shadow ram is cleared and is ready for 4052 * future writes. 4053 **/ 4054static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 4055{ 4056 struct e1000_nvm_info *nvm = &hw->nvm; 4057 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4058 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4059 s32 ret_val; 4060 u32 dword = 0; 4061 4062 DEBUGFUNC("e1000_update_nvm_checksum_spt"); 4063 4064 ret_val = e1000_update_nvm_checksum_generic(hw); 4065 if (ret_val) 4066 goto out; 4067 4068 if (nvm->type != e1000_nvm_flash_sw) 4069 goto out; 4070 4071 nvm->ops.acquire(hw); 4072 4073 /* We're writing to the opposite bank so if we're on bank 1, 4074 * write to bank 0 etc. We also need to erase the segment that 4075 * is going to be written 4076 */ 4077 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4078 if (ret_val != E1000_SUCCESS) { 4079 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4080 bank = 0; 4081 } 4082 4083 if (bank == 0) { 4084 new_bank_offset = nvm->flash_bank_size; 4085 old_bank_offset = 0; 4086 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4087 if (ret_val) 4088 goto release; 4089 } else { 4090 old_bank_offset = nvm->flash_bank_size; 4091 new_bank_offset = 0; 4092 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4093 if (ret_val) 4094 goto release; 4095 } 4096 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) { 4097 /* Determine whether to write the value stored 4098 * in the other NVM bank or a modified value stored 4099 * in the shadow RAM 4100 */ 4101 ret_val = e1000_read_flash_dword_ich8lan(hw, 4102 i + old_bank_offset, 4103 &dword); 4104 4105 if (dev_spec->shadow_ram[i].modified) { 4106 dword &= 0xffff0000; 4107 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 4108 } 4109 if (dev_spec->shadow_ram[i + 1].modified) { 4110 dword &= 0x0000ffff; 4111 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 4112 << 16); 4113 } 4114 if (ret_val) 4115 break; 4116 4117 /* If the word is 0x13, then make sure the signature bits 4118 * (15:14) are 11b until the commit has completed. 4119 * This will allow us to write 10b which indicates the 4120 * signature is valid. We want to do this after the write 4121 * has completed so that we don't mark the segment valid 4122 * while the write is still in progress 4123 */ 4124 if (i == E1000_ICH_NVM_SIG_WORD - 1) 4125 dword |= E1000_ICH_NVM_SIG_MASK << 16; 4126 4127 /* Convert offset to bytes. */ 4128 act_offset = (i + new_bank_offset) << 1; 4129 4130 usec_delay(100); 4131 4132 /* Write the data to the new bank. Offset in words*/ 4133 act_offset = i + new_bank_offset; 4134 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4135 dword); 4136 if (ret_val) 4137 break; 4138 } 4139 4140 /* Don't bother writing the segment valid bits if sector 4141 * programming failed. 4142 */ 4143 if (ret_val) { 4144 DEBUGOUT("Flash commit failed.\n"); 4145 goto release; 4146 } 4147 4148 /* Finally validate the new segment by setting bit 15:14 4149 * to 10b in word 0x13 , this can be done without an 4150 * erase as well since these bits are 11 to start with 4151 * and we need to change bit 14 to 0b 4152 */ 4153 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4154 4155 /*offset in words but we read dword*/ 4156 --act_offset; 4157 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4158 4159 if (ret_val) 4160 goto release; 4161 4162 dword &= 0xBFFFFFFF; 4163 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4164 4165 if (ret_val) 4166 goto release; 4167 4168 /* And invalidate the previously valid segment by setting 4169 * its signature word (0x13) high_byte to 0b. This can be 4170 * done without an erase because flash erase sets all bits 4171 * to 1's. We can write 1's to 0's without an erase 4172 */ 4173 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4174 4175 /* offset in words but we read dword*/ 4176 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4177 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4178 4179 if (ret_val) 4180 goto release; 4181 4182 dword &= 0x00FFFFFF; 4183 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4184 4185 if (ret_val) 4186 goto release; 4187 4188 /* Great! Everything worked, we can now clear the cached entries. */ 4189 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4190 dev_spec->shadow_ram[i].modified = FALSE; 4191 dev_spec->shadow_ram[i].value = 0xFFFF; 4192 } 4193 4194release: 4195 nvm->ops.release(hw); 4196 4197 /* Reload the EEPROM, or else modifications will not appear 4198 * until after the next adapter reset. 4199 */ 4200 if (!ret_val) { 4201 nvm->ops.reload(hw); 4202 msec_delay(10); 4203 } 4204 4205out: 4206 if (ret_val) 4207 DEBUGOUT1("NVM update error: %d\n", ret_val); 4208 4209 return ret_val; 4210} 4211 4212/** 4213 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4214 * @hw: pointer to the HW structure 4215 * 4216 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4217 * which writes the checksum to the shadow ram. The changes in the shadow 4218 * ram are then committed to the EEPROM by processing each bank at a time 4219 * checking for the modified bit and writing only the pending changes. 4220 * After a successful commit, the shadow ram is cleared and is ready for 4221 * future writes. 4222 **/ 4223static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4224{ 4225 struct e1000_nvm_info *nvm = &hw->nvm; 4226 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4227 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4228 s32 ret_val; 4229 u16 data = 0; 4230 4231 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 4232 4233 ret_val = e1000_update_nvm_checksum_generic(hw); 4234 if (ret_val) 4235 goto out; 4236 4237 if (nvm->type != e1000_nvm_flash_sw) 4238 goto out; 4239 4240 nvm->ops.acquire(hw); 4241 4242 /* We're writing to the opposite bank so if we're on bank 1, 4243 * write to bank 0 etc. We also need to erase the segment that 4244 * is going to be written 4245 */ 4246 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4247 if (ret_val != E1000_SUCCESS) { 4248 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 4249 bank = 0; 4250 } 4251 4252 if (bank == 0) { 4253 new_bank_offset = nvm->flash_bank_size; 4254 old_bank_offset = 0; 4255 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4256 if (ret_val) 4257 goto release; 4258 } else { 4259 old_bank_offset = nvm->flash_bank_size; 4260 new_bank_offset = 0; 4261 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4262 if (ret_val) 4263 goto release; 4264 } 4265 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4266 if (dev_spec->shadow_ram[i].modified) { 4267 data = dev_spec->shadow_ram[i].value; 4268 } else { 4269 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4270 old_bank_offset, 4271 &data); 4272 if (ret_val) 4273 break; 4274 } 4275 /* If the word is 0x13, then make sure the signature bits 4276 * (15:14) are 11b until the commit has completed. 4277 * This will allow us to write 10b which indicates the 4278 * signature is valid. We want to do this after the write 4279 * has completed so that we don't mark the segment valid 4280 * while the write is still in progress 4281 */ 4282 if (i == E1000_ICH_NVM_SIG_WORD) 4283 data |= E1000_ICH_NVM_SIG_MASK; 4284 4285 /* Convert offset to bytes. */ 4286 act_offset = (i + new_bank_offset) << 1; 4287 4288 usec_delay(100); 4289 4290 /* Write the bytes to the new bank. */ 4291 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4292 act_offset, 4293 (u8)data); 4294 if (ret_val) 4295 break; 4296 4297 usec_delay(100); 4298 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4299 act_offset + 1, 4300 (u8)(data >> 8)); 4301 if (ret_val) 4302 break; 4303 } 4304 4305 /* Don't bother writing the segment valid bits if sector 4306 * programming failed. 4307 */ 4308 if (ret_val) { 4309 DEBUGOUT("Flash commit failed.\n"); 4310 goto release; 4311 } 4312 4313 /* Finally validate the new segment by setting bit 15:14 4314 * to 10b in word 0x13 , this can be done without an 4315 * erase as well since these bits are 11 to start with 4316 * and we need to change bit 14 to 0b 4317 */ 4318 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4319 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4320 if (ret_val) 4321 goto release; 4322 4323 data &= 0xBFFF; 4324 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, 4325 (u8)(data >> 8)); 4326 if (ret_val) 4327 goto release; 4328 4329 /* And invalidate the previously valid segment by setting 4330 * its signature word (0x13) high_byte to 0b. This can be 4331 * done without an erase because flash erase sets all bits 4332 * to 1's. We can write 1's to 0's without an erase 4333 */ 4334 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4335 4336 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4337 4338 if (ret_val) 4339 goto release; 4340 4341 /* Great! Everything worked, we can now clear the cached entries. */ 4342 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4343 dev_spec->shadow_ram[i].modified = FALSE; 4344 dev_spec->shadow_ram[i].value = 0xFFFF; 4345 } 4346 4347release: 4348 nvm->ops.release(hw); 4349 4350 /* Reload the EEPROM, or else modifications will not appear 4351 * until after the next adapter reset. 4352 */ 4353 if (!ret_val) { 4354 nvm->ops.reload(hw); 4355 msec_delay(10); 4356 } 4357 4358out: 4359 if (ret_val) 4360 DEBUGOUT1("NVM update error: %d\n", ret_val); 4361 4362 return ret_val; 4363} 4364 4365/** 4366 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4367 * @hw: pointer to the HW structure 4368 * 4369 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4370 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4371 * calculated, in which case we need to calculate the checksum and set bit 6. 4372 **/ 4373static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4374{ 4375 s32 ret_val; 4376 u16 data; 4377 u16 word; 4378 u16 valid_csum_mask; 4379 4380 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 4381 4382 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4383 * the checksum needs to be fixed. This bit is an indication that 4384 * the NVM was prepared by OEM software and did not calculate 4385 * the checksum...a likely scenario. 4386 */ 4387 switch (hw->mac.type) { 4388 case e1000_pch_lpt: 4389 case e1000_pch_spt: 4390 word = NVM_COMPAT; 4391 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4392 break; 4393 default: 4394 word = NVM_FUTURE_INIT_WORD1; 4395 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4396 break; 4397 } 4398 4399 ret_val = hw->nvm.ops.read(hw, word, 1, &data); 4400 if (ret_val) 4401 return ret_val; 4402 4403 if (!(data & valid_csum_mask)) { 4404 data |= valid_csum_mask; 4405 ret_val = hw->nvm.ops.write(hw, word, 1, &data); 4406 if (ret_val) 4407 return ret_val; 4408 ret_val = hw->nvm.ops.update(hw); 4409 if (ret_val) 4410 return ret_val; 4411 } 4412 4413 return e1000_validate_nvm_checksum_generic(hw); 4414} 4415 4416/** 4417 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4418 * @hw: pointer to the HW structure 4419 * @offset: The offset (in bytes) of the byte/word to read. 4420 * @size: Size of data to read, 1=byte 2=word 4421 * @data: The byte(s) to write to the NVM. 4422 * 4423 * Writes one/two bytes to the NVM using the flash access registers. 4424 **/ 4425static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4426 u8 size, u16 data) 4427{ 4428 union ich8_hws_flash_status hsfsts; 4429 union ich8_hws_flash_ctrl hsflctl; 4430 u32 flash_linear_addr; 4431 u32 flash_data = 0; 4432 s32 ret_val; 4433 u8 count = 0; 4434 4435 DEBUGFUNC("e1000_write_ich8_data"); 4436 4437 if (hw->mac.type == e1000_pch_spt) { 4438 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4439 return -E1000_ERR_NVM; 4440 } else { 4441 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4442 return -E1000_ERR_NVM; 4443 } 4444 4445 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4446 hw->nvm.flash_base_addr); 4447 4448 do { 4449 usec_delay(1); 4450 /* Steps */ 4451 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4452 if (ret_val != E1000_SUCCESS) 4453 break; 4454 /* In SPT, This register is in Lan memory space, not 4455 * flash. Therefore, only 32 bit access is supported 4456 */ 4457 if (hw->mac.type == e1000_pch_spt) 4458 hsflctl.regval = 4459 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; 4460 else 4461 hsflctl.regval = 4462 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 4463 4464 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4465 hsflctl.hsf_ctrl.fldbcount = size - 1; 4466 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4467 /* In SPT, This register is in Lan memory space, 4468 * not flash. Therefore, only 32 bit access is 4469 * supported 4470 */ 4471 if (hw->mac.type == e1000_pch_spt) 4472 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4473 hsflctl.regval << 16); 4474 else 4475 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4476 hsflctl.regval); 4477 4478 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4479 4480 if (size == 1) 4481 flash_data = (u32)data & 0x00FF; 4482 else 4483 flash_data = (u32)data; 4484 4485 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 4486 4487 /* check if FCERR is set to 1 , if set to 1, clear it 4488 * and try the whole sequence a few more times else done 4489 */ 4490 ret_val = 4491 e1000_flash_cycle_ich8lan(hw, 4492 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4493 if (ret_val == E1000_SUCCESS) 4494 break; 4495 4496 /* If we're here, then things are most likely 4497 * completely hosed, but if the error condition 4498 * is detected, it won't hurt to give it another 4499 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4500 */ 4501 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4502 if (hsfsts.hsf_status.flcerr) 4503 /* Repeat for some time before giving up. */ 4504 continue; 4505 if (!hsfsts.hsf_status.flcdone) { 4506 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4507 break; 4508 } 4509 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4510 4511 return ret_val; 4512} 4513 4514/** 4515* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4516* @hw: pointer to the HW structure 4517* @offset: The offset (in bytes) of the dwords to read. 4518* @data: The 4 bytes to write to the NVM. 4519* 4520* Writes one/two/four bytes to the NVM using the flash access registers. 4521**/ 4522static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4523 u32 data) 4524{ 4525 union ich8_hws_flash_status hsfsts; 4526 union ich8_hws_flash_ctrl hsflctl; 4527 u32 flash_linear_addr; 4528 s32 ret_val; 4529 u8 count = 0; 4530 4531 DEBUGFUNC("e1000_write_flash_data32_ich8lan"); 4532 4533 if (hw->mac.type == e1000_pch_spt) { 4534 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4535 return -E1000_ERR_NVM; 4536 } 4537 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4538 hw->nvm.flash_base_addr); 4539 do { 4540 usec_delay(1); 4541 /* Steps */ 4542 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4543 if (ret_val != E1000_SUCCESS) 4544 break; 4545 4546 /* In SPT, This register is in Lan memory space, not 4547 * flash. Therefore, only 32 bit access is supported 4548 */ 4549 if (hw->mac.type == e1000_pch_spt) 4550 hsflctl.regval = E1000_READ_FLASH_REG(hw, 4551 ICH_FLASH_HSFSTS) 4552 >> 16; 4553 else 4554 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 4555 ICH_FLASH_HSFCTL); 4556 4557 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4558 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4559 4560 /* In SPT, This register is in Lan memory space, 4561 * not flash. Therefore, only 32 bit access is 4562 * supported 4563 */ 4564 if (hw->mac.type == e1000_pch_spt) 4565 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4566 hsflctl.regval << 16); 4567 else 4568 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4569 hsflctl.regval); 4570 4571 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 4572 4573 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data); 4574 4575 /* check if FCERR is set to 1 , if set to 1, clear it 4576 * and try the whole sequence a few more times else done 4577 */ 4578 ret_val = e1000_flash_cycle_ich8lan(hw, 4579 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4580 4581 if (ret_val == E1000_SUCCESS) 4582 break; 4583 4584 /* If we're here, then things are most likely 4585 * completely hosed, but if the error condition 4586 * is detected, it won't hurt to give it another 4587 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4588 */ 4589 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4590 4591 if (hsfsts.hsf_status.flcerr) 4592 /* Repeat for some time before giving up. */ 4593 continue; 4594 if (!hsfsts.hsf_status.flcdone) { 4595 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); 4596 break; 4597 } 4598 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4599 4600 return ret_val; 4601} 4602 4603/** 4604 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4605 * @hw: pointer to the HW structure 4606 * @offset: The index of the byte to read. 4607 * @data: The byte to write to the NVM. 4608 * 4609 * Writes a single byte to the NVM using the flash access registers. 4610 **/ 4611static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4612 u8 data) 4613{ 4614 u16 word = (u16)data; 4615 4616 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 4617 4618 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4619} 4620 4621/** 4622* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4623* @hw: pointer to the HW structure 4624* @offset: The offset of the word to write. 4625* @dword: The dword to write to the NVM. 4626* 4627* Writes a single dword to the NVM using the flash access registers. 4628* Goes through a retry algorithm before giving up. 4629**/ 4630static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4631 u32 offset, u32 dword) 4632{ 4633 s32 ret_val; 4634 u16 program_retries; 4635 4636 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan"); 4637 4638 /* Must convert word offset into bytes. */ 4639 offset <<= 1; 4640 4641 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4642 4643 if (!ret_val) 4644 return ret_val; 4645 for (program_retries = 0; program_retries < 100; program_retries++) { 4646 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset); 4647 usec_delay(100); 4648 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4649 if (ret_val == E1000_SUCCESS) 4650 break; 4651 } 4652 if (program_retries == 100) 4653 return -E1000_ERR_NVM; 4654 4655 return E1000_SUCCESS; 4656} 4657 4658/** 4659 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4660 * @hw: pointer to the HW structure 4661 * @offset: The offset of the byte to write. 4662 * @byte: The byte to write to the NVM. 4663 * 4664 * Writes a single byte to the NVM using the flash access registers. 4665 * Goes through a retry algorithm before giving up. 4666 **/ 4667static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4668 u32 offset, u8 byte) 4669{ 4670 s32 ret_val; 4671 u16 program_retries; 4672 4673 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 4674 4675 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4676 if (!ret_val) 4677 return ret_val; 4678 4679 for (program_retries = 0; program_retries < 100; program_retries++) { 4680 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 4681 usec_delay(100); 4682 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4683 if (ret_val == E1000_SUCCESS) 4684 break; 4685 } 4686 if (program_retries == 100) 4687 return -E1000_ERR_NVM; 4688 4689 return E1000_SUCCESS; 4690} 4691 4692/** 4693 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4694 * @hw: pointer to the HW structure 4695 * @bank: 0 for first bank, 1 for second bank, etc. 4696 * 4697 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4698 * bank N is 4096 * N + flash_reg_addr. 4699 **/ 4700static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4701{ 4702 struct e1000_nvm_info *nvm = &hw->nvm; 4703 union ich8_hws_flash_status hsfsts; 4704 union ich8_hws_flash_ctrl hsflctl; 4705 u32 flash_linear_addr; 4706 /* bank size is in 16bit words - adjust to bytes */ 4707 u32 flash_bank_size = nvm->flash_bank_size * 2; 4708 s32 ret_val; 4709 s32 count = 0; 4710 s32 j, iteration, sector_size; 4711 4712 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 4713 4714 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 4715 4716 /* Determine HW Sector size: Read BERASE bits of hw flash status 4717 * register 4718 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4719 * consecutive sectors. The start index for the nth Hw sector 4720 * can be calculated as = bank * 4096 + n * 256 4721 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4722 * The start index for the nth Hw sector can be calculated 4723 * as = bank * 4096 4724 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4725 * (ich9 only, otherwise error condition) 4726 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4727 */ 4728 switch (hsfsts.hsf_status.berasesz) { 4729 case 0: 4730 /* Hw sector size 256 */ 4731 sector_size = ICH_FLASH_SEG_SIZE_256; 4732 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4733 break; 4734 case 1: 4735 sector_size = ICH_FLASH_SEG_SIZE_4K; 4736 iteration = 1; 4737 break; 4738 case 2: 4739 sector_size = ICH_FLASH_SEG_SIZE_8K; 4740 iteration = 1; 4741 break; 4742 case 3: 4743 sector_size = ICH_FLASH_SEG_SIZE_64K; 4744 iteration = 1; 4745 break; 4746 default: 4747 return -E1000_ERR_NVM; 4748 } 4749 4750 /* Start with the base address, then add the sector offset. */ 4751 flash_linear_addr = hw->nvm.flash_base_addr; 4752 flash_linear_addr += (bank) ? flash_bank_size : 0; 4753 4754 for (j = 0; j < iteration; j++) { 4755 do { 4756 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4757 4758 /* Steps */ 4759 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4760 if (ret_val) 4761 return ret_val; 4762 4763 /* Write a value 11 (block Erase) in Flash 4764 * Cycle field in hw flash control 4765 */ 4766 if (hw->mac.type == e1000_pch_spt) 4767 hsflctl.regval = 4768 E1000_READ_FLASH_REG(hw, 4769 ICH_FLASH_HSFSTS)>>16; 4770 else 4771 hsflctl.regval = 4772 E1000_READ_FLASH_REG16(hw, 4773 ICH_FLASH_HSFCTL); 4774 4775 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4776 if (hw->mac.type == e1000_pch_spt) 4777 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, 4778 hsflctl.regval << 16); 4779 else 4780 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 4781 hsflctl.regval); 4782 4783 /* Write the last 24 bits of an index within the 4784 * block into Flash Linear address field in Flash 4785 * Address. 4786 */ 4787 flash_linear_addr += (j * sector_size); 4788 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 4789 flash_linear_addr); 4790 4791 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4792 if (ret_val == E1000_SUCCESS) 4793 break; 4794 4795 /* Check if FCERR is set to 1. If 1, 4796 * clear it and try the whole sequence 4797 * a few more times else Done 4798 */ 4799 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 4800 ICH_FLASH_HSFSTS); 4801 if (hsfsts.hsf_status.flcerr) 4802 /* repeat for some time before giving up */ 4803 continue; 4804 else if (!hsfsts.hsf_status.flcdone) 4805 return ret_val; 4806 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4807 } 4808 4809 return E1000_SUCCESS; 4810} 4811 4812/** 4813 * e1000_valid_led_default_ich8lan - Set the default LED settings 4814 * @hw: pointer to the HW structure 4815 * @data: Pointer to the LED settings 4816 * 4817 * Reads the LED default settings from the NVM to data. If the NVM LED 4818 * settings is all 0's or F's, set the LED default to a valid LED default 4819 * setting. 4820 **/ 4821static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4822{ 4823 s32 ret_val; 4824 4825 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 4826 4827 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 4828 if (ret_val) { 4829 DEBUGOUT("NVM Read Error\n"); 4830 return ret_val; 4831 } 4832 4833 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4834 *data = ID_LED_DEFAULT_ICH8LAN; 4835 4836 return E1000_SUCCESS; 4837} 4838 4839/** 4840 * e1000_id_led_init_pchlan - store LED configurations 4841 * @hw: pointer to the HW structure 4842 * 4843 * PCH does not control LEDs via the LEDCTL register, rather it uses 4844 * the PHY LED configuration register. 4845 * 4846 * PCH also does not have an "always on" or "always off" mode which 4847 * complicates the ID feature. Instead of using the "on" mode to indicate 4848 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 4849 * use "link_up" mode. The LEDs will still ID on request if there is no 4850 * link based on logic in e1000_led_[on|off]_pchlan(). 4851 **/ 4852static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4853{ 4854 struct e1000_mac_info *mac = &hw->mac; 4855 s32 ret_val; 4856 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4857 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4858 u16 data, i, temp, shift; 4859 4860 DEBUGFUNC("e1000_id_led_init_pchlan"); 4861 4862 /* Get default ID LED modes */ 4863 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4864 if (ret_val) 4865 return ret_val; 4866 4867 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 4868 mac->ledctl_mode1 = mac->ledctl_default; 4869 mac->ledctl_mode2 = mac->ledctl_default; 4870 4871 for (i = 0; i < 4; i++) { 4872 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4873 shift = (i * 5); 4874 switch (temp) { 4875 case ID_LED_ON1_DEF2: 4876 case ID_LED_ON1_ON2: 4877 case ID_LED_ON1_OFF2: 4878 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4879 mac->ledctl_mode1 |= (ledctl_on << shift); 4880 break; 4881 case ID_LED_OFF1_DEF2: 4882 case ID_LED_OFF1_ON2: 4883 case ID_LED_OFF1_OFF2: 4884 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4885 mac->ledctl_mode1 |= (ledctl_off << shift); 4886 break; 4887 default: 4888 /* Do nothing */ 4889 break; 4890 } 4891 switch (temp) { 4892 case ID_LED_DEF1_ON2: 4893 case ID_LED_ON1_ON2: 4894 case ID_LED_OFF1_ON2: 4895 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4896 mac->ledctl_mode2 |= (ledctl_on << shift); 4897 break; 4898 case ID_LED_DEF1_OFF2: 4899 case ID_LED_ON1_OFF2: 4900 case ID_LED_OFF1_OFF2: 4901 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4902 mac->ledctl_mode2 |= (ledctl_off << shift); 4903 break; 4904 default: 4905 /* Do nothing */ 4906 break; 4907 } 4908 } 4909 4910 return E1000_SUCCESS; 4911} 4912 4913/** 4914 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4915 * @hw: pointer to the HW structure 4916 * 4917 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4918 * register, so the bus width is hard coded. 4919 **/ 4920static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4921{ 4922 struct e1000_bus_info *bus = &hw->bus; 4923 s32 ret_val; 4924 4925 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 4926 4927 ret_val = e1000_get_bus_info_pcie_generic(hw); 4928 4929 /* ICH devices are "PCI Express"-ish. They have 4930 * a configuration space, but do not contain 4931 * PCI Express Capability registers, so bus width 4932 * must be hardcoded. 4933 */ 4934 if (bus->width == e1000_bus_width_unknown) 4935 bus->width = e1000_bus_width_pcie_x1; 4936 4937 return ret_val; 4938} 4939 4940/** 4941 * e1000_reset_hw_ich8lan - Reset the hardware 4942 * @hw: pointer to the HW structure 4943 * 4944 * Does a full reset of the hardware which includes a reset of the PHY and 4945 * MAC. 4946 **/ 4947static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4948{ 4949 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4950 u16 kum_cfg; 4951 u32 ctrl, reg; 4952 s32 ret_val; 4953 4954 DEBUGFUNC("e1000_reset_hw_ich8lan"); 4955 4956 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4957 * on the last TLP read/write transaction when MAC is reset. 4958 */ 4959 ret_val = e1000_disable_pcie_master_generic(hw); 4960 if (ret_val) 4961 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 4962 4963 DEBUGOUT("Masking off all interrupts\n"); 4964 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4965 4966 /* Disable the Transmit and Receive units. Then delay to allow 4967 * any pending transactions to complete before we hit the MAC 4968 * with the global reset. 4969 */ 4970 E1000_WRITE_REG(hw, E1000_RCTL, 0); 4971 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 4972 E1000_WRITE_FLUSH(hw); 4973 4974 msec_delay(10); 4975 4976 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4977 if (hw->mac.type == e1000_ich8lan) { 4978 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4979 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 4980 /* Set Packet Buffer Size to 16k. */ 4981 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 4982 } 4983 4984 if (hw->mac.type == e1000_pchlan) { 4985 /* Save the NVM K1 bit setting*/ 4986 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4987 if (ret_val) 4988 return ret_val; 4989 4990 if (kum_cfg & E1000_NVM_K1_ENABLE) 4991 dev_spec->nvm_k1_enabled = TRUE; 4992 else 4993 dev_spec->nvm_k1_enabled = FALSE; 4994 } 4995 4996 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4997 4998 if (!hw->phy.ops.check_reset_block(hw)) { 4999 /* Full-chip reset requires MAC and PHY reset at the same 5000 * time to make sure the interface between MAC and the 5001 * external PHY is reset. 5002 */ 5003 ctrl |= E1000_CTRL_PHY_RST; 5004 5005 /* Gate automatic PHY configuration by hardware on 5006 * non-managed 82579 5007 */ 5008 if ((hw->mac.type == e1000_pch2lan) && 5009 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 5010 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 5011 } 5012 ret_val = e1000_acquire_swflag_ich8lan(hw); 5013 DEBUGOUT("Issuing a global reset to ich8lan\n"); 5014 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 5015 /* cannot issue a flush here because it hangs the hardware */ 5016 msec_delay(20); 5017 5018 /* Set Phy Config Counter to 50msec */ 5019 if (hw->mac.type == e1000_pch2lan) { 5020 reg = E1000_READ_REG(hw, E1000_FEXTNVM3); 5021 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 5022 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 5023 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); 5024 } 5025 5026 if (!ret_val) 5027 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 5028 5029 if (ctrl & E1000_CTRL_PHY_RST) { 5030 ret_val = hw->phy.ops.get_cfg_done(hw); 5031 if (ret_val) 5032 return ret_val; 5033 5034 ret_val = e1000_post_phy_reset_ich8lan(hw); 5035 if (ret_val) 5036 return ret_val; 5037 } 5038 5039 /* For PCH, this write will make sure that any noise 5040 * will be detected as a CRC error and be dropped rather than show up 5041 * as a bad packet to the DMA engine. 5042 */ 5043 if (hw->mac.type == e1000_pchlan) 5044 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 5045 5046 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 5047 E1000_READ_REG(hw, E1000_ICR); 5048 5049 reg = E1000_READ_REG(hw, E1000_KABGTXD); 5050 reg |= E1000_KABGTXD_BGSQLBIAS; 5051 E1000_WRITE_REG(hw, E1000_KABGTXD, reg); 5052 5053 return E1000_SUCCESS; 5054} 5055 5056/** 5057 * e1000_init_hw_ich8lan - Initialize the hardware 5058 * @hw: pointer to the HW structure 5059 * 5060 * Prepares the hardware for transmit and receive by doing the following: 5061 * - initialize hardware bits 5062 * - initialize LED identification 5063 * - setup receive address registers 5064 * - setup flow control 5065 * - setup transmit descriptors 5066 * - clear statistics 5067 **/ 5068static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 5069{ 5070 struct e1000_mac_info *mac = &hw->mac; 5071 u32 ctrl_ext, txdctl, snoop; 5072 s32 ret_val; 5073 u16 i; 5074 5075 DEBUGFUNC("e1000_init_hw_ich8lan"); 5076 5077 e1000_initialize_hw_bits_ich8lan(hw); 5078 5079 /* Initialize identification LED */ 5080 ret_val = mac->ops.id_led_init(hw); 5081 /* An error is not fatal and we should not stop init due to this */ 5082 if (ret_val) 5083 DEBUGOUT("Error initializing identification LED\n"); 5084 5085 /* Setup the receive address. */ 5086 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 5087 5088 /* Zero out the Multicast HASH table */ 5089 DEBUGOUT("Zeroing the MTA\n"); 5090 for (i = 0; i < mac->mta_reg_count; i++) 5091 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 5092 5093 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 5094 * the ME. Disable wakeup by clearing the host wakeup bit. 5095 * Reset the phy after disabling host wakeup to reset the Rx buffer. 5096 */ 5097 if (hw->phy.type == e1000_phy_82578) { 5098 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); 5099 i &= ~BM_WUC_HOST_WU_BIT; 5100 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); 5101 ret_val = e1000_phy_hw_reset_ich8lan(hw); 5102 if (ret_val) 5103 return ret_val; 5104 } 5105 5106 /* Setup link and flow control */ 5107 ret_val = mac->ops.setup_link(hw); 5108 5109 /* Set the transmit descriptor write-back policy for both queues */ 5110 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5111 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5112 E1000_TXDCTL_FULL_TX_DESC_WB); 5113 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5114 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5115 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 5116 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5117 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5118 E1000_TXDCTL_FULL_TX_DESC_WB); 5119 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5120 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5121 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 5122 5123 /* ICH8 has opposite polarity of no_snoop bits. 5124 * By default, we should use snoop behavior. 5125 */ 5126 if (mac->type == e1000_ich8lan) 5127 snoop = PCIE_ICH8_SNOOP_ALL; 5128 else 5129 snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 5130 e1000_set_pcie_no_snoop_generic(hw, snoop); 5131 5132 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5133 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5134 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5135 5136 /* Clear all of the statistics registers (clear on read). It is 5137 * important that we do this after we have tried to establish link 5138 * because the symbol error count will increment wildly if there 5139 * is no link. 5140 */ 5141 e1000_clear_hw_cntrs_ich8lan(hw); 5142 5143 return ret_val; 5144} 5145 5146/** 5147 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5148 * @hw: pointer to the HW structure 5149 * 5150 * Sets/Clears required hardware bits necessary for correctly setting up the 5151 * hardware for transmit and receive. 5152 **/ 5153static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5154{ 5155 u32 reg; 5156 5157 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 5158 5159 /* Extended Device Control */ 5160 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 5161 reg |= (1 << 22); 5162 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5163 if (hw->mac.type >= e1000_pchlan) 5164 reg |= E1000_CTRL_EXT_PHYPDEN; 5165 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 5166 5167 /* Transmit Descriptor Control 0 */ 5168 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 5169 reg |= (1 << 22); 5170 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 5171 5172 /* Transmit Descriptor Control 1 */ 5173 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 5174 reg |= (1 << 22); 5175 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 5176 5177 /* Transmit Arbitration Control 0 */ 5178 reg = E1000_READ_REG(hw, E1000_TARC(0)); 5179 if (hw->mac.type == e1000_ich8lan) 5180 reg |= (1 << 28) | (1 << 29); 5181 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 5182 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 5183 5184 /* Transmit Arbitration Control 1 */ 5185 reg = E1000_READ_REG(hw, E1000_TARC(1)); 5186 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 5187 reg &= ~(1 << 28); 5188 else 5189 reg |= (1 << 28); 5190 reg |= (1 << 24) | (1 << 26) | (1 << 30); 5191 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 5192 5193 /* Device Status */ 5194 if (hw->mac.type == e1000_ich8lan) { 5195 reg = E1000_READ_REG(hw, E1000_STATUS); 5196 reg &= ~(1 << 31); 5197 E1000_WRITE_REG(hw, E1000_STATUS, reg); 5198 } 5199 5200 /* work-around descriptor data corruption issue during nfs v2 udp 5201 * traffic, just disable the nfs filtering capability 5202 */ 5203 reg = E1000_READ_REG(hw, E1000_RFCTL); 5204 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5205 5206 /* Disable IPv6 extension header parsing because some malformed 5207 * IPv6 headers can hang the Rx. 5208 */ 5209 if (hw->mac.type == e1000_ich8lan) 5210 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5211 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 5212 5213 /* Enable ECC on Lynxpoint */ 5214 if ((hw->mac.type == e1000_pch_lpt) || 5215 (hw->mac.type == e1000_pch_spt)) { 5216 reg = E1000_READ_REG(hw, E1000_PBECCSTS); 5217 reg |= E1000_PBECCSTS_ECC_ENABLE; 5218 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); 5219 5220 reg = E1000_READ_REG(hw, E1000_CTRL); 5221 reg |= E1000_CTRL_MEHE; 5222 E1000_WRITE_REG(hw, E1000_CTRL, reg); 5223 } 5224 5225 return; 5226} 5227 5228/** 5229 * e1000_setup_link_ich8lan - Setup flow control and link settings 5230 * @hw: pointer to the HW structure 5231 * 5232 * Determines which flow control settings to use, then configures flow 5233 * control. Calls the appropriate media-specific link configuration 5234 * function. Assuming the adapter has a valid link partner, a valid link 5235 * should be established. Assumes the hardware has previously been reset 5236 * and the transmitter and receiver are not enabled. 5237 **/ 5238static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5239{ 5240 s32 ret_val; 5241 5242 DEBUGFUNC("e1000_setup_link_ich8lan"); 5243 5244 if (hw->phy.ops.check_reset_block(hw)) 5245 return E1000_SUCCESS; 5246 5247 /* ICH parts do not have a word in the NVM to determine 5248 * the default flow control setting, so we explicitly 5249 * set it to full. 5250 */ 5251 if (hw->fc.requested_mode == e1000_fc_default) 5252 hw->fc.requested_mode = e1000_fc_full; 5253 5254 /* Save off the requested flow control mode for use later. Depending 5255 * on the link partner's capabilities, we may or may not use this mode. 5256 */ 5257 hw->fc.current_mode = hw->fc.requested_mode; 5258 5259 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 5260 hw->fc.current_mode); 5261 5262 /* Continue to configure the copper link. */ 5263 ret_val = hw->mac.ops.setup_physical_interface(hw); 5264 if (ret_val) 5265 return ret_val; 5266 5267 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 5268 if ((hw->phy.type == e1000_phy_82578) || 5269 (hw->phy.type == e1000_phy_82579) || 5270 (hw->phy.type == e1000_phy_i217) || 5271 (hw->phy.type == e1000_phy_82577)) { 5272 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 5273 5274 ret_val = hw->phy.ops.write_reg(hw, 5275 PHY_REG(BM_PORT_CTRL_PAGE, 27), 5276 hw->fc.pause_time); 5277 if (ret_val) 5278 return ret_val; 5279 } 5280 5281 return e1000_set_fc_watermarks_generic(hw); 5282} 5283 5284/** 5285 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5286 * @hw: pointer to the HW structure 5287 * 5288 * Configures the kumeran interface to the PHY to wait the appropriate time 5289 * when polling the PHY, then call the generic setup_copper_link to finish 5290 * configuring the copper link. 5291 **/ 5292static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5293{ 5294 u32 ctrl; 5295 s32 ret_val; 5296 u16 reg_data; 5297 5298 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 5299 5300 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5301 ctrl |= E1000_CTRL_SLU; 5302 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5303 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5304 5305 /* Set the mac to wait the maximum time between each iteration 5306 * and increase the max iterations when polling the phy; 5307 * this fixes erroneous timeouts at 10Mbps. 5308 */ 5309 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 5310 0xFFFF); 5311 if (ret_val) 5312 return ret_val; 5313 ret_val = e1000_read_kmrn_reg_generic(hw, 5314 E1000_KMRNCTRLSTA_INBAND_PARAM, 5315 ®_data); 5316 if (ret_val) 5317 return ret_val; 5318 reg_data |= 0x3F; 5319 ret_val = e1000_write_kmrn_reg_generic(hw, 5320 E1000_KMRNCTRLSTA_INBAND_PARAM, 5321 reg_data); 5322 if (ret_val) 5323 return ret_val; 5324 5325 switch (hw->phy.type) { 5326 case e1000_phy_igp_3: 5327 ret_val = e1000_copper_link_setup_igp(hw); 5328 if (ret_val) 5329 return ret_val; 5330 break; 5331 case e1000_phy_bm: 5332 case e1000_phy_82578: 5333 ret_val = e1000_copper_link_setup_m88(hw); 5334 if (ret_val) 5335 return ret_val; 5336 break; 5337 case e1000_phy_82577: 5338 case e1000_phy_82579: 5339 ret_val = e1000_copper_link_setup_82577(hw); 5340 if (ret_val) 5341 return ret_val; 5342 break; 5343 case e1000_phy_ife: 5344 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 5345 ®_data); 5346 if (ret_val) 5347 return ret_val; 5348 5349 reg_data &= ~IFE_PMC_AUTO_MDIX; 5350 5351 switch (hw->phy.mdix) { 5352 case 1: 5353 reg_data &= ~IFE_PMC_FORCE_MDIX; 5354 break; 5355 case 2: 5356 reg_data |= IFE_PMC_FORCE_MDIX; 5357 break; 5358 case 0: 5359 default: 5360 reg_data |= IFE_PMC_AUTO_MDIX; 5361 break; 5362 } 5363 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 5364 reg_data); 5365 if (ret_val) 5366 return ret_val; 5367 break; 5368 default: 5369 break; 5370 } 5371 5372 return e1000_setup_copper_link_generic(hw); 5373} 5374 5375/** 5376 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5377 * @hw: pointer to the HW structure 5378 * 5379 * Calls the PHY specific link setup function and then calls the 5380 * generic setup_copper_link to finish configuring the link for 5381 * Lynxpoint PCH devices 5382 **/ 5383static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5384{ 5385 u32 ctrl; 5386 s32 ret_val; 5387 5388 DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); 5389 5390 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5391 ctrl |= E1000_CTRL_SLU; 5392 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5393 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5394 5395 ret_val = e1000_copper_link_setup_82577(hw); 5396 if (ret_val) 5397 return ret_val; 5398 5399 return e1000_setup_copper_link_generic(hw); 5400} 5401 5402/** 5403 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5404 * @hw: pointer to the HW structure 5405 * @speed: pointer to store current link speed 5406 * @duplex: pointer to store the current link duplex 5407 * 5408 * Calls the generic get_speed_and_duplex to retrieve the current link 5409 * information and then calls the Kumeran lock loss workaround for links at 5410 * gigabit speeds. 5411 **/ 5412static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5413 u16 *duplex) 5414{ 5415 s32 ret_val; 5416 5417 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 5418 5419 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 5420 if (ret_val) 5421 return ret_val; 5422 5423 if ((hw->mac.type == e1000_ich8lan) && 5424 (hw->phy.type == e1000_phy_igp_3) && 5425 (*speed == SPEED_1000)) { 5426 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5427 } 5428 5429 return ret_val; 5430} 5431 5432/** 5433 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5434 * @hw: pointer to the HW structure 5435 * 5436 * Work-around for 82566 Kumeran PCS lock loss: 5437 * On link status change (i.e. PCI reset, speed change) and link is up and 5438 * speed is gigabit- 5439 * 0) if workaround is optionally disabled do nothing 5440 * 1) wait 1ms for Kumeran link to come up 5441 * 2) check Kumeran Diagnostic register PCS lock loss bit 5442 * 3) if not set the link is locked (all is good), otherwise... 5443 * 4) reset the PHY 5444 * 5) repeat up to 10 times 5445 * Note: this is only called for IGP3 copper when speed is 1gb. 5446 **/ 5447static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5448{ 5449 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5450 u32 phy_ctrl; 5451 s32 ret_val; 5452 u16 i, data; 5453 bool link; 5454 5455 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 5456 5457 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5458 return E1000_SUCCESS; 5459 5460 /* Make sure link is up before proceeding. If not just return. 5461 * Attempting this while link is negotiating fouled up link 5462 * stability 5463 */ 5464 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 5465 if (!link) 5466 return E1000_SUCCESS; 5467 5468 for (i = 0; i < 10; i++) { 5469 /* read once to clear */ 5470 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5471 if (ret_val) 5472 return ret_val; 5473 /* and again to get new status */ 5474 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 5475 if (ret_val) 5476 return ret_val; 5477 5478 /* check for PCS lock */ 5479 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5480 return E1000_SUCCESS; 5481 5482 /* Issue PHY reset */ 5483 hw->phy.ops.reset(hw); 5484 msec_delay_irq(5); 5485 } 5486 /* Disable GigE link negotiation */ 5487 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5488 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5489 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5490 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5491 5492 /* Call gig speed drop workaround on Gig disable before accessing 5493 * any PHY registers 5494 */ 5495 e1000_gig_downshift_workaround_ich8lan(hw); 5496 5497 /* unable to acquire PCS lock */ 5498 return -E1000_ERR_PHY; 5499} 5500 5501/** 5502 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5503 * @hw: pointer to the HW structure 5504 * @state: boolean value used to set the current Kumeran workaround state 5505 * 5506 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 5507 * /disabled - FALSE). 5508 **/ 5509void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5510 bool state) 5511{ 5512 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5513 5514 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 5515 5516 if (hw->mac.type != e1000_ich8lan) { 5517 DEBUGOUT("Workaround applies to ICH8 only.\n"); 5518 return; 5519 } 5520 5521 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5522 5523 return; 5524} 5525 5526/** 5527 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5528 * @hw: pointer to the HW structure 5529 * 5530 * Workaround for 82566 power-down on D3 entry: 5531 * 1) disable gigabit link 5532 * 2) write VR power-down enable 5533 * 3) read it back 5534 * Continue if successful, else issue LCD reset and repeat 5535 **/ 5536void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5537{ 5538 u32 reg; 5539 u16 data; 5540 u8 retry = 0; 5541 5542 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 5543 5544 if (hw->phy.type != e1000_phy_igp_3) 5545 return; 5546 5547 /* Try the workaround twice (if needed) */ 5548 do { 5549 /* Disable link */ 5550 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 5551 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5552 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5553 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 5554 5555 /* Call gig speed drop workaround on Gig disable before 5556 * accessing any PHY registers 5557 */ 5558 if (hw->mac.type == e1000_ich8lan) 5559 e1000_gig_downshift_workaround_ich8lan(hw); 5560 5561 /* Write VR power-down enable */ 5562 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5563 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5564 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 5565 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5566 5567 /* Read it back and test */ 5568 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 5569 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5570 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5571 break; 5572 5573 /* Issue PHY reset and repeat at most one more time */ 5574 reg = E1000_READ_REG(hw, E1000_CTRL); 5575 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 5576 retry++; 5577 } while (retry); 5578} 5579 5580/** 5581 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5582 * @hw: pointer to the HW structure 5583 * 5584 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5585 * LPLU, Gig disable, MDIC PHY reset): 5586 * 1) Set Kumeran Near-end loopback 5587 * 2) Clear Kumeran Near-end loopback 5588 * Should only be called for ICH8[m] devices with any 1G Phy. 5589 **/ 5590void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5591{ 5592 s32 ret_val; 5593 u16 reg_data; 5594 5595 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 5596 5597 if ((hw->mac.type != e1000_ich8lan) || 5598 (hw->phy.type == e1000_phy_ife)) 5599 return; 5600 5601 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5602 ®_data); 5603 if (ret_val) 5604 return; 5605 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5606 ret_val = e1000_write_kmrn_reg_generic(hw, 5607 E1000_KMRNCTRLSTA_DIAG_OFFSET, 5608 reg_data); 5609 if (ret_val) 5610 return; 5611 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5612 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5613 reg_data); 5614} 5615 5616/** 5617 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5618 * @hw: pointer to the HW structure 5619 * 5620 * During S0 to Sx transition, it is possible the link remains at gig 5621 * instead of negotiating to a lower speed. Before going to Sx, set 5622 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5623 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5624 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5625 * needs to be written. 5626 * Parts that support (and are linked to a partner which support) EEE in 5627 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5628 * than 10Mbps w/o EEE. 5629 **/ 5630void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5631{ 5632 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5633 u32 phy_ctrl; 5634 s32 ret_val; 5635 5636 DEBUGFUNC("e1000_suspend_workarounds_ich8lan"); 5637 5638 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 5639 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5640 5641 if (hw->phy.type == e1000_phy_i217) { 5642 u16 phy_reg, device_id = hw->device_id; 5643 5644 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5645 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5646 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5647 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5648 (hw->mac.type == e1000_pch_spt)) { 5649 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); 5650 5651 E1000_WRITE_REG(hw, E1000_FEXTNVM6, 5652 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5653 } 5654 5655 ret_val = hw->phy.ops.acquire(hw); 5656 if (ret_val) 5657 goto out; 5658 5659 if (!dev_spec->eee_disable) { 5660 u16 eee_advert; 5661 5662 ret_val = 5663 e1000_read_emi_reg_locked(hw, 5664 I217_EEE_ADVERTISEMENT, 5665 &eee_advert); 5666 if (ret_val) 5667 goto release; 5668 5669 /* Disable LPLU if both link partners support 100BaseT 5670 * EEE and 100Full is advertised on both ends of the 5671 * link, and enable Auto Enable LPI since there will 5672 * be no driver to enable LPI while in Sx. 5673 */ 5674 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5675 (dev_spec->eee_lp_ability & 5676 I82579_EEE_100_SUPPORTED) && 5677 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5678 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5679 E1000_PHY_CTRL_NOND0A_LPLU); 5680 5681 /* Set Auto Enable LPI after link up */ 5682 hw->phy.ops.read_reg_locked(hw, 5683 I217_LPI_GPIO_CTRL, 5684 &phy_reg); 5685 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5686 hw->phy.ops.write_reg_locked(hw, 5687 I217_LPI_GPIO_CTRL, 5688 phy_reg); 5689 } 5690 } 5691 5692 /* For i217 Intel Rapid Start Technology support, 5693 * when the system is going into Sx and no manageability engine 5694 * is present, the driver must configure proxy to reset only on 5695 * power good. LPI (Low Power Idle) state must also reset only 5696 * on power good, as well as the MTA (Multicast table array). 5697 * The SMBus release must also be disabled on LCD reset. 5698 */ 5699 if (!(E1000_READ_REG(hw, E1000_FWSM) & 5700 E1000_ICH_FWSM_FW_VALID)) { 5701 /* Enable proxy to reset only on power good. */ 5702 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, 5703 &phy_reg); 5704 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5705 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 5706 phy_reg); 5707 5708 /* Set bit enable LPI (EEE) to reset only on 5709 * power good. 5710 */ 5711 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); 5712 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5713 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); 5714 5715 /* Disable the SMB release on LCD reset. */ 5716 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); 5717 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5718 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5719 } 5720 5721 /* Enable MTA to reset for Intel Rapid Start Technology 5722 * Support 5723 */ 5724 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); 5725 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5726 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5727 5728release: 5729 hw->phy.ops.release(hw); 5730 } 5731out: 5732 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 5733 5734 if (hw->mac.type == e1000_ich8lan) 5735 e1000_gig_downshift_workaround_ich8lan(hw); 5736 5737 if (hw->mac.type >= e1000_pchlan) { 5738 e1000_oem_bits_config_ich8lan(hw, FALSE); 5739 5740 /* Reset PHY to activate OEM bits on 82577/8 */ 5741 if (hw->mac.type == e1000_pchlan) 5742 e1000_phy_hw_reset_generic(hw); 5743 5744 ret_val = hw->phy.ops.acquire(hw); 5745 if (ret_val) 5746 return; 5747 e1000_write_smbus_addr(hw); 5748 hw->phy.ops.release(hw); 5749 } 5750 5751 return; 5752} 5753 5754/** 5755 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5756 * @hw: pointer to the HW structure 5757 * 5758 * During Sx to S0 transitions on non-managed devices or managed devices 5759 * on which PHY resets are not blocked, if the PHY registers cannot be 5760 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5761 * the PHY. 5762 * On i217, setup Intel Rapid Start Technology. 5763 **/ 5764u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5765{ 5766 s32 ret_val; 5767 5768 DEBUGFUNC("e1000_resume_workarounds_pchlan"); 5769 if (hw->mac.type < e1000_pch2lan) 5770 return E1000_SUCCESS; 5771 5772 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5773 if (ret_val) { 5774 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); 5775 return ret_val; 5776 } 5777 5778 /* For i217 Intel Rapid Start Technology support when the system 5779 * is transitioning from Sx and no manageability engine is present 5780 * configure SMBus to restore on reset, disable proxy, and enable 5781 * the reset on MTA (Multicast table array). 5782 */ 5783 if (hw->phy.type == e1000_phy_i217) { 5784 u16 phy_reg; 5785 5786 ret_val = hw->phy.ops.acquire(hw); 5787 if (ret_val) { 5788 DEBUGOUT("Failed to setup iRST\n"); 5789 return ret_val; 5790 } 5791 5792 /* Clear Auto Enable LPI after link up */ 5793 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5794 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5795 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5796 5797 if (!(E1000_READ_REG(hw, E1000_FWSM) & 5798 E1000_ICH_FWSM_FW_VALID)) { 5799 /* Restore clear on SMB if no manageability engine 5800 * is present 5801 */ 5802 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, 5803 &phy_reg); 5804 if (ret_val) 5805 goto release; 5806 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5807 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); 5808 5809 /* Disable Proxy */ 5810 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); 5811 } 5812 /* Enable reset on MTA */ 5813 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, 5814 &phy_reg); 5815 if (ret_val) 5816 goto release; 5817 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5818 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); 5819release: 5820 if (ret_val) 5821 DEBUGOUT1("Error %d in resume workarounds\n", ret_val); 5822 hw->phy.ops.release(hw); 5823 return ret_val; 5824 } 5825 return E1000_SUCCESS; 5826} 5827 5828/** 5829 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5830 * @hw: pointer to the HW structure 5831 * 5832 * Return the LED back to the default configuration. 5833 **/ 5834static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5835{ 5836 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 5837 5838 if (hw->phy.type == e1000_phy_ife) 5839 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5840 0); 5841 5842 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 5843 return E1000_SUCCESS; 5844} 5845 5846/** 5847 * e1000_led_on_ich8lan - Turn LEDs on 5848 * @hw: pointer to the HW structure 5849 * 5850 * Turn on the LEDs. 5851 **/ 5852static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5853{ 5854 DEBUGFUNC("e1000_led_on_ich8lan"); 5855 5856 if (hw->phy.type == e1000_phy_ife) 5857 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5858 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5859 5860 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 5861 return E1000_SUCCESS; 5862} 5863 5864/** 5865 * e1000_led_off_ich8lan - Turn LEDs off 5866 * @hw: pointer to the HW structure 5867 * 5868 * Turn off the LEDs. 5869 **/ 5870static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5871{ 5872 DEBUGFUNC("e1000_led_off_ich8lan"); 5873 5874 if (hw->phy.type == e1000_phy_ife) 5875 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5876 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 5877 5878 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 5879 return E1000_SUCCESS; 5880} 5881 5882/** 5883 * e1000_setup_led_pchlan - Configures SW controllable LED 5884 * @hw: pointer to the HW structure 5885 * 5886 * This prepares the SW controllable LED for use. 5887 **/ 5888static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5889{ 5890 DEBUGFUNC("e1000_setup_led_pchlan"); 5891 5892 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5893 (u16)hw->mac.ledctl_mode1); 5894} 5895 5896/** 5897 * e1000_cleanup_led_pchlan - Restore the default LED operation 5898 * @hw: pointer to the HW structure 5899 * 5900 * Return the LED back to the default configuration. 5901 **/ 5902static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5903{ 5904 DEBUGFUNC("e1000_cleanup_led_pchlan"); 5905 5906 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 5907 (u16)hw->mac.ledctl_default); 5908} 5909 5910/** 5911 * e1000_led_on_pchlan - Turn LEDs on 5912 * @hw: pointer to the HW structure 5913 * 5914 * Turn on the LEDs. 5915 **/ 5916static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5917{ 5918 u16 data = (u16)hw->mac.ledctl_mode2; 5919 u32 i, led; 5920 5921 DEBUGFUNC("e1000_led_on_pchlan"); 5922 5923 /* If no link, then turn LED on by setting the invert bit 5924 * for each LED that's mode is "link_up" in ledctl_mode2. 5925 */ 5926 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5927 for (i = 0; i < 3; i++) { 5928 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5929 if ((led & E1000_PHY_LED0_MODE_MASK) != 5930 E1000_LEDCTL_MODE_LINK_UP) 5931 continue; 5932 if (led & E1000_PHY_LED0_IVRT) 5933 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5934 else 5935 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5936 } 5937 } 5938 5939 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5940} 5941 5942/** 5943 * e1000_led_off_pchlan - Turn LEDs off 5944 * @hw: pointer to the HW structure 5945 * 5946 * Turn off the LEDs. 5947 **/ 5948static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5949{ 5950 u16 data = (u16)hw->mac.ledctl_mode1; 5951 u32 i, led; 5952 5953 DEBUGFUNC("e1000_led_off_pchlan"); 5954 5955 /* If no link, then turn LED off by clearing the invert bit 5956 * for each LED that's mode is "link_up" in ledctl_mode1. 5957 */ 5958 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 5959 for (i = 0; i < 3; i++) { 5960 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5961 if ((led & E1000_PHY_LED0_MODE_MASK) != 5962 E1000_LEDCTL_MODE_LINK_UP) 5963 continue; 5964 if (led & E1000_PHY_LED0_IVRT) 5965 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5966 else 5967 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5968 } 5969 } 5970 5971 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 5972} 5973 5974/** 5975 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5976 * @hw: pointer to the HW structure 5977 * 5978 * Read appropriate register for the config done bit for completion status 5979 * and configure the PHY through s/w for EEPROM-less parts. 5980 * 5981 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5982 * config done bit, so only an error is logged and continues. If we were 5983 * to return with error, EEPROM-less silicon would not be able to be reset 5984 * or change link. 5985 **/ 5986static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5987{ 5988 s32 ret_val = E1000_SUCCESS; 5989 u32 bank = 0; 5990 u32 status; 5991 5992 DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 5993 5994 e1000_get_cfg_done_generic(hw); 5995 5996 /* Wait for indication from h/w that it has completed basic config */ 5997 if (hw->mac.type >= e1000_ich10lan) { 5998 e1000_lan_init_done_ich8lan(hw); 5999 } else { 6000 ret_val = e1000_get_auto_rd_done_generic(hw); 6001 if (ret_val) { 6002 /* When auto config read does not complete, do not 6003 * return with an error. This can happen in situations 6004 * where there is no eeprom and prevents getting link. 6005 */ 6006 DEBUGOUT("Auto Read Done did not complete\n"); 6007 ret_val = E1000_SUCCESS; 6008 } 6009 } 6010 6011 /* Clear PHY Reset Asserted bit */ 6012 status = E1000_READ_REG(hw, E1000_STATUS); 6013 if (status & E1000_STATUS_PHYRA) 6014 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 6015 else 6016 DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 6017 6018 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 6019 if (hw->mac.type <= e1000_ich9lan) { 6020 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 6021 (hw->phy.type == e1000_phy_igp_3)) { 6022 e1000_phy_init_script_igp3(hw); 6023 } 6024 } else { 6025 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 6026 /* Maybe we should do a basic PHY config */ 6027 DEBUGOUT("EEPROM not present\n"); 6028 ret_val = -E1000_ERR_CONFIG; 6029 } 6030 } 6031 6032 return ret_val; 6033} 6034 6035/** 6036 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 6037 * @hw: pointer to the HW structure 6038 * 6039 * In the case of a PHY power down to save power, or to turn off link during a 6040 * driver unload, or wake on lan is not enabled, remove the link. 6041 **/ 6042static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 6043{ 6044 /* If the management interface is not enabled, then power down */ 6045 if (!(hw->mac.ops.check_mng_mode(hw) || 6046 hw->phy.ops.check_reset_block(hw))) 6047 e1000_power_down_phy_copper(hw); 6048 6049 return; 6050} 6051 6052/** 6053 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 6054 * @hw: pointer to the HW structure 6055 * 6056 * Clears hardware counters specific to the silicon family and calls 6057 * clear_hw_cntrs_generic to clear all general purpose counters. 6058 **/ 6059static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 6060{ 6061 u16 phy_data; 6062 s32 ret_val; 6063 6064 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 6065 6066 e1000_clear_hw_cntrs_base_generic(hw); 6067 6068 E1000_READ_REG(hw, E1000_ALGNERRC); 6069 E1000_READ_REG(hw, E1000_RXERRC); 6070 E1000_READ_REG(hw, E1000_TNCRS); 6071 E1000_READ_REG(hw, E1000_CEXTERR); 6072 E1000_READ_REG(hw, E1000_TSCTC); 6073 E1000_READ_REG(hw, E1000_TSCTFC); 6074 6075 E1000_READ_REG(hw, E1000_MGTPRC); 6076 E1000_READ_REG(hw, E1000_MGTPDC); 6077 E1000_READ_REG(hw, E1000_MGTPTC); 6078 6079 E1000_READ_REG(hw, E1000_IAC); 6080 E1000_READ_REG(hw, E1000_ICRXOC); 6081 6082 /* Clear PHY statistics registers */ 6083 if ((hw->phy.type == e1000_phy_82578) || 6084 (hw->phy.type == e1000_phy_82579) || 6085 (hw->phy.type == e1000_phy_i217) || 6086 (hw->phy.type == e1000_phy_82577)) { 6087 ret_val = hw->phy.ops.acquire(hw); 6088 if (ret_val) 6089 return; 6090 ret_val = hw->phy.ops.set_page(hw, 6091 HV_STATS_PAGE << IGP_PAGE_SHIFT); 6092 if (ret_val) 6093 goto release; 6094 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 6095 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 6096 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 6097 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 6098 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 6099 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 6100 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 6101 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 6102 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 6103 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 6104 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 6105 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 6106 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 6107 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 6108release: 6109 hw->phy.ops.release(hw); 6110 } 6111} 6112 6113