1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: releng/11.0/sys/dev/drm2/i915/i915_drv.c 296548 2016-03-08 20:33:02Z dumbbell $"); 32 33#include <dev/drm2/drmP.h> 34#include <dev/drm2/drm_pciids.h> 35#include <dev/drm2/i915/i915_drm.h> 36#include "dev/drm2/i915/i915_drv.h" 37#ifdef __linux__ 38#include "dev/drm2/i915/i915_trace.h" 39#endif 40#include "dev/drm2/i915/intel_drv.h" 41 42#include <dev/drm2/drm_crtc_helper.h> 43 44#include "fb_if.h" 45 46static int i915_modeset __read_mostly = 1; 47TUNABLE_INT("drm.i915.modeset", &i915_modeset); 48module_param_named(modeset, i915_modeset, int, 0400); 49MODULE_PARM_DESC(modeset, 50 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " 51 "1=on, -1=force vga console preference [default])"); 52 53#ifdef __linux__ 54unsigned int i915_fbpercrtc __always_unused = 0; 55module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); 56#endif 57 58int i915_panel_ignore_lid __read_mostly = 1; 59TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid); 60module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); 61MODULE_PARM_DESC(panel_ignore_lid, 62 "Override lid status (0=autodetect, 1=autodetect disabled [default], " 63 "-1=force lid closed, -2=force lid open)"); 64 65unsigned int i915_powersave __read_mostly = 1; 66TUNABLE_INT("drm.i915.powersave", &i915_powersave); 67module_param_named(powersave, i915_powersave, int, 0600); 68MODULE_PARM_DESC(powersave, 69 "Enable powersavings, fbc, downclocking, etc. (default: true)"); 70 71int i915_semaphores __read_mostly = -1; 72TUNABLE_INT("drm.i915.semaphores", &i915_semaphores); 73module_param_named(semaphores, i915_semaphores, int, 0600); 74MODULE_PARM_DESC(semaphores, 75 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); 76 77int i915_enable_rc6 __read_mostly = -1; 78TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6); 79module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); 80MODULE_PARM_DESC(i915_enable_rc6, 81 "Enable power-saving render C-state 6. " 82 "Different stages can be selected via bitmask values " 83 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " 84 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " 85 "default: -1 (use per-chip default)"); 86 87int i915_enable_fbc __read_mostly = -1; 88TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc); 89module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); 90MODULE_PARM_DESC(i915_enable_fbc, 91 "Enable frame buffer compression for power savings " 92 "(default: -1 (use per-chip default))"); 93 94unsigned int i915_lvds_downclock __read_mostly = 0; 95TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock); 96module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); 97MODULE_PARM_DESC(lvds_downclock, 98 "Use panel (LVDS/eDP) downclocking for power savings " 99 "(default: false)"); 100 101int i915_lvds_channel_mode __read_mostly; 102TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode); 103module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); 104MODULE_PARM_DESC(lvds_channel_mode, 105 "Specify LVDS channel mode " 106 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); 107 108int i915_panel_use_ssc __read_mostly = -1; 109TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc); 110module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); 111MODULE_PARM_DESC(lvds_use_ssc, 112 "Use Spread Spectrum Clock with panels [LVDS/eDP] " 113 "(default: auto from VBT)"); 114 115int i915_vbt_sdvo_panel_type __read_mostly = -1; 116TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type); 117module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); 118MODULE_PARM_DESC(vbt_sdvo_panel_type, 119 "Override/Ignore selection of SDVO panel mode in the VBT " 120 "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); 121 122static int i915_try_reset __read_mostly = true; 123TUNABLE_INT("drm.i915.try_reset", &i915_try_reset); 124module_param_named(reset, i915_try_reset, bool, 0600); 125MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); 126 127int i915_enable_hangcheck __read_mostly = true; 128TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck); 129module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); 130MODULE_PARM_DESC(enable_hangcheck, 131 "Periodically check GPU activity for detecting hangs. " 132 "WARNING: Disabling this can cause system wide hangs. " 133 "(default: true)"); 134 135int i915_enable_ppgtt __read_mostly = -1; 136TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt); 137module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); 138MODULE_PARM_DESC(i915_enable_ppgtt, 139 "Enable PPGTT (default: true)"); 140 141unsigned int i915_preliminary_hw_support __read_mostly = 0; 142TUNABLE_INT("drm.i915.enable_unsupported", &i915_preliminary_hw_support); 143module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); 144MODULE_PARM_DESC(preliminary_hw_support, 145 "Enable preliminary hardware support. " 146 "Enable Haswell and ValleyView Support. " 147 "(default: false)"); 148 149int intel_iommu_gfx_mapped = 0; 150TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped); 151 152static struct drm_driver driver; 153int intel_agp_enabled = 1; /* On FreeBSD, agp is a required dependency. */ 154 155#define INTEL_VGA_DEVICE(id, info_) { \ 156 .device = id, \ 157 .info = info_, \ 158} 159 160static const struct intel_device_info intel_i830_info = { 161 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, 162 .has_overlay = 1, .overlay_needs_physical = 1, 163}; 164 165static const struct intel_device_info intel_845g_info = { 166 .gen = 2, 167 .has_overlay = 1, .overlay_needs_physical = 1, 168}; 169 170static const struct intel_device_info intel_i85x_info = { 171 .gen = 2, .is_i85x = 1, .is_mobile = 1, 172 .cursor_needs_physical = 1, 173 .has_overlay = 1, .overlay_needs_physical = 1, 174}; 175 176static const struct intel_device_info intel_i865g_info = { 177 .gen = 2, 178 .has_overlay = 1, .overlay_needs_physical = 1, 179}; 180 181static const struct intel_device_info intel_i915g_info = { 182 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, 183 .has_overlay = 1, .overlay_needs_physical = 1, 184}; 185static const struct intel_device_info intel_i915gm_info = { 186 .gen = 3, .is_mobile = 1, 187 .cursor_needs_physical = 1, 188 .has_overlay = 1, .overlay_needs_physical = 1, 189 .supports_tv = 1, 190}; 191static const struct intel_device_info intel_i945g_info = { 192 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, 193 .has_overlay = 1, .overlay_needs_physical = 1, 194}; 195static const struct intel_device_info intel_i945gm_info = { 196 .gen = 3, .is_i945gm = 1, .is_mobile = 1, 197 .has_hotplug = 1, .cursor_needs_physical = 1, 198 .has_overlay = 1, .overlay_needs_physical = 1, 199 .supports_tv = 1, 200}; 201 202static const struct intel_device_info intel_i965g_info = { 203 .gen = 4, .is_broadwater = 1, 204 .has_hotplug = 1, 205 .has_overlay = 1, 206}; 207 208static const struct intel_device_info intel_i965gm_info = { 209 .gen = 4, .is_crestline = 1, 210 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 211 .has_overlay = 1, 212 .supports_tv = 1, 213}; 214 215static const struct intel_device_info intel_g33_info = { 216 .gen = 3, .is_g33 = 1, 217 .need_gfx_hws = 1, .has_hotplug = 1, 218 .has_overlay = 1, 219}; 220 221static const struct intel_device_info intel_g45_info = { 222 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, 223 .has_pipe_cxsr = 1, .has_hotplug = 1, 224 .has_bsd_ring = 1, 225}; 226 227static const struct intel_device_info intel_gm45_info = { 228 .gen = 4, .is_g4x = 1, 229 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 230 .has_pipe_cxsr = 1, .has_hotplug = 1, 231 .supports_tv = 1, 232 .has_bsd_ring = 1, 233}; 234 235static const struct intel_device_info intel_pineview_info = { 236 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, 237 .need_gfx_hws = 1, .has_hotplug = 1, 238 .has_overlay = 1, 239}; 240 241static const struct intel_device_info intel_ironlake_d_info = { 242 .gen = 5, 243 .need_gfx_hws = 1, .has_hotplug = 1, 244 .has_bsd_ring = 1, 245}; 246 247static const struct intel_device_info intel_ironlake_m_info = { 248 .gen = 5, .is_mobile = 1, 249 .need_gfx_hws = 1, .has_hotplug = 1, 250 .has_fbc = 1, 251 .has_bsd_ring = 1, 252}; 253 254static const struct intel_device_info intel_sandybridge_d_info = { 255 .gen = 6, 256 .need_gfx_hws = 1, .has_hotplug = 1, 257 .has_bsd_ring = 1, 258 .has_blt_ring = 1, 259 .has_llc = 1, 260 .has_force_wake = 1, 261}; 262 263static const struct intel_device_info intel_sandybridge_m_info = { 264 .gen = 6, .is_mobile = 1, 265 .need_gfx_hws = 1, .has_hotplug = 1, 266 .has_fbc = 1, 267 .has_bsd_ring = 1, 268 .has_blt_ring = 1, 269 .has_llc = 1, 270 .has_force_wake = 1, 271}; 272 273static const struct intel_device_info intel_ivybridge_d_info = { 274 .is_ivybridge = 1, .gen = 7, 275 .need_gfx_hws = 1, .has_hotplug = 1, 276 .has_bsd_ring = 1, 277 .has_blt_ring = 1, 278 .has_llc = 1, 279 .has_force_wake = 1, 280}; 281 282static const struct intel_device_info intel_ivybridge_m_info = { 283 .is_ivybridge = 1, .gen = 7, .is_mobile = 1, 284 .need_gfx_hws = 1, .has_hotplug = 1, 285 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ 286 .has_bsd_ring = 1, 287 .has_blt_ring = 1, 288 .has_llc = 1, 289 .has_force_wake = 1, 290}; 291 292static const struct intel_device_info intel_valleyview_m_info = { 293 .gen = 7, .is_mobile = 1, 294 .need_gfx_hws = 1, .has_hotplug = 1, 295 .has_fbc = 0, 296 .has_bsd_ring = 1, 297 .has_blt_ring = 1, 298 .is_valleyview = 1, 299}; 300 301static const struct intel_device_info intel_valleyview_d_info = { 302 .gen = 7, 303 .need_gfx_hws = 1, .has_hotplug = 1, 304 .has_fbc = 0, 305 .has_bsd_ring = 1, 306 .has_blt_ring = 1, 307 .is_valleyview = 1, 308}; 309 310static const struct intel_device_info intel_haswell_d_info = { 311 .is_haswell = 1, .gen = 7, 312 .need_gfx_hws = 1, .has_hotplug = 1, 313 .has_bsd_ring = 1, 314 .has_blt_ring = 1, 315 .has_llc = 1, 316 .has_force_wake = 1, 317}; 318 319static const struct intel_device_info intel_haswell_m_info = { 320 .is_haswell = 1, .gen = 7, .is_mobile = 1, 321 .need_gfx_hws = 1, .has_hotplug = 1, 322 .has_bsd_ring = 1, 323 .has_blt_ring = 1, 324 .has_llc = 1, 325 .has_force_wake = 1, 326}; 327 328/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */ 329static const drm_pci_id_list_t pciidlist[] = { 330 i915_PCI_IDS 331}; 332 333static const struct intel_gfx_device_id { 334 int device; 335 const struct intel_device_info *info; 336} i915_infolist[] = { /* aka */ 337 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ 338 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ 339 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ 340 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), 341 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ 342 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ 343 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ 344 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ 345 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ 346 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ 347 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ 348 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ 349 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ 350 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ 351 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ 352 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ 353 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ 354 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ 355 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ 356 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ 357 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ 358 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ 359 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ 360 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ 361 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ 362 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ 363 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ 364 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), 365 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), 366 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), 367 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), 368 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), 369 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), 370 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), 371 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), 372 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), 373 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), 374 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), 375 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ 376 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ 377 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ 378 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ 379 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ 380 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ 381 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ 382 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ 383 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ 384 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ 385 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ 386 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ 387 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ 388 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ 389 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ 390 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ 391 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ 392 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ 393 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ 394 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ 395 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ 396 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ 397 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ 398 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ 399 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ 400 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ 401 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ 402 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ 403 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ 404 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ 405 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ 406 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ 407 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ 408 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */ 409 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */ 410 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ 411 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */ 412 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */ 413 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ 414 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */ 415 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */ 416 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ 417 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), 418 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), 419 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), 420 {0, 0} 421}; 422 423#if defined(CONFIG_DRM_I915_KMS) 424MODULE_DEVICE_TABLE(pci, pciidlist); 425#endif 426 427void intel_detect_pch(struct drm_device *dev) 428{ 429 struct drm_i915_private *dev_priv = dev->dev_private; 430 device_t pch; 431 432 /* 433 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 434 * make graphics device passthrough work easy for VMM, that only 435 * need to expose ISA bridge to let driver know the real hardware 436 * underneath. This is a requirement from virtualization team. 437 */ 438 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA); 439 if (pch) { 440 if (pci_get_vendor(pch) == PCI_VENDOR_ID_INTEL) { 441 unsigned short id; 442 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 443 dev_priv->pch_id = id; 444 445 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 446 dev_priv->pch_type = PCH_IBX; 447 dev_priv->num_pch_pll = 2; 448 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 449 WARN_ON(!IS_GEN5(dev)); 450 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 451 dev_priv->pch_type = PCH_CPT; 452 dev_priv->num_pch_pll = 2; 453 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 454 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 455 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 456 /* PantherPoint is CPT compatible */ 457 dev_priv->pch_type = PCH_CPT; 458 dev_priv->num_pch_pll = 2; 459 DRM_DEBUG_KMS("Found PatherPoint PCH\n"); 460 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 461 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 462 dev_priv->pch_type = PCH_LPT; 463 dev_priv->num_pch_pll = 0; 464 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 465 WARN_ON(!IS_HASWELL(dev)); 466 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 467 dev_priv->pch_type = PCH_LPT; 468 dev_priv->num_pch_pll = 0; 469 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 470 WARN_ON(!IS_HASWELL(dev)); 471 } 472 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); 473 } 474 } 475} 476 477bool i915_semaphore_is_enabled(struct drm_device *dev) 478{ 479 if (INTEL_INFO(dev)->gen < 6) 480 return 0; 481 482 if (i915_semaphores >= 0) 483 return i915_semaphores; 484 485#ifdef CONFIG_INTEL_IOMMU 486 /* Enable semaphores on SNB when IO remapping is off */ 487 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 488 return false; 489#endif 490 491 return 1; 492} 493 494static int i915_drm_freeze(struct drm_device *dev) 495{ 496 struct drm_i915_private *dev_priv = dev->dev_private; 497 498 drm_kms_helper_poll_disable(dev); 499 500#ifdef __linux__ 501 pci_save_state(dev->pdev); 502#endif 503 504 /* If KMS is active, we do the leavevt stuff here */ 505 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 506 int error = i915_gem_idle(dev); 507 if (error) { 508 dev_err(dev->dev, 509 "GEM idle failed, resume might fail\n"); 510 return error; 511 } 512 513 taskqueue_cancel_timeout(dev_priv->wq, 514 &dev_priv->rps.delayed_resume_work, NULL); 515 516 intel_modeset_disable(dev); 517 518 drm_irq_uninstall(dev); 519 } 520 521 i915_save_state(dev); 522 523 intel_opregion_fini(dev); 524 525 /* Modeset on resume, not lid events */ 526 dev_priv->modeset_on_lid = 0; 527 528 console_lock(); 529 intel_fbdev_set_suspend(dev, 1); 530 console_unlock(); 531 532 return 0; 533} 534 535int i915_suspend(struct drm_device *dev, pm_message_t state) 536{ 537 int error; 538 539 if (!dev || !dev->dev_private) { 540 DRM_ERROR("dev: %p\n", dev); 541 DRM_ERROR("DRM not initialized, aborting suspend.\n"); 542 return -ENODEV; 543 } 544 545 if (state.event == PM_EVENT_PRETHAW) 546 return 0; 547 548 549 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 550 return 0; 551 552 error = i915_drm_freeze(dev); 553 if (error) 554 return error; 555 556 if (state.event == PM_EVENT_SUSPEND) { 557#ifdef __linux__ 558 /* Shut down the device */ 559 pci_disable_device(dev->pdev); 560 pci_set_power_state(dev->pdev, PCI_D3hot); 561#endif 562 } 563 564 return 0; 565} 566 567void intel_console_resume(void *arg, int pending) 568{ 569 struct drm_i915_private *dev_priv = 570 arg; 571 struct drm_device *dev = dev_priv->dev; 572 573 console_lock(); 574 intel_fbdev_set_suspend(dev, 0); 575 console_unlock(); 576} 577 578static int __i915_drm_thaw(struct drm_device *dev) 579{ 580 struct drm_i915_private *dev_priv = dev->dev_private; 581 int error = 0; 582 583 i915_restore_state(dev); 584 intel_opregion_setup(dev); 585 586 /* KMS EnterVT equivalent */ 587 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 588 intel_init_pch_refclk(dev); 589 590 DRM_LOCK(dev); 591 dev_priv->mm.suspended = 0; 592 593 error = i915_gem_init_hw(dev); 594 DRM_UNLOCK(dev); 595 596 intel_modeset_init_hw(dev); 597 intel_modeset_setup_hw_state(dev, false); 598 drm_irq_install(dev); 599 } 600 601 intel_opregion_init(dev); 602 603 dev_priv->modeset_on_lid = 0; 604 605 /* 606 * The console lock can be pretty contented on resume due 607 * to all the printk activity. Try to keep it out of the hot 608 * path of resume if possible. 609 */ 610 if (console_trylock()) { 611 intel_fbdev_set_suspend(dev, 0); 612 console_unlock(); 613 } else { 614 taskqueue_enqueue(dev_priv->wq, 615 &dev_priv->console_resume_work); 616 } 617 618 return error; 619} 620 621#ifdef __linux__ 622static int i915_drm_thaw(struct drm_device *dev) 623{ 624 int error = 0; 625 626 intel_gt_reset(dev); 627 628 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 629 DRM_LOCK(dev); 630 i915_gem_restore_gtt_mappings(dev); 631 DRM_UNLOCK(dev); 632 } 633 634 __i915_drm_thaw(dev); 635 636 return error; 637} 638#endif 639 640int i915_resume(struct drm_device *dev) 641{ 642 struct drm_i915_private *dev_priv = dev->dev_private; 643 int ret; 644 645 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 646 return 0; 647 648#ifdef __linux__ 649 if (pci_enable_device(dev->pdev)) 650 return -EIO; 651 652 pci_set_master(dev->pdev); 653#endif 654 655 intel_gt_reset(dev); 656 657 /* 658 * Platforms with opregion should have sane BIOS, older ones (gen3 and 659 * earlier) need this since the BIOS might clear all our scratch PTEs. 660 */ 661 if (drm_core_check_feature(dev, DRIVER_MODESET) && 662 !dev_priv->opregion.header) { 663 DRM_LOCK(dev); 664 i915_gem_restore_gtt_mappings(dev); 665 DRM_UNLOCK(dev); 666 } 667 668 ret = __i915_drm_thaw(dev); 669 if (ret) 670 return ret; 671 672 drm_kms_helper_poll_enable(dev); 673 return 0; 674} 675 676static int i8xx_do_reset(struct drm_device *dev) 677{ 678 struct drm_i915_private *dev_priv = dev->dev_private; 679 int onems; 680 681 if (IS_I85X(dev)) 682 return -ENODEV; 683 684 onems = hz / 1000; 685 if (onems == 0) 686 onems = 1; 687 688 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); 689 POSTING_READ(D_STATE); 690 691 if (IS_I830(dev) || IS_845G(dev)) { 692 I915_WRITE(DEBUG_RESET_I830, 693 DEBUG_RESET_DISPLAY | 694 DEBUG_RESET_RENDER | 695 DEBUG_RESET_FULL); 696 POSTING_READ(DEBUG_RESET_I830); 697 pause("i8xxrst1", onems); 698 699 I915_WRITE(DEBUG_RESET_I830, 0); 700 POSTING_READ(DEBUG_RESET_I830); 701 } 702 703 pause("i8xxrst2", onems); 704 705 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); 706 POSTING_READ(D_STATE); 707 708 return 0; 709} 710 711static int i965_reset_complete(struct drm_device *dev) 712{ 713 u8 gdrst; 714 pci_read_config_byte(dev->dev, I965_GDRST, &gdrst); 715 return (gdrst & GRDOM_RESET_ENABLE) == 0; 716} 717 718static int i965_do_reset(struct drm_device *dev) 719{ 720 int ret; 721 u8 gdrst; 722 723 /* 724 * Set the domains we want to reset (GRDOM/bits 2 and 3) as 725 * well as the reset bit (GR/bit 0). Setting the GR bit 726 * triggers the reset; when done, the hardware will clear it. 727 */ 728 pci_read_config_byte(dev->dev, I965_GDRST, &gdrst); 729 pci_write_config_byte(dev->dev, I965_GDRST, 730 gdrst | GRDOM_RENDER | 731 GRDOM_RESET_ENABLE); 732 ret = wait_for(i965_reset_complete(dev), 500); 733 if (ret) 734 return ret; 735 736 /* We can't reset render&media without also resetting display ... */ 737 pci_read_config_byte(dev->dev, I965_GDRST, &gdrst); 738 pci_write_config_byte(dev->dev, I965_GDRST, 739 gdrst | GRDOM_MEDIA | 740 GRDOM_RESET_ENABLE); 741 742 return wait_for(i965_reset_complete(dev), 500); 743} 744 745static int ironlake_do_reset(struct drm_device *dev) 746{ 747 struct drm_i915_private *dev_priv = dev->dev_private; 748 u32 gdrst; 749 int ret; 750 751 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); 752 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 753 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); 754 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); 755 if (ret) 756 return ret; 757 758 /* We can't reset render&media without also resetting display ... */ 759 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); 760 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 761 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); 762 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); 763} 764 765static int gen6_do_reset(struct drm_device *dev) 766{ 767 struct drm_i915_private *dev_priv = dev->dev_private; 768 int ret; 769 770 /* Hold gt_lock across reset to prevent any register access 771 * with forcewake not set correctly 772 */ 773 mtx_lock(&dev_priv->gt_lock); 774 775 /* Reset the chip */ 776 777 /* GEN6_GDRST is not in the gt power well, no need to check 778 * for fifo space for the write or forcewake the chip for 779 * the read 780 */ 781 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); 782 783 /* Spin waiting for the device to ack the reset request */ 784 /* 785 * NOTE Linux<->FreeBSD: We use _intel_wait_for() instead of 786 * wait_for(), because we want to set the 4th argument to 0. 787 * This allows us to use a struct mtx for dev_priv->gt_lock and 788 * avoid a LOR. 789 */ 790 ret = _intel_wait_for(dev, 791 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 792 500, 0, "915rst"); 793 794 /* If reset with a user forcewake, try to restore, otherwise turn it off */ 795 if (dev_priv->forcewake_count) 796 dev_priv->gt.force_wake_get(dev_priv); 797 else 798 dev_priv->gt.force_wake_put(dev_priv); 799 800 /* Restore fifo count */ 801 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 802 803 mtx_unlock(&dev_priv->gt_lock); 804 return ret; 805} 806 807int intel_gpu_reset(struct drm_device *dev) 808{ 809 struct drm_i915_private *dev_priv = dev->dev_private; 810 int ret = -ENODEV; 811 812 switch (INTEL_INFO(dev)->gen) { 813 case 7: 814 case 6: 815 ret = gen6_do_reset(dev); 816 break; 817 case 5: 818 ret = ironlake_do_reset(dev); 819 break; 820 case 4: 821 ret = i965_do_reset(dev); 822 break; 823 case 2: 824 ret = i8xx_do_reset(dev); 825 break; 826 } 827 828 /* Also reset the gpu hangman. */ 829 if (dev_priv->stop_rings) { 830 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); 831 dev_priv->stop_rings = 0; 832 if (ret == -ENODEV) { 833 DRM_ERROR("Reset not implemented, but ignoring " 834 "error for simulated gpu hangs\n"); 835 ret = 0; 836 } 837 } 838 839 return ret; 840} 841 842/** 843 * i915_reset - reset chip after a hang 844 * @dev: drm device to reset 845 * 846 * Reset the chip. Useful if a hang is detected. Returns zero on successful 847 * reset or otherwise an error code. 848 * 849 * Procedure is fairly simple: 850 * - reset the chip using the reset reg 851 * - re-init context state 852 * - re-init hardware status page 853 * - re-init ring buffer 854 * - re-init interrupt state 855 * - re-init display 856 */ 857int i915_reset(struct drm_device *dev) 858{ 859 drm_i915_private_t *dev_priv = dev->dev_private; 860 int ret; 861 862 if (!i915_try_reset) 863 return 0; 864 865 DRM_LOCK(dev); 866 867 i915_gem_reset(dev); 868 869 ret = -ENODEV; 870 if (get_seconds() - dev_priv->last_gpu_reset < 5) 871 DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); 872 else 873 ret = intel_gpu_reset(dev); 874 875 dev_priv->last_gpu_reset = get_seconds(); 876 if (ret) { 877 DRM_ERROR("Failed to reset chip.\n"); 878 DRM_UNLOCK(dev); 879 return ret; 880 } 881 882 /* Ok, now get things going again... */ 883 884 /* 885 * Everything depends on having the GTT running, so we need to start 886 * there. Fortunately we don't need to do this unless we reset the 887 * chip at a PCI level. 888 * 889 * Next we need to restore the context, but we don't use those 890 * yet either... 891 * 892 * Ring buffer needs to be re-initialized in the KMS case, or if X 893 * was running at the time of the reset (i.e. we weren't VT 894 * switched away). 895 */ 896 if (drm_core_check_feature(dev, DRIVER_MODESET) || 897 !dev_priv->mm.suspended) { 898 struct intel_ring_buffer *ring; 899 int i; 900 901 dev_priv->mm.suspended = 0; 902 903 i915_gem_init_swizzling(dev); 904 905 for_each_ring(ring, dev_priv, i) 906 ring->init(ring); 907 908 i915_gem_context_init(dev); 909 i915_gem_init_ppgtt(dev); 910 911 /* 912 * It would make sense to re-init all the other hw state, at 913 * least the rps/rc6/emon init done within modeset_init_hw. For 914 * some unknown reason, this blows up my ilk, so don't. 915 */ 916 917 DRM_UNLOCK(dev); 918 919 drm_irq_uninstall(dev); 920 drm_irq_install(dev); 921 } else { 922 DRM_UNLOCK(dev); 923 } 924 925 return 0; 926} 927 928const struct intel_device_info * 929i915_get_device_id(int device) 930{ 931 const struct intel_gfx_device_id *did; 932 933 for (did = &i915_infolist[0]; did->device != 0; did++) { 934 if (did->device != device) 935 continue; 936 return (did->info); 937 } 938 return (NULL); 939} 940 941static int i915_probe(device_t kdev) 942{ 943 const struct intel_device_info *intel_info = 944 i915_get_device_id(pci_get_device(kdev)); 945 946 if (intel_info == NULL) 947 return (ENXIO); 948 if (intel_info->is_valleyview) 949 if(!i915_preliminary_hw_support) { 950 DRM_ERROR("Preliminary hardware support disabled\n"); 951 return (ENXIO); 952 } 953 954 /* Only bind to function 0 of the device. Early generations 955 * used function 1 as a placeholder for multi-head. This causes 956 * us confusion instead, especially on the systems where both 957 * functions have the same PCI-ID! 958 */ 959 if (pci_get_function(kdev)) 960 return (ENXIO); 961 962 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC 963 * implementation for gen3 (and only gen3) that used legacy drm maps 964 * (gasp!) to share buffers between X and the client. Hence we need to 965 * keep around the fake agp stuff for gen3, even when kms is enabled. */ 966 if (intel_info->gen != 3) { 967 driver.driver_features &= 968 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); 969 } else if (!intel_agp_enabled) { 970 DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); 971 return (ENXIO); 972 } 973 974 return -drm_probe_helper(kdev, pciidlist); 975} 976 977#ifdef __linux__ 978static void 979i915_pci_remove(struct pci_dev *pdev) 980{ 981 struct drm_device *dev = pci_get_drvdata(pdev); 982 983 drm_put_dev(dev); 984} 985 986static int i915_pm_suspend(struct device *dev) 987{ 988 struct pci_dev *pdev = to_pci_dev(dev); 989 struct drm_device *drm_dev = pci_get_drvdata(pdev); 990 int error; 991 992 if (!drm_dev || !drm_dev->dev_private) { 993 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 994 return -ENODEV; 995 } 996 997 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 998 return 0; 999 1000 error = i915_drm_freeze(drm_dev); 1001 if (error) 1002 return error; 1003 1004 pci_disable_device(pdev); 1005 pci_set_power_state(pdev, PCI_D3hot); 1006 1007 return 0; 1008} 1009 1010static int i915_pm_resume(struct device *dev) 1011{ 1012 struct pci_dev *pdev = to_pci_dev(dev); 1013 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1014 1015 return i915_resume(drm_dev); 1016} 1017 1018static int i915_pm_freeze(struct device *dev) 1019{ 1020 struct pci_dev *pdev = to_pci_dev(dev); 1021 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1022 1023 if (!drm_dev || !drm_dev->dev_private) { 1024 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 1025 return -ENODEV; 1026 } 1027 1028 return i915_drm_freeze(drm_dev); 1029} 1030 1031static int i915_pm_thaw(struct device *dev) 1032{ 1033 struct pci_dev *pdev = to_pci_dev(dev); 1034 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1035 1036 return i915_drm_thaw(drm_dev); 1037} 1038 1039static int i915_pm_poweroff(struct device *dev) 1040{ 1041 struct pci_dev *pdev = to_pci_dev(dev); 1042 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1043 1044 return i915_drm_freeze(drm_dev); 1045} 1046 1047static const struct dev_pm_ops i915_pm_ops = { 1048 .suspend = i915_pm_suspend, 1049 .resume = i915_pm_resume, 1050 .freeze = i915_pm_freeze, 1051 .thaw = i915_pm_thaw, 1052 .poweroff = i915_pm_poweroff, 1053 .restore = i915_pm_resume, 1054}; 1055 1056static const struct vm_operations_struct i915_gem_vm_ops = { 1057 .fault = i915_gem_fault, 1058 .open = drm_gem_vm_open, 1059 .close = drm_gem_vm_close, 1060}; 1061 1062static const struct file_operations i915_driver_fops = { 1063 .owner = THIS_MODULE, 1064 .open = drm_open, 1065 .release = drm_release, 1066 .unlocked_ioctl = drm_ioctl, 1067 .mmap = drm_gem_mmap, 1068 .poll = drm_poll, 1069 .fasync = drm_fasync, 1070 .read = drm_read, 1071#ifdef CONFIG_COMPAT 1072 .compat_ioctl = i915_compat_ioctl, 1073#endif 1074 .llseek = noop_llseek, 1075}; 1076#endif /* __linux__ */ 1077 1078#ifdef COMPAT_FREEBSD32 1079extern struct drm_ioctl_desc i915_compat_ioctls[]; 1080extern int i915_compat_ioctls_nr; 1081#endif 1082 1083static struct drm_driver driver = { 1084 /* Don't use MTRRs here; the Xserver or userspace app should 1085 * deal with them for Intel hardware. 1086 */ 1087 .driver_features = 1088 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ 1089 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, 1090 .load = i915_driver_load, 1091 .unload = i915_driver_unload, 1092 .open = i915_driver_open, 1093 .lastclose = i915_driver_lastclose, 1094 .preclose = i915_driver_preclose, 1095 .postclose = i915_driver_postclose, 1096 1097 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ 1098 .suspend = i915_suspend, 1099 .resume = i915_resume, 1100 1101 .device_is_agp = i915_driver_device_is_agp, 1102 .master_create = i915_master_create, 1103 .master_destroy = i915_master_destroy, 1104#if defined(CONFIG_DEBUG_FS) 1105 .debugfs_init = i915_debugfs_init, 1106 .debugfs_cleanup = i915_debugfs_cleanup, 1107#endif 1108 .gem_init_object = i915_gem_init_object, 1109 .gem_free_object = i915_gem_free_object, 1110#if defined(__linux__) 1111 .gem_vm_ops = &i915_gem_vm_ops, 1112#elif defined(__FreeBSD__) 1113 .gem_pager_ops = &i915_gem_pager_ops, 1114#endif 1115 1116#ifdef FREEBSD_WIP 1117 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1118 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1119 .gem_prime_export = i915_gem_prime_export, 1120 .gem_prime_import = i915_gem_prime_import, 1121#endif /* FREEBSD_WIP */ 1122 1123 .dumb_create = i915_gem_dumb_create, 1124 .dumb_map_offset = i915_gem_mmap_gtt, 1125 .dumb_destroy = i915_gem_dumb_destroy, 1126 .ioctls = i915_ioctls, 1127#ifdef COMPAT_FREEBSD32 1128 .compat_ioctls = i915_compat_ioctls, 1129 .num_compat_ioctls = &i915_compat_ioctls_nr, 1130#endif 1131#ifdef __linux__ 1132 .fops = &i915_driver_fops, 1133#endif 1134#ifdef __FreeBSD__ 1135 .sysctl_init = i915_sysctl_init, 1136 .sysctl_cleanup = i915_sysctl_cleanup, 1137#endif 1138 .name = DRIVER_NAME, 1139 .desc = DRIVER_DESC, 1140 .date = DRIVER_DATE, 1141 .major = DRIVER_MAJOR, 1142 .minor = DRIVER_MINOR, 1143 .patchlevel = DRIVER_PATCHLEVEL, 1144}; 1145 1146#ifdef __linux__ 1147static struct pci_driver i915_pci_driver = { 1148 .name = DRIVER_NAME, 1149 .id_table = pciidlist, 1150 .probe = i915_pci_probe, 1151 .remove = i915_pci_remove, 1152 .driver.pm = &i915_pm_ops, 1153}; 1154#endif 1155 1156static int __init i915_attach(device_t kdev) 1157{ 1158 driver.num_ioctls = i915_max_ioctl; 1159 1160 /* 1161 * If CONFIG_DRM_I915_KMS is set, default to KMS unless 1162 * explicitly disabled with the module pararmeter. 1163 * 1164 * Otherwise, just follow the parameter (defaulting to off). 1165 * 1166 * Allow optional vga_text_mode_force boot option to override 1167 * the default behavior. 1168 */ 1169#if defined(CONFIG_DRM_I915_KMS) 1170 if (i915_modeset != 0) 1171 driver.driver_features |= DRIVER_MODESET; 1172#endif 1173 if (i915_modeset == 1) 1174 driver.driver_features |= DRIVER_MODESET; 1175 1176#ifdef CONFIG_VGA_CONSOLE 1177 if (vgacon_text_force() && i915_modeset == -1) 1178 driver.driver_features &= ~DRIVER_MODESET; 1179#endif 1180 1181 if (!(driver.driver_features & DRIVER_MODESET)) 1182 driver.get_vblank_timestamp = NULL; 1183 1184 return (-drm_attach_helper(kdev, pciidlist, &driver)); 1185} 1186 1187static struct fb_info * 1188i915_fb_helper_getinfo(device_t kdev) 1189{ 1190 struct intel_fbdev *ifbdev; 1191 drm_i915_private_t *dev_priv; 1192 struct drm_device *dev; 1193 struct fb_info *info; 1194 1195 dev = device_get_softc(kdev); 1196 dev_priv = dev->dev_private; 1197 ifbdev = dev_priv->fbdev; 1198 if (ifbdev == NULL) 1199 return (NULL); 1200 1201 info = ifbdev->helper.fbdev; 1202 1203 return (info); 1204} 1205 1206static device_method_t i915_methods[] = { 1207 /* Device interface */ 1208 DEVMETHOD(device_probe, i915_probe), 1209 DEVMETHOD(device_attach, i915_attach), 1210 DEVMETHOD(device_suspend, drm_generic_suspend), 1211 DEVMETHOD(device_resume, drm_generic_resume), 1212 DEVMETHOD(device_detach, drm_generic_detach), 1213 1214 /* Framebuffer service methods */ 1215 DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo), 1216 1217 DEVMETHOD_END 1218}; 1219 1220static driver_t i915_driver = { 1221 "drmn", 1222 i915_methods, 1223 sizeof(struct drm_device) 1224}; 1225 1226MODULE_AUTHOR(DRIVER_AUTHOR); 1227MODULE_DESCRIPTION(DRIVER_DESC); 1228MODULE_LICENSE("GPL and additional rights"); 1229 1230extern devclass_t drm_devclass; 1231DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0, 1232 SI_ORDER_ANY); 1233MODULE_DEPEND(i915kms, drmn, 1, 1, 1); 1234MODULE_DEPEND(i915kms, agp, 1, 1, 1); 1235MODULE_DEPEND(i915kms, iicbus, 1, 1, 1); 1236MODULE_DEPEND(i915kms, iic, 1, 1, 1); 1237MODULE_DEPEND(i915kms, iicbb, 1, 1, 1); 1238 1239/* We give fast paths for the really cool registers */ 1240#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1241 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ 1242 ((reg) < 0x40000) && \ 1243 ((reg) != FORCEWAKE)) 1244 1245static bool IS_DISPLAYREG(u32 reg) 1246{ 1247 /* 1248 * This should make it easier to transition modules over to the 1249 * new register block scheme, since we can do it incrementally. 1250 */ 1251 if (reg >= VLV_DISPLAY_BASE) 1252 return false; 1253 1254 if (reg >= RENDER_RING_BASE && 1255 reg < RENDER_RING_BASE + 0xff) 1256 return false; 1257 if (reg >= GEN6_BSD_RING_BASE && 1258 reg < GEN6_BSD_RING_BASE + 0xff) 1259 return false; 1260 if (reg >= BLT_RING_BASE && 1261 reg < BLT_RING_BASE + 0xff) 1262 return false; 1263 1264 if (reg == PGTBL_ER) 1265 return false; 1266 1267 if (reg >= IPEIR_I965 && 1268 reg < HWSTAM) 1269 return false; 1270 1271 if (reg == MI_MODE) 1272 return false; 1273 1274 if (reg == GFX_MODE_GEN7) 1275 return false; 1276 1277 if (reg == RENDER_HWS_PGA_GEN7 || 1278 reg == BSD_HWS_PGA_GEN7 || 1279 reg == BLT_HWS_PGA_GEN7) 1280 return false; 1281 1282 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || 1283 reg == GEN6_BSD_RNCID) 1284 return false; 1285 1286 if (reg == GEN6_BLITTER_ECOSKPD) 1287 return false; 1288 1289 if (reg >= 0x4000c && 1290 reg <= 0x4002c) 1291 return false; 1292 1293 if (reg >= 0x4f000 && 1294 reg <= 0x4f08f) 1295 return false; 1296 1297 if (reg >= 0x4f100 && 1298 reg <= 0x4f11f) 1299 return false; 1300 1301 if (reg >= VLV_MASTER_IER && 1302 reg <= GEN6_PMIER) 1303 return false; 1304 1305 if (reg >= FENCE_REG_SANDYBRIDGE_0 && 1306 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) 1307 return false; 1308 1309 if (reg >= VLV_IIR_RW && 1310 reg <= VLV_ISR) 1311 return false; 1312 1313 if (reg == FORCEWAKE_VLV || 1314 reg == FORCEWAKE_ACK_VLV) 1315 return false; 1316 1317 if (reg == GEN6_GDRST) 1318 return false; 1319 1320 switch (reg) { 1321 case _3D_CHICKEN3: 1322 case IVB_CHICKEN3: 1323 case GEN7_COMMON_SLICE_CHICKEN1: 1324 case GEN7_L3CNTLREG1: 1325 case GEN7_L3_CHICKEN_MODE_REGISTER: 1326 case GEN7_ROW_CHICKEN2: 1327 case GEN7_L3SQCREG4: 1328 case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: 1329 case GEN7_HALF_SLICE_CHICKEN1: 1330 case GEN6_MBCTL: 1331 case GEN6_UCGCTL2: 1332 return false; 1333 default: 1334 break; 1335 } 1336 1337 return true; 1338} 1339 1340static void 1341ilk_dummy_write(struct drm_i915_private *dev_priv) 1342{ 1343 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the 1344 * chip from rc6 before touching it for real. MI_MODE is masked, hence 1345 * harmless to write 0 into. */ 1346 I915_WRITE_NOTRACE(MI_MODE, 0); 1347} 1348 1349#define __i915_read(x, y) \ 1350u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1351 u##x val = 0; \ 1352 if (IS_GEN5(dev_priv->dev)) \ 1353 ilk_dummy_write(dev_priv); \ 1354 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 1355 mtx_lock(&dev_priv->gt_lock); \ 1356 if (dev_priv->forcewake_count == 0) \ 1357 dev_priv->gt.force_wake_get(dev_priv); \ 1358 val = DRM_READ##x(dev_priv->mmio_map, reg); \ 1359 if (dev_priv->forcewake_count == 0) \ 1360 dev_priv->gt.force_wake_put(dev_priv); \ 1361 mtx_unlock(&dev_priv->gt_lock); \ 1362 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ 1363 val = DRM_READ##x(dev_priv->mmio_map, reg + 0x180000); \ 1364 } else { \ 1365 val = DRM_READ##x(dev_priv->mmio_map, reg); \ 1366 } \ 1367 trace_i915_reg_rw(false, reg, val, sizeof(val)); \ 1368 return val; \ 1369} 1370 1371__i915_read(8, b) 1372__i915_read(16, w) 1373__i915_read(32, l) 1374__i915_read(64, q) 1375#undef __i915_read 1376 1377#define __i915_write(x, y) \ 1378void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 1379 u32 __fifo_ret = 0; \ 1380 trace_i915_reg_rw(true, reg, val, sizeof(val)); \ 1381 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 1382 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 1383 } \ 1384 if (IS_GEN5(dev_priv->dev)) \ 1385 ilk_dummy_write(dev_priv); \ 1386 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ 1387 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \ 1388 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ 1389 } \ 1390 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ 1391 DRM_WRITE##x(dev_priv->mmio_map, reg + 0x180000, val); \ 1392 } else { \ 1393 DRM_WRITE##x(dev_priv->mmio_map, reg, val); \ 1394 } \ 1395 if (unlikely(__fifo_ret)) { \ 1396 gen6_gt_check_fifodbg(dev_priv); \ 1397 } \ 1398 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ 1399 DRM_ERROR("Unclaimed write to %x\n", reg); \ 1400 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \ 1401 } \ 1402} 1403__i915_write(8, b) 1404__i915_write(16, w) 1405__i915_write(32, l) 1406__i915_write(64, q) 1407#undef __i915_write 1408 1409static const struct register_whitelist { 1410 uint64_t offset; 1411 uint32_t size; 1412 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ 1413} whitelist[] = { 1414 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, 1415}; 1416 1417int i915_reg_read_ioctl(struct drm_device *dev, 1418 void *data, struct drm_file *file) 1419{ 1420 struct drm_i915_private *dev_priv = dev->dev_private; 1421 struct drm_i915_reg_read *reg = data; 1422 struct register_whitelist const *entry = whitelist; 1423 int i; 1424 1425 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { 1426 if (entry->offset == reg->offset && 1427 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) 1428 break; 1429 } 1430 1431 if (i == ARRAY_SIZE(whitelist)) 1432 return -EINVAL; 1433 1434 switch (entry->size) { 1435 case 8: 1436 reg->val = I915_READ64(reg->offset); 1437 break; 1438 case 4: 1439 reg->val = I915_READ(reg->offset); 1440 break; 1441 case 2: 1442 reg->val = I915_READ16(reg->offset); 1443 break; 1444 case 1: 1445 reg->val = I915_READ8(reg->offset); 1446 break; 1447 default: 1448 WARN_ON(1); 1449 return -EINVAL; 1450 } 1451 1452 return 0; 1453} 1454