if_athioctl.h revision 250326
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athioctl.h 250326 2013-05-07 07:52:18Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHIOCTL_H 36116743Ssam#define _DEV_ATH_ATHIOCTL_H 37116743Ssam 38227327Sadrianstruct ath_tx_aggr_stats { 39227327Sadrian u_int32_t aggr_pkts[64]; 40227327Sadrian u_int32_t aggr_single_pkt; 41227327Sadrian u_int32_t aggr_nonbaw_pkt; 42227327Sadrian u_int32_t aggr_aggr_pkt; 43227327Sadrian u_int32_t aggr_baw_closed_single_pkt; 44227327Sadrian u_int32_t aggr_low_hwq_single_pkt; 45227327Sadrian u_int32_t aggr_sched_nopkt; 46233989Sadrian u_int32_t aggr_rts_aggr_limited; 47227327Sadrian}; 48227327Sadrian 49234090Sadrianstruct ath_intr_stats { 50234090Sadrian u_int32_t sync_intr[32]; 51234090Sadrian}; 52234090Sadrian 53116743Ssamstruct ath_stats { 54116743Ssam u_int32_t ast_watchdog; /* device reset by watchdog */ 55116743Ssam u_int32_t ast_hardware; /* fatal hardware error interrupts */ 56116743Ssam u_int32_t ast_bmiss; /* beacon miss interrupts */ 57155492Ssam u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 58138570Ssam u_int32_t ast_bstuck; /* beacon stuck interrupts */ 59116743Ssam u_int32_t ast_rxorn; /* rx overrun interrupts */ 60116743Ssam u_int32_t ast_rxeol; /* rx eol interrupts */ 61116743Ssam u_int32_t ast_txurn; /* tx underrun interrupts */ 62138570Ssam u_int32_t ast_mib; /* mib interrupts */ 63116743Ssam u_int32_t ast_intrcoal; /* interrupts coalesced */ 64138570Ssam u_int32_t ast_tx_packets; /* packet sent on the interface */ 65116743Ssam u_int32_t ast_tx_mgmt; /* management frames transmitted */ 66116743Ssam u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 67116743Ssam u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 68116743Ssam u_int32_t ast_tx_encap; /* tx encapsulation failed */ 69116743Ssam u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 70116743Ssam u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 71116743Ssam u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 72116743Ssam u_int32_t ast_tx_linear; /* tx linearized to cluster */ 73116743Ssam u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 74116743Ssam u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 75116743Ssam u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 76116743Ssam u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 77116743Ssam u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 78116743Ssam u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 79116743Ssam u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 80116743Ssam u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 81116743Ssam u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 82116743Ssam u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 83116743Ssam u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 84116743Ssam u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 85127779Ssam u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 86127779Ssam u_int32_t ast_tx_protect; /* tx frames with protection */ 87170530Ssam u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 88170530Ssam u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 89116743Ssam u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 90116743Ssam u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 91116743Ssam u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 92116743Ssam u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 93116743Ssam u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 94116743Ssam u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 95138570Ssam u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 96116743Ssam u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 97218689Sadrian u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */ 98119147Ssam u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 99127779Ssam u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 100138570Ssam u_int32_t ast_rx_packets; /* packet recv on the interface */ 101138570Ssam u_int32_t ast_rx_mgt; /* management frames received */ 102119147Ssam u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 103138570Ssam int8_t ast_tx_rssi; /* tx rssi of last ack */ 104138570Ssam int8_t ast_rx_rssi; /* rx rssi from histogram */ 105161187Ssam u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 106138570Ssam u_int32_t ast_be_xmit; /* beacons transmitted */ 107116743Ssam u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 108116743Ssam u_int32_t ast_per_cal; /* periodic calibration calls */ 109116743Ssam u_int32_t ast_per_calfail;/* periodic calibration failed */ 110116743Ssam u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 111116743Ssam u_int32_t ast_rate_calls; /* rate control checks */ 112116743Ssam u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 113116743Ssam u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 114138570Ssam u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 115138570Ssam u_int32_t ast_ant_txswitch;/* tx antenna switches */ 116138570Ssam u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 117138570Ssam u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 118159894Ssam u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 119159894Ssam u_int32_t ast_cabq_busy; /* cabq found busy */ 120160992Ssam u_int32_t ast_tx_raw; /* tx frames through raw api */ 121170530Ssam u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 122170530Ssam u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 123170530Ssam u_int32_t ast_ff_rx; /* fast frames rx'd */ 124170530Ssam u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 125170530Ssam u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 126170530Ssam int8_t ast_rx_noise; /* rx noise floor */ 127186904Ssam u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 128186904Ssam u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 129186904Ssam u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 130186904Ssam u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 131186904Ssam u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 132186904Ssam u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 133188195Ssam u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 134188195Ssam u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 135188555Ssam u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 136211299Sadrian u_int32_t ast_be_missed; /* missed beacons */ 137217684Sadrian u_int32_t ast_ani_cal; /* ANI calibrations performed */ 138218378Sadrian u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 139221965Sadrian u_int32_t ast_rx_halfgi; /* RX half-GI */ 140221965Sadrian u_int32_t ast_rx_2040; /* RX 40mhz frame */ 141221965Sadrian u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 142221965Sadrian u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 143221965Sadrian u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 144218689Sadrian u_int32_t ast_rx_hi_rx_chain; 145218924Sadrian u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 146221965Sadrian u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 147220772Sadrian u_int32_t ast_tx_timeout; /* Global TX timeout */ 148220782Sadrian u_int32_t ast_tx_cst; /* Carrier sense timeout */ 149221965Sadrian u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 150221965Sadrian u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 151221965Sadrian u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 152226798Sadrian u_int32_t ast_tx_swretries; /* software TX retries */ 153226798Sadrian u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 154226798Sadrian u_int32_t ast_tx_data_underrun; 155226798Sadrian u_int32_t ast_tx_delim_underrun; 156227868Sadrian u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 157226798Sadrian u_int32_t ast_tx_getnobuf; 158226798Sadrian u_int32_t ast_tx_getbusybuf; 159226798Sadrian u_int32_t ast_tx_intr; 160226798Sadrian u_int32_t ast_rx_intr; 161227868Sadrian u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 162227868Sadrian u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 163232764Sadrian u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 164238507Sadrian u_int32_t ast_rx_keymiss; 165240639Sadrian u_int32_t ast_tx_swfiltered; 166250326Sadrian u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */ 167238507Sadrian 168250326Sadrian u_int32_t ast_pad[14]; 169116743Ssam}; 170116743Ssam 171116743Ssam#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 172188557Ssam#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 173236833Sadrian#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 174116743Ssam 175123044Ssamstruct ath_diag { 176138570Ssam char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 177138570Ssam u_int16_t ad_id; 178138570Ssam#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 179138570Ssam#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 180138570Ssam#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 181138570Ssam#define ATH_DIAG_ID 0x0fff 182138570Ssam u_int16_t ad_in_size; /* pack to fit, yech */ 183138570Ssam caddr_t ad_in_data; 184138570Ssam caddr_t ad_out_data; 185138570Ssam u_int ad_out_size; 186123044Ssam 187123044Ssam}; 188123044Ssam#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 189224245Sadrian#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 190123044Ssam 191238632Sadrian 192119783Ssam/* 193238632Sadrian * The rate control ioctl has to support multiple potential rate 194238632Sadrian * control classes. For now, instead of trying to support an 195238632Sadrian * abstraction for this in the API, let's just use a TLV 196238632Sadrian * representation for the payload and let userspace sort it out. 197238632Sadrian */ 198238632Sadrianstruct ath_rateioctl_tlv { 199238632Sadrian uint16_t tlv_id; 200238632Sadrian uint16_t tlv_len; /* length excluding TLV header */ 201238632Sadrian}; 202238632Sadrian 203238632Sadrian/* 204238632Sadrian * This is purely the six byte MAC address. 205238632Sadrian */ 206238632Sadrian#define ATH_RATE_TLV_MACADDR 0xaab0 207238632Sadrian 208238632Sadrian/* 209238638Sadrian * The rate control modules may decide to push a mapping table 210238638Sadrian * of rix -> net80211 ratecode as part of the update. 211238638Sadrian */ 212238638Sadrian#define ATH_RATE_TLV_RATETABLE_NENTRIES 64 213238638Sadrianstruct ath_rateioctl_rt { 214238638Sadrian uint16_t nentries; 215238638Sadrian uint16_t pad[1]; 216238638Sadrian uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES]; 217238638Sadrian}; 218238638Sadrian#define ATH_RATE_TLV_RATETABLE 0xaab1 219238638Sadrian 220238638Sadrian/* 221238632Sadrian * This is the sample node statistics structure. 222238632Sadrian * More in ath_rate/sample/sample.h. 223238632Sadrian */ 224238632Sadrian#define ATH_RATE_TLV_SAMPLENODE 0xaab2 225238632Sadrian 226238632Sadrianstruct ath_rateioctl { 227238632Sadrian char if_name[IFNAMSIZ]; /* if name */ 228238632Sadrian union { 229238632Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 230238632Sadrian uint64_t pad; 231238632Sadrian } is_u; 232238632Sadrian uint32_t len; 233238632Sadrian caddr_t buf; 234238632Sadrian}; 235238632Sadrian#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl) 236238929Sadrian#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl) 237238632Sadrian 238238632Sadrian/* 239119783Ssam * Radio capture format. 240119783Ssam */ 241237522Sadrian#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 242154140Ssam (1 << IEEE80211_RADIOTAP_TSFT) | \ 243119783Ssam (1 << IEEE80211_RADIOTAP_FLAGS) | \ 244119783Ssam (1 << IEEE80211_RADIOTAP_RATE) | \ 245123928Ssam (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 246154140Ssam (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 247154140Ssam (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 248170530Ssam (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 249119783Ssam 0) 250119783Ssam 251237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 252237522Sadrian#define ATH_RX_RADIOTAP_PRESENT \ 253237522Sadrian (ATH_RX_RADIOTAP_PRESENT_BASE | \ 254237522Sadrian (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 255237522Sadrian (1 << IEEE80211_RADIOTAP_EXT) | \ 256237522Sadrian 0) 257237522Sadrian#else 258237522Sadrian#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 259237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 260237522Sadrian 261237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 262237522Sadrian/* 263237522Sadrian * This is higher than the vendor bitmap used inside 264237522Sadrian * the Atheros reference codebase. 265237522Sadrian */ 266237522Sadrian 267237522Sadrian/* Bit 8 */ 268237522Sadrian#define ATH_RADIOTAP_VENDOR_HEADER 8 269237522Sadrian 270237522Sadrian/* 271237522Sadrian * Using four chains makes all the fields in the 272237522Sadrian * per-chain info header be 4-byte aligned. 273237522Sadrian */ 274237522Sadrian#define ATH_RADIOTAP_MAX_CHAINS 4 275237522Sadrian 276237522Sadrian/* 277248143Sadrian * AR9380 and later chips are 3x3, which requires 278248143Sadrian * 5 EVM DWORDs in HT40 mode. 279248143Sadrian */ 280248143Sadrian#define ATH_RADIOTAP_MAX_EVM 5 281248143Sadrian 282248143Sadrian/* 283237522Sadrian * The vendor radiotap header data needs to be: 284237522Sadrian * 285237522Sadrian * + Aligned to a 4 byte address 286237522Sadrian * + .. so all internal fields are 4 bytes aligned; 287237522Sadrian * + .. and no 64 bit fields are allowed. 288237522Sadrian * 289237522Sadrian * So padding is required to ensure this is the case. 290237522Sadrian * 291237522Sadrian * Note that because of the lack of alignment with the 292237522Sadrian * vendor header (6 bytes), the first field must be 293237522Sadrian * two bytes so it can be accessed by alignment-strict 294237522Sadrian * platform (eg MIPS.) 295237522Sadrian */ 296237522Sadrianstruct ath_radiotap_vendor_hdr { /* 30 bytes */ 297237522Sadrian uint8_t vh_version; /* 1 */ 298237522Sadrian uint8_t vh_rx_chainmask; /* 1 */ 299237522Sadrian 300237522Sadrian /* At this point it should be 4 byte aligned */ 301248143Sadrian uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */ 302237522Sadrian 303237522Sadrian uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 304237522Sadrian uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 305237522Sadrian 306237522Sadrian uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 307237522Sadrian uint8_t vh_rs_status; /* RX status */ 308237522Sadrian uint8_t vh_rssi; /* Raw RSSI */ 309248146Sadrian uint8_t vh_flags; /* General flags */ 310248146Sadrian#define ATH_VENDOR_PKT_RX 0x01 311248146Sadrian#define ATH_VENDOR_PKT_TX 0x02 312248146Sadrian#define ATH_VENDOR_PKT_RXPHYERR 0x04 313248146Sadrian#define ATH_VENDOR_PKT_ISAGGR 0x08 314248146Sadrian#define ATH_VENDOR_PKT_MOREAGGR 0x10 315248146Sadrian 316248146Sadrian uint8_t vh_rx_hwrate; /* hardware RX ratecode */ 317248146Sadrian uint8_t vh_rs_flags; /* RX HAL flags */ 318248146Sadrian uint8_t vh_pad[2]; /* pad to DWORD boundary */ 319237522Sadrian} __packed; 320237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 321237522Sadrian 322119783Ssamstruct ath_rx_radiotap_header { 323119783Ssam struct ieee80211_radiotap_header wr_ihdr; 324237522Sadrian 325237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 326237522Sadrian /* Vendor extension header bitmap */ 327237522Sadrian uint32_t wr_ext_bitmap; /* 4 */ 328237522Sadrian 329237522Sadrian /* 330237522Sadrian * This padding is needed because: 331237522Sadrian * + the radiotap header is 8 bytes; 332237522Sadrian * + the extension bitmap is 4 bytes; 333237522Sadrian * + the tsf is 8 bytes, so it must start on an 8 byte 334237522Sadrian * boundary. 335237522Sadrian */ 336237522Sadrian uint32_t wr_pad1; 337237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 338237522Sadrian 339237522Sadrian /* Normal radiotap fields */ 340154140Ssam u_int64_t wr_tsf; 341154140Ssam u_int8_t wr_flags; 342119783Ssam u_int8_t wr_rate; 343170530Ssam int8_t wr_antsignal; 344170530Ssam int8_t wr_antnoise; 345170530Ssam u_int8_t wr_antenna; 346170530Ssam u_int8_t wr_pad[3]; 347170530Ssam u_int32_t wr_chan_flags; 348119783Ssam u_int16_t wr_chan_freq; 349170530Ssam u_int8_t wr_chan_ieee; 350170530Ssam int8_t wr_chan_maxpow; 351237522Sadrian 352237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 353237522Sadrian /* 354237522Sadrian * Vendor header section, as required by the 355237522Sadrian * presence of the vendor extension bit and bitmap 356237522Sadrian * entry. 357237522Sadrian * 358237522Sadrian * XXX This must be aligned to a 4 byte address? 359237522Sadrian * XXX or 8 byte address? 360237522Sadrian */ 361237522Sadrian struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 362237522Sadrian 363237522Sadrian /* 364237522Sadrian * Because of the lack of alignment enforced by the above 365237522Sadrian * header, this vendor section won't be aligned in any 366237522Sadrian * useful way. So, this will include a two-byte version 367237522Sadrian * value which will force the structure to be 4-byte aligned. 368237522Sadrian */ 369237522Sadrian struct ath_radiotap_vendor_hdr wr_v; 370237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 371170530Ssam} __packed; 372119783Ssam 373119783Ssam#define ATH_TX_RADIOTAP_PRESENT ( \ 374154140Ssam (1 << IEEE80211_RADIOTAP_TSFT) | \ 375119783Ssam (1 << IEEE80211_RADIOTAP_FLAGS) | \ 376119783Ssam (1 << IEEE80211_RADIOTAP_RATE) | \ 377123928Ssam (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 378123928Ssam (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 379170530Ssam (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 380119783Ssam 0) 381119783Ssam 382119783Ssamstruct ath_tx_radiotap_header { 383119783Ssam struct ieee80211_radiotap_header wt_ihdr; 384154140Ssam u_int64_t wt_tsf; 385154140Ssam u_int8_t wt_flags; 386119783Ssam u_int8_t wt_rate; 387123928Ssam u_int8_t wt_txpower; 388123928Ssam u_int8_t wt_antenna; 389170530Ssam u_int32_t wt_chan_flags; 390170530Ssam u_int16_t wt_chan_freq; 391170530Ssam u_int8_t wt_chan_ieee; 392170530Ssam int8_t wt_chan_maxpow; 393170530Ssam} __packed; 394119783Ssam 395224245Sadrian/* 396224245Sadrian * DFS ioctl commands 397224245Sadrian */ 398224245Sadrian 399224245Sadrian#define DFS_SET_THRESH 2 400224245Sadrian#define DFS_GET_THRESH 3 401224245Sadrian#define DFS_RADARDETECTS 6 402224245Sadrian 403224245Sadrian/* 404224245Sadrian * DFS ioctl parameter types 405224245Sadrian */ 406224245Sadrian#define DFS_PARAM_FIRPWR 1 407224245Sadrian#define DFS_PARAM_RRSSI 2 408224245Sadrian#define DFS_PARAM_HEIGHT 3 409224245Sadrian#define DFS_PARAM_PRSSI 4 410224245Sadrian#define DFS_PARAM_INBAND 5 411224245Sadrian#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 412224245Sadrian#define DFS_PARAM_RELSTEP_EN 7 413224245Sadrian#define DFS_PARAM_RELSTEP 8 414224245Sadrian#define DFS_PARAM_RELPWR_EN 9 415224245Sadrian#define DFS_PARAM_RELPWR 10 416224245Sadrian#define DFS_PARAM_MAXLEN 11 417224245Sadrian#define DFS_PARAM_USEFIR128 12 418224245Sadrian#define DFS_PARAM_BLOCKRADAR 13 419224245Sadrian#define DFS_PARAM_MAXRSSI_EN 14 420224245Sadrian 421224245Sadrian/* FreeBSD-specific start at 32 */ 422224245Sadrian#define DFS_PARAM_ENABLE 32 423224245Sadrian#define DFS_PARAM_EN_EXTCH 33 424224245Sadrian 425244951Sadrian/* 426244951Sadrian * Spectral ioctl parameter types 427244951Sadrian */ 428244951Sadrian#define SPECTRAL_PARAM_FFT_PERIOD 1 429244951Sadrian#define SPECTRAL_PARAM_SS_PERIOD 2 430244951Sadrian#define SPECTRAL_PARAM_SS_COUNT 3 431244951Sadrian#define SPECTRAL_PARAM_SS_SHORT_RPT 4 432244951Sadrian#define SPECTRAL_PARAM_ENABLED 5 433244951Sadrian#define SPECTRAL_PARAM_ACTIVE 6 434244951Sadrian 435244951Sadrian/* 436244951Sadrian * Spectral control parameters 437244951Sadrian */ 438244951Sadrian#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag) 439244951Sadrian 440244951Sadrian#define SPECTRAL_CONTROL_ENABLE 2 441244951Sadrian#define SPECTRAL_CONTROL_DISABLE 3 442244951Sadrian#define SPECTRAL_CONTROL_START 4 443244951Sadrian#define SPECTRAL_CONTROL_STOP 5 444244951Sadrian#define SPECTRAL_CONTROL_GET_PARAMS 6 445244951Sadrian#define SPECTRAL_CONTROL_SET_PARAMS 7 446245185Sadrian#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8 447245185Sadrian#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9 448244951Sadrian 449116743Ssam#endif /* _DEV_ATH_ATHIOCTL_H */ 450