if_athioctl.h revision 250326
1271493Sdelphij/*- 2271493Sdelphij * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3271493Sdelphij * All rights reserved. 4271493Sdelphij * 5271493Sdelphij * Redistribution and use in source and binary forms, with or without 6271493Sdelphij * modification, are permitted provided that the following conditions 7271493Sdelphij * are met: 8271493Sdelphij * 1. Redistributions of source code must retain the above copyright 9271493Sdelphij * notice, this list of conditions and the following disclaimer, 10271493Sdelphij * without modification. 11271493Sdelphij * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12271493Sdelphij * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13271493Sdelphij * redistribution must be conditioned upon including a substantially 14271493Sdelphij * similar Disclaimer requirement for further binary redistribution. 15271493Sdelphij * 16271493Sdelphij * NO WARRANTY 17271493Sdelphij * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18271493Sdelphij * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19271493Sdelphij * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20271493Sdelphij * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21271493Sdelphij * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22271493Sdelphij * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23271493Sdelphij * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24271493Sdelphij * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25271493Sdelphij * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26271493Sdelphij * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27271493Sdelphij * THE POSSIBILITY OF SUCH DAMAGES. 28271493Sdelphij * 29271493Sdelphij * $FreeBSD: head/sys/dev/ath/if_athioctl.h 250326 2013-05-07 07:52:18Z adrian $ 30271493Sdelphij */ 31271493Sdelphij 32271493Sdelphij/* 33271493Sdelphij * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 34271493Sdelphij */ 35271493Sdelphij#ifndef _DEV_ATH_ATHIOCTL_H 36271493Sdelphij#define _DEV_ATH_ATHIOCTL_H 37271493Sdelphij 38271493Sdelphijstruct ath_tx_aggr_stats { 39271493Sdelphij u_int32_t aggr_pkts[64]; 40271493Sdelphij u_int32_t aggr_single_pkt; 41271493Sdelphij u_int32_t aggr_nonbaw_pkt; 42271493Sdelphij u_int32_t aggr_aggr_pkt; 43271493Sdelphij u_int32_t aggr_baw_closed_single_pkt; 44271493Sdelphij u_int32_t aggr_low_hwq_single_pkt; 45271493Sdelphij u_int32_t aggr_sched_nopkt; 46271493Sdelphij u_int32_t aggr_rts_aggr_limited; 47271493Sdelphij}; 48271493Sdelphij 49271493Sdelphijstruct ath_intr_stats { 50271493Sdelphij u_int32_t sync_intr[32]; 51271493Sdelphij}; 52271493Sdelphij 53271493Sdelphijstruct ath_stats { 54271493Sdelphij u_int32_t ast_watchdog; /* device reset by watchdog */ 55271493Sdelphij u_int32_t ast_hardware; /* fatal hardware error interrupts */ 56271493Sdelphij u_int32_t ast_bmiss; /* beacon miss interrupts */ 57271493Sdelphij u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 58271493Sdelphij u_int32_t ast_bstuck; /* beacon stuck interrupts */ 59271493Sdelphij u_int32_t ast_rxorn; /* rx overrun interrupts */ 60271493Sdelphij u_int32_t ast_rxeol; /* rx eol interrupts */ 61271493Sdelphij u_int32_t ast_txurn; /* tx underrun interrupts */ 62271493Sdelphij u_int32_t ast_mib; /* mib interrupts */ 63271493Sdelphij u_int32_t ast_intrcoal; /* interrupts coalesced */ 64271493Sdelphij u_int32_t ast_tx_packets; /* packet sent on the interface */ 65271493Sdelphij u_int32_t ast_tx_mgmt; /* management frames transmitted */ 66271493Sdelphij u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 67271493Sdelphij u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 68271493Sdelphij u_int32_t ast_tx_encap; /* tx encapsulation failed */ 69271493Sdelphij u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 70271493Sdelphij u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 71271493Sdelphij u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 72271493Sdelphij u_int32_t ast_tx_linear; /* tx linearized to cluster */ 73271493Sdelphij u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 74271493Sdelphij u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 75271493Sdelphij u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 76271493Sdelphij u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 77271493Sdelphij u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 78271493Sdelphij u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 79271493Sdelphij u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 80271493Sdelphij u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 81271493Sdelphij u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 82271493Sdelphij u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 83271493Sdelphij u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 84271493Sdelphij u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 85271493Sdelphij u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 86271493Sdelphij u_int32_t ast_tx_protect; /* tx frames with protection */ 87271493Sdelphij u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 88271493Sdelphij u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 89271493Sdelphij u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 90271493Sdelphij u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 91271493Sdelphij u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 92271493Sdelphij u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 93271493Sdelphij u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 94271493Sdelphij u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 95271493Sdelphij u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 96271493Sdelphij u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 97271493Sdelphij u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */ 98271493Sdelphij u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 99271493Sdelphij u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 100271493Sdelphij u_int32_t ast_rx_packets; /* packet recv on the interface */ 101271493Sdelphij u_int32_t ast_rx_mgt; /* management frames received */ 102271493Sdelphij u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 103271493Sdelphij int8_t ast_tx_rssi; /* tx rssi of last ack */ 104271493Sdelphij int8_t ast_rx_rssi; /* rx rssi from histogram */ 105271493Sdelphij u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 106271493Sdelphij u_int32_t ast_be_xmit; /* beacons transmitted */ 107271493Sdelphij u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 108271493Sdelphij u_int32_t ast_per_cal; /* periodic calibration calls */ 109271493Sdelphij u_int32_t ast_per_calfail;/* periodic calibration failed */ 110271493Sdelphij u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 111271493Sdelphij u_int32_t ast_rate_calls; /* rate control checks */ 112271493Sdelphij u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 113271493Sdelphij u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 114271493Sdelphij u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 115271493Sdelphij u_int32_t ast_ant_txswitch;/* tx antenna switches */ 116271493Sdelphij u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 117271493Sdelphij u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 118271493Sdelphij u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 119271493Sdelphij u_int32_t ast_cabq_busy; /* cabq found busy */ 120271493Sdelphij u_int32_t ast_tx_raw; /* tx frames through raw api */ 121271493Sdelphij u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 122271493Sdelphij u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 123271493Sdelphij u_int32_t ast_ff_rx; /* fast frames rx'd */ 124271493Sdelphij u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 125271493Sdelphij u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 126271493Sdelphij int8_t ast_rx_noise; /* rx noise floor */ 127271493Sdelphij u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 128271493Sdelphij u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 129271493Sdelphij u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 130271493Sdelphij u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 131271493Sdelphij u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 132271493Sdelphij u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 133271493Sdelphij u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 134271493Sdelphij u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 135271493Sdelphij u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 136271493Sdelphij u_int32_t ast_be_missed; /* missed beacons */ 137271493Sdelphij u_int32_t ast_ani_cal; /* ANI calibrations performed */ 138271493Sdelphij u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 139271493Sdelphij u_int32_t ast_rx_halfgi; /* RX half-GI */ 140271493Sdelphij u_int32_t ast_rx_2040; /* RX 40mhz frame */ 141271493Sdelphij u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 142271493Sdelphij u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 143271493Sdelphij u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 144271493Sdelphij u_int32_t ast_rx_hi_rx_chain; 145271493Sdelphij u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 146271493Sdelphij u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 147271493Sdelphij u_int32_t ast_tx_timeout; /* Global TX timeout */ 148271493Sdelphij u_int32_t ast_tx_cst; /* Carrier sense timeout */ 149271493Sdelphij u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 150271493Sdelphij u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 151271493Sdelphij u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 152271493Sdelphij u_int32_t ast_tx_swretries; /* software TX retries */ 153271493Sdelphij u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 154271493Sdelphij u_int32_t ast_tx_data_underrun; 155271493Sdelphij u_int32_t ast_tx_delim_underrun; 156271493Sdelphij u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 157271493Sdelphij u_int32_t ast_tx_getnobuf; 158271493Sdelphij u_int32_t ast_tx_getbusybuf; 159271493Sdelphij u_int32_t ast_tx_intr; 160271493Sdelphij u_int32_t ast_rx_intr; 161271493Sdelphij u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 162271493Sdelphij u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 163271493Sdelphij u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 164271493Sdelphij u_int32_t ast_rx_keymiss; 165271493Sdelphij u_int32_t ast_tx_swfiltered; 166271493Sdelphij u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */ 167271493Sdelphij 168271493Sdelphij u_int32_t ast_pad[14]; 169271493Sdelphij}; 170271493Sdelphij 171271493Sdelphij#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 172271493Sdelphij#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 173271493Sdelphij#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 174271493Sdelphij 175271493Sdelphijstruct ath_diag { 176271493Sdelphij char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 177271493Sdelphij u_int16_t ad_id; 178271493Sdelphij#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 179271493Sdelphij#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 180271493Sdelphij#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 181271493Sdelphij#define ATH_DIAG_ID 0x0fff 182271493Sdelphij u_int16_t ad_in_size; /* pack to fit, yech */ 183271493Sdelphij caddr_t ad_in_data; 184271493Sdelphij caddr_t ad_out_data; 185271493Sdelphij u_int ad_out_size; 186271493Sdelphij 187271493Sdelphij}; 188271493Sdelphij#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 189271493Sdelphij#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 190271493Sdelphij 191271493Sdelphij 192271493Sdelphij/* 193271493Sdelphij * The rate control ioctl has to support multiple potential rate 194271493Sdelphij * control classes. For now, instead of trying to support an 195271493Sdelphij * abstraction for this in the API, let's just use a TLV 196271493Sdelphij * representation for the payload and let userspace sort it out. 197271493Sdelphij */ 198271493Sdelphijstruct ath_rateioctl_tlv { 199271493Sdelphij uint16_t tlv_id; 200271493Sdelphij uint16_t tlv_len; /* length excluding TLV header */ 201271493Sdelphij}; 202271493Sdelphij 203271493Sdelphij/* 204271493Sdelphij * This is purely the six byte MAC address. 205271493Sdelphij */ 206271493Sdelphij#define ATH_RATE_TLV_MACADDR 0xaab0 207271493Sdelphij 208271493Sdelphij/* 209271493Sdelphij * The rate control modules may decide to push a mapping table 210271493Sdelphij * of rix -> net80211 ratecode as part of the update. 211271493Sdelphij */ 212271493Sdelphij#define ATH_RATE_TLV_RATETABLE_NENTRIES 64 213271493Sdelphijstruct ath_rateioctl_rt { 214271493Sdelphij uint16_t nentries; 215271493Sdelphij uint16_t pad[1]; 216271493Sdelphij uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES]; 217271493Sdelphij}; 218271493Sdelphij#define ATH_RATE_TLV_RATETABLE 0xaab1 219271493Sdelphij 220271493Sdelphij/* 221271493Sdelphij * This is the sample node statistics structure. 222271493Sdelphij * More in ath_rate/sample/sample.h. 223271493Sdelphij */ 224271493Sdelphij#define ATH_RATE_TLV_SAMPLENODE 0xaab2 225271493Sdelphij 226271493Sdelphijstruct ath_rateioctl { 227271493Sdelphij char if_name[IFNAMSIZ]; /* if name */ 228271493Sdelphij union { 229271493Sdelphij uint8_t macaddr[IEEE80211_ADDR_LEN]; 230271493Sdelphij uint64_t pad; 231271493Sdelphij } is_u; 232271493Sdelphij uint32_t len; 233271493Sdelphij caddr_t buf; 234271493Sdelphij}; 235271493Sdelphij#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl) 236271493Sdelphij#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl) 237271493Sdelphij 238271493Sdelphij/* 239271493Sdelphij * Radio capture format. 240271493Sdelphij */ 241271493Sdelphij#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 242271493Sdelphij (1 << IEEE80211_RADIOTAP_TSFT) | \ 243271493Sdelphij (1 << IEEE80211_RADIOTAP_FLAGS) | \ 244271493Sdelphij (1 << IEEE80211_RADIOTAP_RATE) | \ 245271493Sdelphij (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 246271493Sdelphij (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 247271493Sdelphij (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 248271493Sdelphij (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 249271493Sdelphij 0) 250271493Sdelphij 251271493Sdelphij#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 252271493Sdelphij#define ATH_RX_RADIOTAP_PRESENT \ 253271493Sdelphij (ATH_RX_RADIOTAP_PRESENT_BASE | \ 254271493Sdelphij (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 255271493Sdelphij (1 << IEEE80211_RADIOTAP_EXT) | \ 256271493Sdelphij 0) 257271493Sdelphij#else 258271493Sdelphij#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 259271493Sdelphij#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 260271493Sdelphij 261271493Sdelphij#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 262271493Sdelphij/* 263271493Sdelphij * This is higher than the vendor bitmap used inside 264271493Sdelphij * the Atheros reference codebase. 265271493Sdelphij */ 266271493Sdelphij 267271493Sdelphij/* Bit 8 */ 268271493Sdelphij#define ATH_RADIOTAP_VENDOR_HEADER 8 269271493Sdelphij 270271493Sdelphij/* 271271493Sdelphij * Using four chains makes all the fields in the 272271493Sdelphij * per-chain info header be 4-byte aligned. 273271493Sdelphij */ 274271493Sdelphij#define ATH_RADIOTAP_MAX_CHAINS 4 275271493Sdelphij 276271493Sdelphij/* 277271493Sdelphij * AR9380 and later chips are 3x3, which requires 278271493Sdelphij * 5 EVM DWORDs in HT40 mode. 279271493Sdelphij */ 280271493Sdelphij#define ATH_RADIOTAP_MAX_EVM 5 281271493Sdelphij 282271493Sdelphij/* 283271493Sdelphij * The vendor radiotap header data needs to be: 284271493Sdelphij * 285271493Sdelphij * + Aligned to a 4 byte address 286271493Sdelphij * + .. so all internal fields are 4 bytes aligned; 287271493Sdelphij * + .. and no 64 bit fields are allowed. 288271493Sdelphij * 289271493Sdelphij * So padding is required to ensure this is the case. 290271493Sdelphij * 291271493Sdelphij * Note that because of the lack of alignment with the 292271493Sdelphij * vendor header (6 bytes), the first field must be 293271493Sdelphij * two bytes so it can be accessed by alignment-strict 294271493Sdelphij * platform (eg MIPS.) 295271493Sdelphij */ 296271493Sdelphijstruct ath_radiotap_vendor_hdr { /* 30 bytes */ 297271493Sdelphij uint8_t vh_version; /* 1 */ 298271493Sdelphij uint8_t vh_rx_chainmask; /* 1 */ 299271493Sdelphij 300271493Sdelphij /* At this point it should be 4 byte aligned */ 301271493Sdelphij uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */ 302271493Sdelphij 303271493Sdelphij uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 304271493Sdelphij uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 305271493Sdelphij 306271493Sdelphij uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 307271493Sdelphij uint8_t vh_rs_status; /* RX status */ 308271493Sdelphij uint8_t vh_rssi; /* Raw RSSI */ 309271493Sdelphij uint8_t vh_flags; /* General flags */ 310271493Sdelphij#define ATH_VENDOR_PKT_RX 0x01 311271493Sdelphij#define ATH_VENDOR_PKT_TX 0x02 312271493Sdelphij#define ATH_VENDOR_PKT_RXPHYERR 0x04 313271493Sdelphij#define ATH_VENDOR_PKT_ISAGGR 0x08 314271493Sdelphij#define ATH_VENDOR_PKT_MOREAGGR 0x10 315271493Sdelphij 316271493Sdelphij uint8_t vh_rx_hwrate; /* hardware RX ratecode */ 317271493Sdelphij uint8_t vh_rs_flags; /* RX HAL flags */ 318271493Sdelphij uint8_t vh_pad[2]; /* pad to DWORD boundary */ 319271493Sdelphij} __packed; 320271493Sdelphij#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 321271493Sdelphij 322271493Sdelphijstruct ath_rx_radiotap_header { 323271493Sdelphij struct ieee80211_radiotap_header wr_ihdr; 324271493Sdelphij 325271493Sdelphij#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 326271493Sdelphij /* Vendor extension header bitmap */ 327271493Sdelphij uint32_t wr_ext_bitmap; /* 4 */ 328271493Sdelphij 329271493Sdelphij /* 330271493Sdelphij * This padding is needed because: 331271493Sdelphij * + the radiotap header is 8 bytes; 332271493Sdelphij * + the extension bitmap is 4 bytes; 333271493Sdelphij * + the tsf is 8 bytes, so it must start on an 8 byte 334271493Sdelphij * boundary. 335271493Sdelphij */ 336271493Sdelphij uint32_t wr_pad1; 337271493Sdelphij#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 338271493Sdelphij 339271493Sdelphij /* Normal radiotap fields */ 340271493Sdelphij u_int64_t wr_tsf; 341271493Sdelphij u_int8_t wr_flags; 342271493Sdelphij u_int8_t wr_rate; 343271493Sdelphij int8_t wr_antsignal; 344271493Sdelphij int8_t wr_antnoise; 345271493Sdelphij u_int8_t wr_antenna; 346271493Sdelphij u_int8_t wr_pad[3]; 347271493Sdelphij u_int32_t wr_chan_flags; 348271493Sdelphij u_int16_t wr_chan_freq; 349271493Sdelphij u_int8_t wr_chan_ieee; 350271493Sdelphij int8_t wr_chan_maxpow; 351271493Sdelphij 352271493Sdelphij#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 353271493Sdelphij /* 354271493Sdelphij * Vendor header section, as required by the 355271493Sdelphij * presence of the vendor extension bit and bitmap 356271493Sdelphij * entry. 357271493Sdelphij * 358271493Sdelphij * XXX This must be aligned to a 4 byte address? 359271493Sdelphij * XXX or 8 byte address? 360271493Sdelphij */ 361271493Sdelphij struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 362271493Sdelphij 363271493Sdelphij /* 364271493Sdelphij * Because of the lack of alignment enforced by the above 365271493Sdelphij * header, this vendor section won't be aligned in any 366271493Sdelphij * useful way. So, this will include a two-byte version 367271493Sdelphij * value which will force the structure to be 4-byte aligned. 368271493Sdelphij */ 369271493Sdelphij struct ath_radiotap_vendor_hdr wr_v; 370271493Sdelphij#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 371271493Sdelphij} __packed; 372271493Sdelphij 373271493Sdelphij#define ATH_TX_RADIOTAP_PRESENT ( \ 374271493Sdelphij (1 << IEEE80211_RADIOTAP_TSFT) | \ 375271493Sdelphij (1 << IEEE80211_RADIOTAP_FLAGS) | \ 376271493Sdelphij (1 << IEEE80211_RADIOTAP_RATE) | \ 377271493Sdelphij (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 378271493Sdelphij (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 379271493Sdelphij (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 380271493Sdelphij 0) 381271493Sdelphij 382271493Sdelphijstruct ath_tx_radiotap_header { 383271493Sdelphij struct ieee80211_radiotap_header wt_ihdr; 384271493Sdelphij u_int64_t wt_tsf; 385271493Sdelphij u_int8_t wt_flags; 386271493Sdelphij u_int8_t wt_rate; 387271493Sdelphij u_int8_t wt_txpower; 388271493Sdelphij u_int8_t wt_antenna; 389271493Sdelphij u_int32_t wt_chan_flags; 390271493Sdelphij u_int16_t wt_chan_freq; 391271493Sdelphij u_int8_t wt_chan_ieee; 392271493Sdelphij int8_t wt_chan_maxpow; 393271493Sdelphij} __packed; 394271493Sdelphij 395271493Sdelphij/* 396271493Sdelphij * DFS ioctl commands 397271493Sdelphij */ 398271493Sdelphij 399271493Sdelphij#define DFS_SET_THRESH 2 400271493Sdelphij#define DFS_GET_THRESH 3 401271493Sdelphij#define DFS_RADARDETECTS 6 402271493Sdelphij 403271493Sdelphij/* 404271493Sdelphij * DFS ioctl parameter types 405271493Sdelphij */ 406271493Sdelphij#define DFS_PARAM_FIRPWR 1 407271493Sdelphij#define DFS_PARAM_RRSSI 2 408271493Sdelphij#define DFS_PARAM_HEIGHT 3 409271493Sdelphij#define DFS_PARAM_PRSSI 4 410271493Sdelphij#define DFS_PARAM_INBAND 5 411271493Sdelphij#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 412271493Sdelphij#define DFS_PARAM_RELSTEP_EN 7 413271493Sdelphij#define DFS_PARAM_RELSTEP 8 414271493Sdelphij#define DFS_PARAM_RELPWR_EN 9 415271493Sdelphij#define DFS_PARAM_RELPWR 10 416271493Sdelphij#define DFS_PARAM_MAXLEN 11 417271493Sdelphij#define DFS_PARAM_USEFIR128 12 418271493Sdelphij#define DFS_PARAM_BLOCKRADAR 13 419271493Sdelphij#define DFS_PARAM_MAXRSSI_EN 14 420271493Sdelphij 421271493Sdelphij/* FreeBSD-specific start at 32 */ 422271493Sdelphij#define DFS_PARAM_ENABLE 32 423271493Sdelphij#define DFS_PARAM_EN_EXTCH 33 424271493Sdelphij 425271493Sdelphij/* 426271493Sdelphij * Spectral ioctl parameter types 427271493Sdelphij */ 428271493Sdelphij#define SPECTRAL_PARAM_FFT_PERIOD 1 429271493Sdelphij#define SPECTRAL_PARAM_SS_PERIOD 2 430271493Sdelphij#define SPECTRAL_PARAM_SS_COUNT 3 431271493Sdelphij#define SPECTRAL_PARAM_SS_SHORT_RPT 4 432271493Sdelphij#define SPECTRAL_PARAM_ENABLED 5 433271493Sdelphij#define SPECTRAL_PARAM_ACTIVE 6 434271493Sdelphij 435271493Sdelphij/* 436271493Sdelphij * Spectral control parameters 437271493Sdelphij */ 438271493Sdelphij#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag) 439271493Sdelphij 440271493Sdelphij#define SPECTRAL_CONTROL_ENABLE 2 441271493Sdelphij#define SPECTRAL_CONTROL_DISABLE 3 442271493Sdelphij#define SPECTRAL_CONTROL_START 4 443271493Sdelphij#define SPECTRAL_CONTROL_STOP 5 444271493Sdelphij#define SPECTRAL_CONTROL_GET_PARAMS 6 445271493Sdelphij#define SPECTRAL_CONTROL_SET_PARAMS 7 446271493Sdelphij#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8 447271493Sdelphij#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9 448271493Sdelphij 449271493Sdelphij#endif /* _DEV_ATH_ATHIOCTL_H */ 450271493Sdelphij