1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * General Purpose IO interface. 50 * 51 * <hr>$Revision: 70030 $<hr> 52 */ 53 54#ifndef __CVMX_GPIO_H__ 55#define __CVMX_GPIO_H__ 56 57#ifdef __cplusplus 58extern "C" { 59#endif 60 61/* CSR typedefs have been moved to cvmx-gpio-defs.h */ 62 63/** 64 * Clear the interrupt rising edge detector for the supplied 65 * pins in the mask. Chips which have more than 16 GPIO pins 66 * can't use them for interrupts. 67 e 68 * @param clear_mask Mask of pins to clear 69 */ 70static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask) 71{ 72 if (OCTEON_IS_MODEL(OCTEON_CN61XX)) 73 { 74 cvmx_gpio_multi_cast_t multi_cast; 75 cvmx_gpio_bit_cfgx_t gpio_bit; 76 int core = cvmx_get_core_num(); 77 78 multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST); 79 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core)); 80 81 /* If Multicast mode is enabled, and GPIO interrupt is enabled for 82 edge detection, then GPIO<4..7> interrupts are per core */ 83 if (multi_cast.s.en && gpio_bit.s.int_en && gpio_bit.s.int_type) 84 { 85 /* Clear GPIO<4..7> per core */ 86 cvmx_ciu_intx_sum0_t ciu_sum0; 87 ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2)); 88 ciu_sum0.s.gpio = clear_mask & 0xf0; 89 cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64); 90 91 /* Clear other GPIO pins for all cores. */ 92 cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0)); 93 return; 94 } 95 } 96 /* Clear GPIO pins state across all cores and common interrupt states. */ 97 cvmx_gpio_int_clr_t gpio_int_clr; 98 gpio_int_clr.u64 = 0; 99 gpio_int_clr.s.type = clear_mask; 100 cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64); 101} 102 103/** 104 * GPIO Output Pin 105 * 106 * @param bit The GPIO to use 107 * @param mode Drive GPIO as output pin or not. 108 * 109 */ 110static inline void cvmx_gpio_cfg(int bit, int mode) 111{ 112 if (bit > 15 && bit < 20) 113 { 114 /* CN61XX/CN66XX has 20 GPIO pins and only 16 are interruptable. */ 115 if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) 116 { 117 cvmx_gpio_xbit_cfgx_t gpio_xbit; 118 gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit)); 119 if (mode) 120 gpio_xbit.s.tx_oe = 1; 121 else 122 gpio_xbit.s.tx_oe = 0; 123 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64); 124 } 125 else 126 cvmx_dprintf("cvmx_gpio_cfg: Invalid GPIO bit(%d)\n", bit); 127 } 128 else 129 { 130 cvmx_gpio_bit_cfgx_t gpio_bit; 131 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit)); 132 if (mode) 133 gpio_bit.s.tx_oe = 1; 134 else 135 gpio_bit.s.tx_oe = 0; 136 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64); 137 } 138} 139 140/** 141 * GPIO Read Data 142 * 143 * @return Status of the GPIO pins 144 */ 145static inline uint32_t cvmx_gpio_read(void) 146{ 147 cvmx_gpio_rx_dat_t gpio_rx_dat; 148 gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT); 149 return gpio_rx_dat.s.dat; 150} 151 152 153/** 154 * GPIO Clear pin 155 * 156 * @param clear_mask Bit mask to indicate which bits to drive to '0'. 157 */ 158static inline void cvmx_gpio_clear(uint32_t clear_mask) 159{ 160 cvmx_gpio_tx_clr_t gpio_tx_clr; 161 gpio_tx_clr.u64 = 0; 162 gpio_tx_clr.s.clr = clear_mask; 163 cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64); 164} 165 166 167/** 168 * GPIO Set pin 169 * 170 * @param set_mask Bit mask to indicate which bits to drive to '1'. 171 */ 172static inline void cvmx_gpio_set(uint32_t set_mask) 173{ 174 cvmx_gpio_tx_set_t gpio_tx_set; 175 gpio_tx_set.u64 = 0; 176 gpio_tx_set.s.set = set_mask; 177 cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64); 178} 179 180#ifdef __cplusplus 181} 182#endif 183 184#endif 185 186