1275861Sbr/*-
2275861Sbr * Copyright (c) 2012-2013 Robert N. M. Watson
3275861Sbr * Copyright (c) 2013-2014 SRI International
4275861Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5275861Sbr * All rights reserved.
6275861Sbr *
7275861Sbr * This software was developed by SRI International and the University of
8275861Sbr * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
9275861Sbr * ("CTSRD"), as part of the DARPA CRASH research programme.
10275861Sbr *
11275861Sbr * Redistribution and use in source and binary forms, with or without
12275861Sbr * modification, are permitted provided that the following conditions
13275861Sbr * are met:
14275861Sbr * 1. Redistributions of source code must retain the above copyright
15275861Sbr *    notice, this list of conditions and the following disclaimer.
16275861Sbr * 2. Redistributions in binary form must reproduce the above copyright
17275861Sbr *    notice, this list of conditions and the following disclaimer in the
18275861Sbr *    documentation and/or other materials provided with the distribution.
19275861Sbr *
20275861Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21275861Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22275861Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23275861Sbr * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24275861Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25275861Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26275861Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27275861Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28275861Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29275861Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30275861Sbr * SUCH DAMAGE.
31275861Sbr *
32275861Sbr * $FreeBSD: releng/11.0/sys/boot/fdt/dts/mips/beripad-sockit.dts 275861 2014-12-17 11:36:31Z br $
33275861Sbr */
34275861Sbr
35275861Sbr/dts-v1/;
36275861Sbr
37275861Sbr/*
38275861Sbr * Device names here have been largely made up on the spot, especially for the
39275861Sbr * "compatible" strings, and might want to be revised.
40275861Sbr */
41275861Sbr
42275861Sbr/ {
43275861Sbr	model = "SRI/Cambridge BeriPad (SoCKit)";
44275861Sbr	compatible = "sri-cambridge,beripad-sockit";
45275861Sbr	#address-cells = <1>;
46275861Sbr	#size-cells = <1>;
47275861Sbr
48275861Sbr	cpus {
49275861Sbr		#address-cells = <1>;
50275861Sbr		#size-cells = <1>;
51275861Sbr
52275861Sbr		/*
53275861Sbr		 * Secondary CPUs all start disabled and use the
54275861Sbr		 * spin-table enable method.  cpu-release-addr must be
55275861Sbr		 * specified for each cpu other than cpu@0.  Values of
56275861Sbr		 * cpu-release-addr grow down from 0x100000 (kernel).
57275861Sbr		 */
58275861Sbr		status = "disabled";
59275861Sbr		enable-method = "spin-table";
60275861Sbr
61275861Sbr		cpu@0 {
62275861Sbr			device-type = "cpu";
63275861Sbr			compatible = "sri-cambridge,beri";
64275861Sbr
65275861Sbr			reg = <0 1>;
66275861Sbr			status = "okay";
67275861Sbr		};
68275861Sbr
69275861Sbr/*
70275861Sbr		cpu@1 {
71275861Sbr			device-type = "cpu";
72275861Sbr			compatible = "sri-cambridge,beri";
73275861Sbr
74275861Sbr			reg = <1 1>;
75275861Sbr			// XXX: should we need cached prefix?
76275861Sbr			cpu-release-addr = <0xffffffff 0x800fffe0>;
77275861Sbr		};
78275861Sbr*/
79275861Sbr	};
80275861Sbr
81275861Sbr	memory {
82275861Sbr		device_type = "memory";
83275861Sbr		reg = <0x0 0x10000000>; /* 256MB at 0x0 */
84275861Sbr	};
85275861Sbr
86275861Sbr	soc {
87275861Sbr		#address-cells = <2>;
88275861Sbr		#size-cells = <2>;
89275861Sbr		#interrupt-cells = <1>;
90275861Sbr
91275861Sbr		/*
92275861Sbr		 * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
93275861Sbr		 * we use mips4k coprocessor 0 interrupt management directly.
94275861Sbr		 */
95275861Sbr		compatible = "simple-bus", "mips,mips4k";
96275861Sbr		/* ranges = <>; */
97275861Sbr
98275861Sbr		beripic0: beripic@7f804000 {
99275861Sbr			compatible = "sri-cambridge,beri-pic";
100275861Sbr			interrupt-controller;
101275861Sbr			#address-cells = <0>;
102275861Sbr			#interrupt-cells = <1>;
103275861Sbr			reg = <0x0 0x7f804000 0x0 0x400
104275861Sbr			       0x0 0x7f806000 0x0 0x10
105275861Sbr			       0x0 0x7f806080 0x0 0x10
106275861Sbr			       0x0 0x7f806100 0x0 0x10>;
107275861Sbr			interrupts = <0 1 2 3 4>;
108275861Sbr			hard-interrupt-sources = <64>;
109275861Sbr			soft-interrupt-sources = <64>;
110275861Sbr		};
111275861Sbr
112275861Sbr		pio0: pio@7f020000 {
113275861Sbr			compatible = "altr,pio";
114275861Sbr			reg = <0x0 0x7f020000 0x0 0x1000>; /* send */
115275861Sbr			interrupts = <4>; /* not used */
116275861Sbr			interrupt-parent = <&beripic0>;
117275861Sbr		};
118275861Sbr
119275861Sbr		pio1: pio@7f021000 {
120275861Sbr			compatible = "altr,pio";
121275861Sbr			reg = <0x0 0x7f021000 0x0 0x1000>; /* recv */
122275861Sbr			interrupts = <10>;
123275861Sbr			interrupt-parent = <&beripic0>;
124275861Sbr		};
125275861Sbr
126275861Sbr		pio2: pio@7f022000 {
127275861Sbr			compatible = "altr,pio";
128275861Sbr			reg = <0x0 0x7f022000 0x0 0x1000>; /* send */
129275861Sbr			interrupts = <5>; /* not used */
130275861Sbr			interrupt-parent = <&beripic0>;
131275861Sbr		};
132275861Sbr
133275861Sbr		pio3: pio@7f023000 {
134275861Sbr			compatible = "altr,pio";
135275861Sbr			reg = <0x0 0x7f023000 0x0 0x1000>; /* recv */
136275861Sbr			interrupts = <11>;
137275861Sbr			interrupt-parent = <&beripic0>;
138275861Sbr		};
139275861Sbr
140275861Sbr		virtio_mmio_platform0: virtio_mmio_platform@0 {
141275861Sbr			compatible = "beri,virtio_mmio_platform";
142275861Sbr			pio-send = <&pio0>;
143275861Sbr			pio-recv = <&pio1>;
144275861Sbr		};
145275861Sbr
146275861Sbr		virtio_mmio_platform1: virtio_mmio_platform@1 {
147275861Sbr			compatible = "beri,virtio_mmio_platform";
148275861Sbr			pio-send = <&pio2>;
149275861Sbr			pio-recv = <&pio3>;
150275861Sbr		};
151275861Sbr
152275861Sbr		virtio_block@200001000 {
153275861Sbr			compatible = "virtio,mmio";
154275861Sbr			reg = <0x2 0x1000 0x0 0x1000>;
155275861Sbr			platform = <&virtio_mmio_platform0>;
156275861Sbr			status = "okay";
157275861Sbr		};
158275861Sbr
159275861Sbr		virtio_net@200002000 {
160275861Sbr			compatible = "virtio,mmio";
161275861Sbr			reg = <0x2 0x2000 0x0 0x1000>;
162275861Sbr			platform = <&virtio_mmio_platform1>;
163275861Sbr			status = "okay";
164275861Sbr		};
165275861Sbr
166275861Sbr		serial@7f000000 {
167275861Sbr			compatible = "altera,jtag_uart-11_0";
168275861Sbr			reg = <0x0 0x7f000000 0x0 0x40>;
169275861Sbr			interrupts = <0>;
170275861Sbr			interrupt-parent = <&beripic0>;
171275861Sbr		};
172275861Sbr
173275861Sbr/*
174275861Sbr		serial@7f001000 {
175275861Sbr			compatible = "altera,jtag_uart-11_0";
176275861Sbr			reg = <0x7f001000 0x40>;
177275861Sbr		};
178275861Sbr
179275861Sbr		serial@7f002000 {
180275861Sbr			compatible = "altera,jtag_uart-11_0";
181275861Sbr			reg = <0x7f002000 0x40>;
182275861Sbr		};
183275861Sbr*/
184275861Sbr
185275861Sbr/*
186275861Sbr		led@7f006000 {
187275861Sbr			compatible = "sri-cambridge,de4led";
188275861Sbr			reg = <0x7f006000 0x1>;
189275861Sbr		};
190275861Sbr*/
191275861Sbr
192275861Sbr/*
193275861Sbr		avgen@0x7f009000 {
194275861Sbr			compatible = "sri-cambridge,avgen";
195275861Sbr			reg = <0x7f009000 0x2>;	
196275861Sbr			sri-cambridge,width = <1>;
197275861Sbr			sri-cambridge,fileio = "r";
198275861Sbr			sri-cambridge,devname = "de4bsw";
199275861Sbr		};
200275861Sbr*/
201275861Sbr
202275861Sbr/*
203275861Sbr		berirom@0x7f00a000 {
204275861Sbr			compatible = "sri-cambridge,berirom";
205275861Sbr			reg = <0x7f00a000 0x1000>;
206275861Sbr		};
207275861Sbr*/
208275861Sbr
209275861Sbr/*
210275861Sbr		avgen@0x7f00c000 {
211275861Sbr			compatible = "sri-cambridge,avgen";
212275861Sbr			reg = <0x7f00c000 0x8>;
213275861Sbr			sri-cambridge,width = <4>;
214275861Sbr			sri-cambridge,fileio = "rw";
215275861Sbr			sri-cambridge,devname = "de4tempfan";
216275861Sbr		};
217275861Sbr*/
218275861Sbr	};
219275861Sbr};
220