1273278Sbr/*- 2273278Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3273278Sbr * All rights reserved. 4273278Sbr * 5273278Sbr * This software was developed by SRI International and the University of 6273278Sbr * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7273278Sbr * ("CTSRD"), as part of the DARPA CRASH research programme. 8273278Sbr * 9273278Sbr * Redistribution and use in source and binary forms, with or without 10273278Sbr * modification, are permitted provided that the following conditions 11273278Sbr * are met: 12273278Sbr * 1. Redistributions of source code must retain the above copyright 13273278Sbr * notice, this list of conditions and the following disclaimer. 14273278Sbr * 2. Redistributions in binary form must reproduce the above copyright 15273278Sbr * notice, this list of conditions and the following disclaimer in the 16273278Sbr * documentation and/or other materials provided with the distribution. 17273278Sbr * 18273278Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19273278Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20273278Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21273278Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22273278Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23273278Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24273278Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25273278Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26273278Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27273278Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28273278Sbr * SUCH DAMAGE. 29273278Sbr * 30273278Sbr * $FreeBSD: releng/11.0/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts 275859 2014-12-17 10:48:53Z br $ 31273278Sbr */ 32273278Sbr 33273278Sbr/dts-v1/; 34273278Sbr 35273278Sbr/include/ "socfpga.dtsi" 36273278Sbr 37273278Sbr/ { 38273278Sbr model = "Terasic SoCKit"; 39273278Sbr compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 40273278Sbr 41275049Sbr memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ 42275647Sbr < 0x00001000 0x1000 >, /* virtio block */ 43275647Sbr < 0x00002000 0x1000 >; /* virtio net */ 44273278Sbr 45273278Sbr memory { 46273278Sbr device_type = "memory"; 47273278Sbr reg = < 0x00000000 0x40000000 >; /* 1G RAM */ 48273278Sbr }; 49273278Sbr 50273278Sbr SOC: socfpga { 51273278Sbr serial0: serial@ffc02000 { 52273278Sbr status = "okay"; 53273278Sbr }; 54273278Sbr 55273278Sbr usb1: usb@ffb40000 { 56273278Sbr status = "okay"; 57273278Sbr }; 58273278Sbr 59273278Sbr gmac1: ethernet@ff702000 { 60273278Sbr status = "okay"; 61273380Sbr 62273380Sbr rxd0-skew-ps = <0>; 63273380Sbr rxd1-skew-ps = <0>; 64273380Sbr rxd2-skew-ps = <0>; 65273380Sbr rxd3-skew-ps = <0>; 66273380Sbr txen-skew-ps = <0>; 67273380Sbr txc-skew-ps = <2600>; 68273380Sbr rxdv-skew-ps = <0>; 69273380Sbr rxc-skew-ps = <2000>; 70273278Sbr }; 71273278Sbr 72273278Sbr mmc: dwmmc@ff704000 { 73275049Sbr #address-cells = <1>; 74275049Sbr #size-cells = <0>; 75273278Sbr status = "okay"; 76273278Sbr num-slots = <1>; 77273278Sbr supports-highspeed; 78273278Sbr broken-cd; 79273278Sbr bus-frequency = <25000000>; 80273278Sbr 81273278Sbr slot@0 { 82273278Sbr reg = <0>; 83273278Sbr bus-width = <4>; 84273380Sbr }; 85273278Sbr }; 86273278Sbr 87275049Sbr beri_mem0: mem@d0000000 { 88273469Sbr compatible = "sri-cambridge,beri-mem"; 89275049Sbr reg = <0xd0000000 0x10000000>; /* 256mb */ 90273469Sbr status = "okay"; 91273469Sbr }; 92273469Sbr 93275049Sbr pio0: pio@c0020000 { 94275049Sbr compatible = "altr,pio"; 95275049Sbr reg = <0xc0020000 0x1000>; /* recv */ 96275049Sbr interrupts = < 76 >; 97275049Sbr interrupt-parent = <&GIC>; 98275049Sbr status = "okay"; 99275049Sbr }; 100275049Sbr 101275049Sbr pio1: pio@c0021000 { 102275049Sbr compatible = "altr,pio"; 103275049Sbr reg = <0xc0021000 0x1000>; /* send */ 104275049Sbr interrupts = < 82 >; /* not in use on arm side */ 105275049Sbr interrupt-parent = <&GIC>; 106275049Sbr status = "okay"; 107275049Sbr }; 108275049Sbr 109275859Sbr pio2: pio@c0022000 { 110275859Sbr compatible = "altr,pio"; 111275859Sbr reg = <0xc0022000 0x1000>; /* recv */ 112275859Sbr interrupts = < 77 >; 113275859Sbr interrupt-parent = <&GIC>; 114275859Sbr status = "okay"; 115275859Sbr }; 116275859Sbr 117275859Sbr pio3: pio@c0023000 { 118275859Sbr compatible = "altr,pio"; 119275859Sbr reg = <0xc0023000 0x1000>; /* send */ 120275859Sbr interrupts = < 83 >; /* not in use on arm side */ 121275859Sbr interrupt-parent = <&GIC>; 122275859Sbr status = "okay"; 123275859Sbr }; 124275859Sbr 125275049Sbr beri_vtblk: vtblk@00001000 { 126275049Sbr compatible = "sri-cambridge,beri-vtblk"; 127275049Sbr reg = <0x00001000 0x1000>; 128275049Sbr pio-recv = <&pio0>; 129275049Sbr pio-send = <&pio1>; 130275049Sbr beri-mem = <&beri_mem0>; 131275859Sbr status = "okay"; 132275647Sbr }; 133275647Sbr 134275647Sbr beri_vtnet: vtnet@00002000 { 135275647Sbr compatible = "sri-cambridge,beri-vtnet"; 136275647Sbr reg = <0x00002000 0x1000>; 137275859Sbr pio-recv = <&pio2>; 138275859Sbr pio-send = <&pio3>; 139275647Sbr beri-mem = <&beri_mem0>; 140275049Sbr status = "okay"; 141275049Sbr }; 142275049Sbr 143273278Sbr beri_debug: ring@c0000000 { 144273278Sbr compatible = "sri-cambridge,beri-ring"; 145273278Sbr reg = <0xc0000000 0x3000>; 146273278Sbr interrupts = < 72 73 >; 147273278Sbr interrupt-parent = <&GIC>; 148273278Sbr device_name = "beri_debug"; 149273278Sbr data_size = <0x1000>; 150273278Sbr data_read = <0x0>; 151273278Sbr data_write = <0x1000>; 152273278Sbr control_read = <0x2000>; 153273278Sbr control_write = <0x2010>; 154273278Sbr status = "okay"; 155273278Sbr }; 156273278Sbr 157273278Sbr beri_console: ring@c0004000 { 158273278Sbr compatible = "sri-cambridge,beri-ring"; 159273278Sbr reg = <0xc0004000 0x3000>; 160273278Sbr interrupts = < 74 75 >; 161273278Sbr interrupt-parent = <&GIC>; 162273278Sbr device_name = "beri_console"; 163273278Sbr data_size = <0x1000>; 164273278Sbr data_read = <0x0>; 165273278Sbr data_write = <0x1000>; 166273278Sbr control_read = <0x2000>; 167273278Sbr control_write = <0x2010>; 168273278Sbr status = "okay"; 169273278Sbr }; 170273278Sbr }; 171273278Sbr 172273278Sbr chosen { 173273278Sbr bootargs = "-v"; 174273278Sbr stdin = "serial0"; 175273278Sbr stdout = "serial0"; 176273278Sbr }; 177273278Sbr}; 178