1/*-
2 * Copyright (c) 2015 John Wehle <john@feith.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: releng/11.0/sys/boot/fdt/dts/arm/meson3.dtsi 283361 2015-05-24 08:45:19Z ganbold $
27 */
28
29/*
30 * The basic single core aml8726 (aka meson) uses an Amlogic interrupt
31 * controller, however meson.dtsi specifies GIC (which is present on
32 * the multicore aml8726) so we need to override things here.
33 */
34
35/include/ "meson.dtsi"
36
37/ {
38	model = "Amlogic Meson3 SoC";
39	compatible = "amlogic,meson3";
40
41	interrupt-parent = <&pic>;
42
43	pic: pic@c1109a40 {
44		device_type = "interrupt-controller";
45		compatible = "amlogic,aml8726-pic";
46		reg = <0xc1109a40 128>; /* cbus 0x2690 */
47
48		interrupt-controller;
49		#interrupt-cells = <3>;
50	};
51
52	cpus {
53		#address-cells = <1>;
54		#size-cells = <0>;
55
56		cpu@200 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a9";
59			next-level-cache = <&L2>;
60			reg = <0x200>;
61		};
62	};
63
64	clk81: clk@0 {
65		#clock-cells = <0>;
66		compatible = "fixed-clock";
67		clock-frequency = <0>;
68	};
69};
70
71&gic {
72	status = "disabled";
73};
74
75&L2 {
76	interrupts = <0 61 1>;
77};
78