1/* 2 * Device Tree Include file for Marvell Armada 38x family of SoCs. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 * 48 * $FreeBSD: releng/11.0/sys/boot/fdt/dts/arm/armada-38x.dtsi 301225 2016-06-02 18:41:33Z zbb $ 49 */ 50 51#include "skeleton.dtsi" 52#include <dt-bindings/interrupt-controller/arm-gic.h> 53#include <dt-bindings/interrupt-controller/irq.h> 54 55#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 56 57/ { 58 model = "Marvell Armada 38x family SoC"; 59 compatible = "marvell,armada380"; 60 61 aliases { 62 gpio0 = &gpio0; 63 gpio1 = &gpio1; 64 serial0 = &uart0; 65 serial1 = &uart1; 66 sram0 = &SRAM0; 67 sram1 = &SRAM1; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a9-pmu"; 72 interrupts-extended = <&mpic 3>; 73 }; 74 75 SRAM0: sram@f1100000 { 76 compatible = "mrvl,cesa-sram"; 77 reg = <0xf1100000 0x0010000>; 78 }; 79 80 SRAM1: sram@f1110000 { 81 compatible = "mrvl,cesa-sram"; 82 reg = <0xf1110000 0x0010000>; 83 }; 84 85 soc { 86 compatible = "marvell,armada380-mbus", "simple-bus"; 87 #address-cells = <2>; 88 #size-cells = <1>; 89 controller = <&mbusc>; 90 interrupt-parent = <&gic>; 91 pcie-mem-aperture = <0xe0000000 0x8000000>; 92 pcie-io-aperture = <0xe8000000 0x100000>; 93 94 bootrom { 95 compatible = "marvell,bootrom"; 96 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 97 }; 98 99 devbus-bootcs { 100 compatible = "marvell,mvebu-devbus"; 101 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 102 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 clocks = <&coreclk 0>; 106 status = "disabled"; 107 }; 108 109 devbus-cs0 { 110 compatible = "marvell,mvebu-devbus"; 111 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 112 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 clocks = <&coreclk 0>; 116 status = "disabled"; 117 }; 118 119 devbus-cs1 { 120 compatible = "marvell,mvebu-devbus"; 121 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 122 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 clocks = <&coreclk 0>; 126 status = "disabled"; 127 }; 128 129 devbus-cs2 { 130 compatible = "marvell,mvebu-devbus"; 131 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 132 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 clocks = <&coreclk 0>; 136 status = "disabled"; 137 }; 138 139 devbus-cs3 { 140 compatible = "marvell,mvebu-devbus"; 141 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 142 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 clocks = <&coreclk 0>; 146 status = "disabled"; 147 }; 148 149 internal-regs { 150 compatible = "simple-bus"; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 154 155 crypto@90000 { 156 compatible = "mrvl,cesa"; 157 reg = <0x90000 0x10000>; 158 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 159 interrupt-parent = <&gic>; 160 sram-handle = <&SRAM0>; 161 status = "disabled"; 162 }; 163 164 crypto@92000 { 165 compatible = "mrvl,cesa"; 166 reg = <0x92000 0x1000 /* tdma base reg chan 1 */ 167 0x9F000 0x1000>; /* cesa base reg chan 1 */ 168 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-parent = <&gic>; 170 sram-handle = <&SRAM1>; 171 status = "disabled"; 172 }; 173 174 L2: cache-controller@8000 { 175 compatible = "arm,pl310-cache"; 176 reg = <0x8000 0x1000>; 177 cache-unified; 178 cache-level = <2>; 179 }; 180 181 scu@c000 { 182 compatible = "arm,cortex-a9-scu"; 183 reg = <0xc000 0x58>; 184 }; 185 186 timer@c200 { 187 compatible = "arm,cortex-a9-global-timer"; 188 reg = <0xc200 0x20>; 189 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 190 clock-frequency = <800000000>; 191 clocks = <&coreclk 2>; 192 }; 193 194 timer@c600 { 195 compatible = "arm,cortex-a9-twd-timer"; 196 reg = <0xc600 0x20>; 197 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 198 clock-frequency = <800000000>; 199 clocks = <&coreclk 2>; 200 }; 201 202 gic: interrupt-controller@d000 { 203 compatible = "arm,cortex-a9-gic"; 204 #interrupt-cells = <3>; 205 #size-cells = <0>; 206 interrupt-controller; 207 reg = <0xd000 0x1000>, 208 <0xc100 0x100>; 209 }; 210 211 spi0: spi@10600 { 212 compatible = "marvell,armada-380-spi", 213 "marvell,orion-spi"; 214 reg = <0x10600 0x50>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 cell-index = <0>; 218 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&coreclk 0>; 220 status = "disabled"; 221 }; 222 223 spi1: spi@10680 { 224 compatible = "marvell,armada-380-spi", 225 "marvell,orion-spi"; 226 reg = <0x10680 0x50>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 cell-index = <1>; 230 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&coreclk 0>; 232 status = "disabled"; 233 }; 234 235 i2c0: i2c@11000 { 236 compatible = "marvell,mv64xxx-i2c"; 237 reg = <0x11000 0x20>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 241 timeout-ms = <1000>; 242 clocks = <&coreclk 0>; 243 status = "disabled"; 244 }; 245 246 i2c1: i2c@11100 { 247 compatible = "marvell,mv64xxx-i2c"; 248 reg = <0x11100 0x20>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 252 timeout-ms = <1000>; 253 clocks = <&coreclk 0>; 254 status = "disabled"; 255 }; 256 257 uart0: serial@12000 { 258 compatible = "snps,dw-apb-uart"; 259 reg = <0x12000 0x100>; 260 reg-shift = <2>; 261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 262 reg-io-width = <1>; 263 clocks = <&coreclk 0>; 264 status = "disabled"; 265 }; 266 267 uart1: serial@12100 { 268 compatible = "snps,dw-apb-uart"; 269 reg = <0x12100 0x100>; 270 reg-shift = <2>; 271 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 272 reg-io-width = <1>; 273 clocks = <&coreclk 0>; 274 status = "disabled"; 275 }; 276 277 pinctrl: pinctrl@18000 { 278 reg = <0x18000 0x20>; 279 280 ge0_rgmii_pins: ge-rgmii-pins-0 { 281 marvell,pins = "mpp6", "mpp7", "mpp8", 282 "mpp9", "mpp10", "mpp11", 283 "mpp12", "mpp13", "mpp14", 284 "mpp15", "mpp16", "mpp17"; 285 marvell,function = "ge0"; 286 }; 287 288 ge1_rgmii_pins: ge-rgmii-pins-1 { 289 marvell,pins = "mpp21", "mpp27", "mpp28", 290 "mpp29", "mpp30", "mpp31", 291 "mpp32", "mpp37", "mpp38", 292 "mpp39", "mpp40", "mpp41"; 293 marvell,function = "ge1"; 294 }; 295 296 i2c0_pins: i2c-pins-0 { 297 marvell,pins = "mpp2", "mpp3"; 298 marvell,function = "i2c0"; 299 }; 300 301 mdio_pins: mdio-pins { 302 marvell,pins = "mpp4", "mpp5"; 303 marvell,function = "ge"; 304 }; 305 306 ref_clk0_pins: ref-clk-pins-0 { 307 marvell,pins = "mpp45"; 308 marvell,function = "ref"; 309 }; 310 311 ref_clk1_pins: ref-clk-pins-1 { 312 marvell,pins = "mpp46"; 313 marvell,function = "ref"; 314 }; 315 316 spi0_pins: spi-pins-0 { 317 marvell,pins = "mpp22", "mpp23", "mpp24", 318 "mpp25"; 319 marvell,function = "spi0"; 320 }; 321 322 spi1_pins: spi-pins-1 { 323 marvell,pins = "mpp56", "mpp57", "mpp58", 324 "mpp59"; 325 marvell,function = "spi1"; 326 }; 327 328 uart0_pins: uart-pins-0 { 329 marvell,pins = "mpp0", "mpp1"; 330 marvell,function = "ua0"; 331 }; 332 333 uart1_pins: uart-pins-1 { 334 marvell,pins = "mpp19", "mpp20"; 335 marvell,function = "ua1"; 336 }; 337 338 sdhci_pins: sdhci-pins { 339 marvell,pins = "mpp48", "mpp49", "mpp50", 340 "mpp52", "mpp53", "mpp54", 341 "mpp55", "mpp57", "mpp58", 342 "mpp59"; 343 marvell,function = "sd0"; 344 }; 345 346 sata0_pins: sata-pins-0 { 347 marvell,pins = "mpp20"; 348 marvell,function = "sata0"; 349 }; 350 351 sata1_pins: sata-pins-1 { 352 marvell,pins = "mpp19"; 353 marvell,function = "sata1"; 354 }; 355 356 sata2_pins: sata-pins-2 { 357 marvell,pins = "mpp47"; 358 marvell,function = "sata2"; 359 }; 360 361 sata3_pins: sata-pins-3 { 362 marvell,pins = "mpp44"; 363 marvell,function = "sata3"; 364 }; 365 }; 366 367 gpio0: gpio@18100 { 368 compatible = "marvell,orion-gpio"; 369 reg = <0x18100 0x40>; 370 ngpios = <32>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 379 }; 380 381 gpio1: gpio@18140 { 382 compatible = "marvell,orion-gpio"; 383 reg = <0x18140 0x40>; 384 ngpios = <28>; 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 395 system-controller@18200 { 396 compatible = "marvell,armada-380-system-controller", 397 "marvell,armada-370-xp-system-controller"; 398 reg = <0x18200 0x100>; 399 }; 400 401 gateclk: clock-gating-control@18220 { 402 compatible = "marvell,armada-380-gating-clock"; 403 reg = <0x18220 0x4>; 404 clocks = <&coreclk 0>; 405 #clock-cells = <1>; 406 }; 407 408 coreclk: mvebu-sar@18600 { 409 compatible = "marvell,armada-380-core-clock"; 410 reg = <0x18600 0x04>; 411 #clock-cells = <1>; 412 }; 413 414 mbusc: mbus-controller@20000 { 415 compatible = "marvell,mbus-controller"; 416 reg = <0x20000 0x100>, <0x20180 0x20>; 417 }; 418 419 mpic: interrupt-controller@20a00 { 420 compatible = "marvell,mpic"; 421 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 422 #interrupt-cells = <1>; 423 #size-cells = <1>; 424 interrupt-controller; 425 msi-controller; 426 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 427 }; 428 429 timer@20300 { 430 compatible = "marvell,armada-380-timer", 431 "marvell,armada-xp-timer"; 432 reg = <0x20300 0x30>, <0x21040 0x30>; 433 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 434 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 435 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 436 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 437 <&mpic 5>, 438 <&mpic 6>; 439 clocks = <&coreclk 2>, <&refclk>; 440 clock-names = "nbclk", "fixed"; 441 }; 442 443 watchdog@20300 { 444 compatible = "marvell,armada-380-wdt"; 445 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 446 clocks = <&coreclk 2>, <&refclk>; 447 clock-names = "nbclk", "fixed"; 448 }; 449 450 cpurst@20800 { 451 compatible = "marvell,armada-370-cpu-reset"; 452 reg = <0x20800 0x10>; 453 }; 454 455 mpcore-soc-ctrl@20d20 { 456 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 457 reg = <0x20d20 0x6c>; 458 }; 459 460 coherency-fabric@21010 { 461 compatible = "marvell,armada-380-coherency-fabric"; 462 reg = <0x21010 0x1c>; 463 }; 464 465 pmsu@22000 { 466 compatible = "marvell,armada-380-pmsu"; 467 reg = <0x22000 0x1000>; 468 }; 469 470 eth1: ethernet@30000 { 471 compatible = "marvell,armada-370-neta"; 472 reg = <0x30000 0x4000>; 473 interrupts-extended = <&mpic 10>; 474 clocks = <&gateclk 3>; 475 status = "disabled"; 476 }; 477 478 eth2: ethernet@34000 { 479 compatible = "marvell,armada-370-neta"; 480 reg = <0x34000 0x4000>; 481 interrupts-extended = <&mpic 12>; 482 clocks = <&gateclk 2>; 483 status = "disabled"; 484 }; 485 486 usb@58000 { 487 compatible = "marvell,orion-ehci"; 488 reg = <0x58000 0x500>; 489 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&gateclk 18>; 491 status = "disabled"; 492 }; 493 494 xor@60800 { 495 compatible = "marvell,orion-xor"; 496 reg = <0x60800 0x100 497 0x60a00 0x100>; 498 clocks = <&gateclk 22>; 499 status = "okay"; 500 501 xor00 { 502 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 503 dmacap,memcpy; 504 dmacap,xor; 505 }; 506 xor01 { 507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 508 dmacap,memcpy; 509 dmacap,xor; 510 dmacap,memset; 511 }; 512 }; 513 514 xor@60900 { 515 compatible = "marvell,orion-xor"; 516 reg = <0x60900 0x100 517 0x60b00 0x100>; 518 clocks = <&gateclk 28>; 519 status = "okay"; 520 521 xor10 { 522 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 523 dmacap,memcpy; 524 dmacap,xor; 525 }; 526 xor11 { 527 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 528 dmacap,memcpy; 529 dmacap,xor; 530 dmacap,memset; 531 }; 532 }; 533 534 eth0: ethernet@70000 { 535 compatible = "marvell,armada-370-neta"; 536 reg = <0x70000 0x4000>; 537 interrupts-extended = <&mpic 8>; 538 clocks = <&gateclk 4>; 539 status = "disabled"; 540 }; 541 542 mdio: mdio@72004 { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 compatible = "marvell,orion-mdio"; 546 reg = <0x72004 0x4>; 547 clocks = <&gateclk 4>; 548 }; 549 550 rtc@a3800 { 551 compatible = "marvell,armada-380-rtc"; 552 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 553 reg-names = "rtc", "rtc-soc"; 554 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 555 }; 556 557 sata@a8000 { 558 compatible = "marvell,armada-380-ahci"; 559 reg = <0xa8000 0x2000>; 560 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&gateclk 15>; 562 status = "disabled"; 563 }; 564 565 sata@e0000 { 566 compatible = "marvell,armada-380-ahci"; 567 reg = <0xe0000 0x2000>; 568 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&gateclk 30>; 570 status = "disabled"; 571 }; 572 573 coredivclk: clock@e4250 { 574 compatible = "marvell,armada-380-corediv-clock"; 575 reg = <0xe4250 0xc>; 576 #clock-cells = <1>; 577 clocks = <&mainpll>; 578 clock-output-names = "nand"; 579 }; 580 581 thermal@e8078 { 582 compatible = "marvell,armada380-thermal"; 583 reg = <0xe4078 0x4>, <0xe4074 0x4>; 584 status = "okay"; 585 }; 586 587 flash@d0000 { 588 compatible = "marvell,armada370-nand"; 589 reg = <0xd0000 0x54>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&coredivclk 0>; 594 status = "disabled"; 595 }; 596 597 sdhci@d8000 { 598 compatible = "marvell,armada-380-sdhci"; 599 reg-names = "sdhci", "mbus", "conf-sdio3"; 600 reg = <0xd8000 0x1000>, 601 <0xdc000 0x100>, 602 <0x18454 0x4>; 603 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&gateclk 17>; 605 mrvl,clk-delay-cycles = <0x1F>; 606 status = "disabled"; 607 }; 608 609 usb3@f0000 { 610 compatible = "marvell,armada-380-xhci"; 611 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 612 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&gateclk 9>; 614 status = "disabled"; 615 }; 616 617 usb3@f8000 { 618 compatible = "marvell,armada-380-xhci"; 619 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 620 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&gateclk 10>; 622 status = "disabled"; 623 }; 624 }; 625 }; 626 627 pci0: pcie@f1080000 { 628 compatible = "mrvl,pcie"; 629 status = "disabled"; 630 device_type = "pci"; 631 #interrupt-cells = <3>; 632 #size-cells = <2>; 633 #address-cells = <3>; 634 reg = <0xf1080000 0x2000>; 635 bus-range = <0 255>; 636 ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000 637 0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>; 638 interrupt-parent = <&gic>; 639 interrupts = <GIC_SPI 91 0>; 640 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 641 interrupt-map = < 642 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 643 >; 644 }; 645 646 clocks { 647 /* 2 GHz fixed main PLL */ 648 mainpll: mainpll { 649 compatible = "fixed-clock"; 650 #clock-cells = <0>; 651 clock-frequency = <1000000000>; 652 }; 653 654 /* 25 MHz reference crystal */ 655 refclk: oscillator { 656 compatible = "fixed-clock"; 657 #clock-cells = <0>; 658 clock-frequency = <25000000>; 659 }; 660 }; 661}; 662