avila_machdep.c revision 194784
1/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * machdep.c 40 * 41 * Machine dependant functions for kernel setup 42 * 43 * This file needs a lot of work. 44 * 45 * Created : 17/09/94 46 */ 47 48#include "opt_msgbuf.h" 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/avila_machdep.c 194784 2009-06-23 22:42:39Z jeff $"); 52 53#define _ARM32_BUS_DMA_PRIVATE 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sysproto.h> 57#include <sys/signalvar.h> 58#include <sys/imgact.h> 59#include <sys/kernel.h> 60#include <sys/ktr.h> 61#include <sys/linker.h> 62#include <sys/lock.h> 63#include <sys/malloc.h> 64#include <sys/mutex.h> 65#include <sys/pcpu.h> 66#include <sys/proc.h> 67#include <sys/ptrace.h> 68#include <sys/cons.h> 69#include <sys/bio.h> 70#include <sys/bus.h> 71#include <sys/buf.h> 72#include <sys/exec.h> 73#include <sys/kdb.h> 74#include <sys/msgbuf.h> 75#include <machine/reg.h> 76#include <machine/cpu.h> 77 78#include <vm/vm.h> 79#include <vm/pmap.h> 80#include <vm/vm_object.h> 81#include <vm/vm_page.h> 82#include <vm/vm_pager.h> 83#include <vm/vm_map.h> 84#include <vm/vnode_pager.h> 85#include <machine/pmap.h> 86#include <machine/vmparam.h> 87#include <machine/pcb.h> 88#include <machine/undefined.h> 89#include <machine/machdep.h> 90#include <machine/metadata.h> 91#include <machine/armreg.h> 92#include <machine/bus.h> 93#include <sys/reboot.h> 94 95#include <arm/xscale/ixp425/ixp425reg.h> 96#include <arm/xscale/ixp425/ixp425var.h> 97 98/* kernel text starts where we were loaded at boot */ 99#define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR) 100#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) 101#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) 102 103#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 104#define KERNEL_PT_IO 1 105#define KERNEL_PT_IO_NUM 3 106#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM 107#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */ 108#define KERNEL_PT_AFKERNEL_NUM 9 109 110/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 111#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 112 113/* Define various stack sizes in pages */ 114#define IRQ_STACK_SIZE 1 115#define ABT_STACK_SIZE 1 116#define UND_STACK_SIZE 1 117 118extern u_int data_abort_handler_address; 119extern u_int prefetch_abort_handler_address; 120extern u_int undefined_handler_address; 121 122struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 123 124extern void *_end; 125 126extern int *end; 127 128struct pcpu __pcpu; 129struct pcpu *pcpup = &__pcpu; 130 131/* Physical and virtual addresses for some global pages */ 132 133vm_paddr_t phys_avail[10]; 134vm_paddr_t dump_avail[4]; 135vm_offset_t physical_pages; 136 137struct pv_addr systempage; 138struct pv_addr msgbufpv; 139struct pv_addr irqstack; 140struct pv_addr undstack; 141struct pv_addr abtstack; 142struct pv_addr kernelstack; 143struct pv_addr minidataclean; 144 145static struct trapframe proc0_tf; 146 147/* Static device mappings. */ 148static const struct pmap_devmap ixp425_devmap[] = { 149 /* Physical/Virtual address for I/O space */ 150 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 151 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 152 153 /* Expansion Bus */ 154 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 155 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 156 157 /* CFI Flash on the Expansion Bus */ 158 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 159 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 160 161 /* IXP425 PCI Configuration */ 162 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 163 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 164 165 /* SDRAM Controller */ 166 { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, 167 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 168 169 /* PCI Memory Space */ 170 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 171 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 172 173 /* Q-Mgr Memory Space */ 174 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 175 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 176 177 { 0 }, 178}; 179 180/* Static device mappings. */ 181static const struct pmap_devmap ixp435_devmap[] = { 182 /* Physical/Virtual address for I/O space */ 183 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 184 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 185 186 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 187 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 188 189 /* IXP425 PCI Configuration */ 190 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 191 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 192 193 /* DDRII Controller NB: mapped same place as IXP425 */ 194 { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, 195 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 196 197 /* PCI Memory Space */ 198 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 199 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 200 201 /* Q-Mgr Memory Space */ 202 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 203 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 204 205 /* CFI Flash on the Expansion Bus */ 206 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 207 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 208 209 /* USB1 Memory Space */ 210 { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, 211 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 212 /* USB2 Memory Space */ 213 { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, 214 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 215 216 /* GPS Memory Space */ 217 { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, 218 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 219 220 /* RS485 Memory Space */ 221 { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, 222 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 223 224 { 0 } 225}; 226 227extern vm_offset_t xscale_cache_clean_addr; 228 229void * 230initarm(void *arg, void *arg2) 231{ 232#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) 233#define next_page(a) next_chunk2(a,PAGE_SIZE) 234 struct pv_addr kernel_l1pt; 235 struct pv_addr dpcpu; 236 int loop, i; 237 u_int l1pagetable; 238 vm_offset_t freemempos; 239 vm_offset_t freemem_pt; 240 vm_offset_t afterkern; 241 vm_offset_t freemem_after; 242 vm_offset_t lastaddr; 243 uint32_t memsize; 244 245 set_cpufuncs(); /* NB: sets cputype */ 246 lastaddr = fake_preload_metadata(); 247 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 248 PCPU_SET(curthread, &thread0); 249 250 /* 251 * We allocate memory downwards from where we were loaded 252 * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS 253 * entries in the L2 page table. Past that we re-align the 254 * allocation boundary so later data structures (stacks, etc) 255 * can be mapped with different attributes (write-back vs 256 * write-through). Note this leaves a gap for expansion 257 * (or might be repurposed). 258 */ 259 freemempos = KERNPHYSADDR; 260 261 /* macros to simplify initial memory allocation */ 262#define alloc_pages(var, np) do { \ 263 freemempos -= (np * PAGE_SIZE); \ 264 (var) = freemempos; \ 265 /* NB: this works because locore maps PA=VA */ \ 266 memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ 267} while (0) 268#define valloc_pages(var, np) do { \ 269 alloc_pages((var).pv_pa, (np)); \ 270 (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \ 271} while (0) 272 273 /* force L1 page table alignment */ 274 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 275 freemempos -= PAGE_SIZE; 276 /* allocate contiguous L1 page table */ 277 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 278 /* now allocate L2 page tables; they are linked to L1 below */ 279 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 280 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 281 valloc_pages(kernel_pt_table[loop], 282 L2_TABLE_SIZE / PAGE_SIZE); 283 } else { 284 kernel_pt_table[loop].pv_pa = freemempos + 285 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 286 L2_TABLE_SIZE_REAL; 287 kernel_pt_table[loop].pv_va = 288 kernel_pt_table[loop].pv_pa + 289 (KERNVIRTADDR - KERNPHYSADDR); 290 } 291 } 292 freemem_pt = freemempos; /* base of allocated pt's */ 293 294 /* 295 * Re-align allocation boundary so we can map the area 296 * write-back instead of write-through for the stacks and 297 * related structures allocated below. 298 */ 299 freemempos = PHYSADDR + 0x100000; 300 /* 301 * Allocate a page for the system page mapped to V0x00000000 302 * This page will just contain the system vectors and can be 303 * shared by all processes. 304 */ 305 valloc_pages(systempage, 1); 306 307 /* Allocate dynamic per-cpu area. */ 308 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 309 dpcpu_init((void *)dpcpu.pv_va, 0); 310 311 /* Allocate stacks for all modes */ 312 valloc_pages(irqstack, IRQ_STACK_SIZE); 313 valloc_pages(abtstack, ABT_STACK_SIZE); 314 valloc_pages(undstack, UND_STACK_SIZE); 315 valloc_pages(kernelstack, KSTACK_PAGES); 316 alloc_pages(minidataclean.pv_pa, 1); 317 valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE); 318#ifdef ARM_USE_SMALL_ALLOC 319 freemempos -= PAGE_SIZE; 320 freemem_pt = trunc_page(freemem_pt); 321 freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) / 322 PAGE_SIZE) * sizeof(struct arm_small_page); 323 arm_add_smallalloc_pages( 324 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 325 (void *)0xc0100000, 326 freemem_pt - (PHYSADDR + 0x100000), 1); 327 freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) * 328 sizeof(struct arm_small_page); 329 arm_add_smallalloc_pages( 330 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 331 (void *)0xc0001000, 332 trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0); 333 freemempos = trunc_page(freemem_after); 334 freemempos -= PAGE_SIZE; 335#endif 336 337 /* 338 * Now construct the L1 page table. First map the L2 339 * page tables into the L1 so we can replace L1 mappings 340 * later on if necessary 341 */ 342 l1pagetable = kernel_l1pt.pv_va; 343 344 /* Map the L2 pages tables in the L1 page table */ 345 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), 346 &kernel_pt_table[KERNEL_PT_SYS]); 347 pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE, 348 &kernel_pt_table[KERNEL_PT_IO]); 349 pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE, 350 &kernel_pt_table[KERNEL_PT_IO + 1]); 351 pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE, 352 &kernel_pt_table[KERNEL_PT_IO + 2]); 353 pmap_link_l2pt(l1pagetable, KERNBASE, 354 &kernel_pt_table[KERNEL_PT_BEFOREKERN]); 355 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000, 356 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 357 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, 358 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 359 pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, 360 next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), 361 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 362 freemem_after = next_page((int)lastaddr); 363 afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); 364 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 365 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 366 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 367 } 368 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 369 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 370 371#ifdef ARM_USE_SMALL_ALLOC 372 if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) { 373 arm_add_smallalloc_pages((void *)(freemem_after), 374 (void*)(freemem_after + PAGE_SIZE), 375 afterkern - (freemem_after + PAGE_SIZE), 0); 376 377 } 378#endif 379 380 /* Map the Mini-Data cache clean area. */ 381 xscale_setup_minidata(l1pagetable, afterkern, 382 minidataclean.pv_pa); 383 384 /* Map the vector page. */ 385 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 386 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 387 if (cpu_is_ixp43x()) 388 pmap_devmap_bootstrap(l1pagetable, ixp435_devmap); 389 else 390 pmap_devmap_bootstrap(l1pagetable, ixp425_devmap); 391 /* 392 * Give the XScale global cache clean code an appropriately 393 * sized chunk of unmapped VA space starting at 0xff000000 394 * (our device mappings end before this address). 395 */ 396 xscale_cache_clean_addr = 0xff000000U; 397 398 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 399 setttb(kernel_l1pt.pv_pa); 400 cpu_tlb_flushID(); 401 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 402 403 /* 404 * Pages were allocated during the secondary bootstrap for the 405 * stacks for different CPU modes. 406 * We must now set the r13 registers in the different CPU modes to 407 * point to these stacks. 408 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 409 * of the stack memory. 410 */ 411 set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE); 412 set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE); 413 set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE); 414 415 /* 416 * We must now clean the cache again.... 417 * Cleaning may be done by reading new data to displace any 418 * dirty data in the cache. This will have happened in setttb() 419 * but since we are boot strapping the addresses used for the read 420 * may have just been remapped and thus the cache could be out 421 * of sync. A re-clean after the switch will cure this. 422 * After booting there are no gross relocations of the kernel thus 423 * this problem will not occur after initarm(). 424 */ 425 cpu_idcache_wbinv_all(); 426 /* ready to setup the console (XXX move earlier if possible) */ 427 cninit(); 428 /* 429 * Fetch the RAM size from the MCU registers. The 430 * expansion bus was mapped above so we can now read 'em. 431 */ 432 if (cpu_is_ixp43x()) 433 memsize = ixp435_ddram_size(); 434 else 435 memsize = ixp425_sdram_size(); 436 physmem = memsize / PAGE_SIZE; 437 438 /* Set stack for exception handlers */ 439 440 data_abort_handler_address = (u_int)data_abort_handler; 441 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 442 undefined_handler_address = (u_int)undefinedinstruction_bounce; 443 undefined_init(); 444 445 proc_linkup0(&proc0, &thread0); 446 thread0.td_kstack = kernelstack.pv_va; 447 thread0.td_pcb = (struct pcb *) 448 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 449 thread0.td_pcb->pcb_flags = 0; 450 thread0.td_frame = &proc0_tf; 451 pcpup->pc_curpcb = thread0.td_pcb; 452 453 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 454 455 pmap_curmaxkvaddr = afterkern + PAGE_SIZE; 456 dump_avail[0] = PHYSADDR; 457 dump_avail[1] = PHYSADDR + memsize; 458 dump_avail[2] = 0; 459 dump_avail[3] = 0; 460 461 pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); 462 msgbufp = (void*)msgbufpv.pv_va; 463 msgbufinit(msgbufp, MSGBUF_SIZE); 464 mutex_init(); 465 466 i = 0; 467#ifdef ARM_USE_SMALL_ALLOC 468 phys_avail[i++] = PHYSADDR; 469 phys_avail[i++] = PHYSADDR + PAGE_SIZE; /* 470 *XXX: Gross hack to get our 471 * pages in the vm_page_array. 472 */ 473#endif 474 phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR); 475 phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1); 476 phys_avail[i++] = 0; 477 phys_avail[i] = 0; 478 479 /* Do basic tuning, hz etc */ 480 init_param1(); 481 init_param2(physmem); 482 kdb_init(); 483 484 /* use static kernel environment if so configured */ 485 if (envmode == 1) 486 kern_envp = static_env; 487 488 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 489 sizeof(struct pcb))); 490#undef next_page 491#undef next_chunk2 492} 493