exynos5_usb_phy.c revision 269369
1269369Sbr/*- 2269369Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3269369Sbr * All rights reserved. 4269369Sbr * 5269369Sbr * Redistribution and use in source and binary forms, with or without 6269369Sbr * modification, are permitted provided that the following conditions 7269369Sbr * are met: 8269369Sbr * 1. Redistributions of source code must retain the above copyright 9269369Sbr * notice, this list of conditions and the following disclaimer. 10269369Sbr * 2. Redistributions in binary form must reproduce the above copyright 11269369Sbr * notice, this list of conditions and the following disclaimer in the 12269369Sbr * documentation and/or other materials provided with the distribution. 13269369Sbr * 14269369Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15269369Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16269369Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17269369Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18269369Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19269369Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20269369Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21269369Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22269369Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23269369Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24269369Sbr * SUCH DAMAGE. 25269369Sbr */ 26269369Sbr 27269369Sbr/* 28269369Sbr * DWC3 USB 3.0 DRD (dual role device) PHY 29269369Sbr */ 30269369Sbr 31269369Sbr#include <sys/cdefs.h> 32269369Sbr__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/exynos5_usb_phy.c 269369 2014-08-01 06:20:25Z br $"); 33269369Sbr 34269369Sbr#include <sys/param.h> 35269369Sbr#include <sys/systm.h> 36269369Sbr#include <sys/bus.h> 37269369Sbr#include <sys/kernel.h> 38269369Sbr#include <sys/module.h> 39269369Sbr#include <sys/malloc.h> 40269369Sbr#include <sys/rman.h> 41269369Sbr#include <sys/timeet.h> 42269369Sbr#include <sys/timetc.h> 43269369Sbr#include <sys/watchdog.h> 44269369Sbr#include <sys/gpio.h> 45269369Sbr 46269369Sbr#include <dev/fdt/fdt_common.h> 47269369Sbr#include <dev/ofw/openfirm.h> 48269369Sbr#include <dev/ofw/ofw_bus.h> 49269369Sbr#include <dev/ofw/ofw_bus_subr.h> 50269369Sbr 51269369Sbr#include <machine/bus.h> 52269369Sbr#include <machine/fdt.h> 53269369Sbr#include <machine/cpu.h> 54269369Sbr#include <machine/intr.h> 55269369Sbr 56269369Sbr#include <arm/samsung/exynos/exynos5_common.h> 57269369Sbr#include <arm/samsung/exynos/exynos5_pmu.h> 58269369Sbr 59269369Sbr#include "gpio_if.h" 60269369Sbr 61269369Sbr#define USB_DRD_LINKSYSTEM 0x04 62269369Sbr#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) 63269369Sbr#define LINKSYSTEM_FLADJ(x) ((x) << 1) 64269369Sbr#define LINKSYSTEM_XHCI_VERSION_CTRL (1 << 27) 65269369Sbr#define USB_DRD_PHYUTMI 0x08 66269369Sbr#define PHYUTMI_OTGDISABLE (1 << 6) 67269369Sbr#define PHYUTMI_FORCESUSPEND (1 << 1) 68269369Sbr#define PHYUTMI_FORCESLEEP (1 << 0) 69269369Sbr#define USB_DRD_PHYPIPE 0x0c 70269369Sbr#define USB_DRD_PHYCLKRST 0x10 71269369Sbr#define PHYCLKRST_PORTRESET (1 << 1) 72269369Sbr#define PHYCLKRST_COMMONONN (1 << 0) 73269369Sbr#define PHYCLKRST_EN_UTMISUSPEND (1 << 31) 74269369Sbr#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) 75269369Sbr#define PHYCLKRST_SSC_REFCLKSEL(x) ((x) << 23) 76269369Sbr#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) 77269369Sbr#define PHYCLKRST_SSC_RANGE(x) ((x) << 21) 78269369Sbr#define PHYCLKRST_SSC_EN (1 << 20) 79269369Sbr#define PHYCLKRST_REF_SSP_EN (1 << 19) 80269369Sbr#define PHYCLKRST_REF_CLKDIV2 (1 << 18) 81269369Sbr#define PHYCLKRST_MPLL_MLTPR_MASK (0x7f << 11) 82269369Sbr#define PHYCLKRST_MPLL_MLTPR_100MHZ (0x19 << 11) 83269369Sbr#define PHYCLKRST_MPLL_MLTPR_50M (0x32 << 11) 84269369Sbr#define PHYCLKRST_MPLL_MLTPR_24MHZ (0x68 << 11) 85269369Sbr#define PHYCLKRST_MPLL_MLTPR_20MHZ (0x7d << 11) 86269369Sbr#define PHYCLKRST_MPLL_MLTPR_19200KHZ (0x02 << 11) 87269369Sbr#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) 88269369Sbr#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8) 89269369Sbr#define PHYCLKRST_FSEL(x) ((x) << 5) 90269369Sbr#define PHYCLKRST_FSEL_9MHZ6 0x0 91269369Sbr#define PHYCLKRST_FSEL_10MHZ 0x1 92269369Sbr#define PHYCLKRST_FSEL_12MHZ 0x2 93269369Sbr#define PHYCLKRST_FSEL_19MHZ2 0x3 94269369Sbr#define PHYCLKRST_FSEL_20MHZ 0x4 95269369Sbr#define PHYCLKRST_FSEL_24MHZ 0x5 96269369Sbr#define PHYCLKRST_FSEL_50MHZ 0x7 97269369Sbr#define PHYCLKRST_RETENABLEN (1 << 4) 98269369Sbr#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) 99269369Sbr#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) 100269369Sbr#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) 101269369Sbr#define USB_DRD_PHYREG0 0x14 102269369Sbr#define USB_DRD_PHYREG1 0x18 103269369Sbr#define USB_DRD_PHYPARAM0 0x1c 104269369Sbr#define PHYPARAM0_REF_USE_PAD (1 << 31) 105269369Sbr#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) 106269369Sbr#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) 107269369Sbr#define USB_DRD_PHYPARAM1 0x20 108269369Sbr#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) 109269369Sbr#define PHYPARAM1_PCS_TXDEEMPH (0x1c) 110269369Sbr#define USB_DRD_PHYTERM 0x24 111269369Sbr#define USB_DRD_PHYTEST 0x28 112269369Sbr#define PHYTEST_POWERDOWN_SSP (1 << 3) 113269369Sbr#define PHYTEST_POWERDOWN_HSP (1 << 2) 114269369Sbr#define USB_DRD_PHYADP 0x2c 115269369Sbr#define USB_DRD_PHYUTMICLKSEL 0x30 116269369Sbr#define PHYUTMICLKSEL_UTMI_CLKSEL (1 << 2) 117269369Sbr#define USB_DRD_PHYRESUME 0x34 118269369Sbr#define USB_DRD_LINKPORT 0x44 119269369Sbr 120269369Sbrstruct usb_phy_softc { 121269369Sbr struct resource *res[1]; 122269369Sbr bus_space_tag_t bst; 123269369Sbr bus_space_handle_t bsh; 124269369Sbr device_t dev; 125269369Sbr}; 126269369Sbr 127269369Sbrstatic struct resource_spec usb_phy_spec[] = { 128269369Sbr { SYS_RES_MEMORY, 0, RF_ACTIVE }, 129269369Sbr { -1, 0 } 130269369Sbr}; 131269369Sbr 132269369Sbrstatic int 133269369Sbrusb_phy_probe(device_t dev) 134269369Sbr{ 135269369Sbr 136269369Sbr if (!ofw_bus_status_okay(dev)) 137269369Sbr return (ENXIO); 138269369Sbr 139269369Sbr if (!ofw_bus_is_compatible(dev, "samsung,exynos5420-usbdrd-phy")) 140269369Sbr return (ENXIO); 141269369Sbr 142269369Sbr device_set_desc(dev, "Samsung Exynos 5 USB PHY"); 143269369Sbr return (BUS_PROBE_DEFAULT); 144269369Sbr} 145269369Sbr 146269369Sbrstatic int 147269369Sbrvbus_on(struct usb_phy_softc *sc) 148269369Sbr{ 149269369Sbr pcell_t dts_value[3]; 150269369Sbr device_t gpio_dev; 151269369Sbr phandle_t node; 152269369Sbr pcell_t pin; 153269369Sbr int len; 154269369Sbr 155269369Sbr if ((node = ofw_bus_get_node(sc->dev)) == -1) 156269369Sbr return (-1); 157269369Sbr 158269369Sbr /* Power pin */ 159269369Sbr if ((len = OF_getproplen(node, "vbus-supply")) <= 0) 160269369Sbr return (-1); 161269369Sbr OF_getprop(node, "vbus-supply", &dts_value, len); 162269369Sbr pin = fdt32_to_cpu(dts_value[0]); 163269369Sbr 164269369Sbr gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 165269369Sbr if (gpio_dev == NULL) { 166269369Sbr device_printf(sc->dev, "cant find gpio_dev\n"); 167269369Sbr return (1); 168269369Sbr } 169269369Sbr 170269369Sbr GPIO_PIN_SETFLAGS(gpio_dev, pin, GPIO_PIN_OUTPUT); 171269369Sbr GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_HIGH); 172269369Sbr 173269369Sbr return (0); 174269369Sbr} 175269369Sbr 176269369Sbrstatic int 177269369Sbrusb3_phy_init(struct usb_phy_softc *sc) 178269369Sbr{ 179269369Sbr int reg; 180269369Sbr 181269369Sbr /* Reset USB 3.0 PHY */ 182269369Sbr WRITE4(sc, USB_DRD_PHYREG0, 0); 183269369Sbr 184269369Sbr reg = READ4(sc, USB_DRD_PHYPARAM0); 185269369Sbr /* PHY CLK src */ 186269369Sbr reg &= ~(PHYPARAM0_REF_USE_PAD); 187269369Sbr reg &= ~(PHYPARAM0_REF_LOSLEVEL_MASK); 188269369Sbr reg |= (PHYPARAM0_REF_LOSLEVEL); 189269369Sbr WRITE4(sc, USB_DRD_PHYPARAM0, reg); 190269369Sbr WRITE4(sc, USB_DRD_PHYRESUME, 0); 191269369Sbr 192269369Sbr reg = (LINKSYSTEM_XHCI_VERSION_CTRL | 193269369Sbr LINKSYSTEM_FLADJ(0x20)); 194269369Sbr WRITE4(sc, USB_DRD_LINKSYSTEM, reg); 195269369Sbr 196269369Sbr reg = READ4(sc, USB_DRD_PHYPARAM1); 197269369Sbr reg &= ~(PHYPARAM1_PCS_TXDEEMPH_MASK); 198269369Sbr reg |= (PHYPARAM1_PCS_TXDEEMPH); 199269369Sbr WRITE4(sc, USB_DRD_PHYPARAM1, reg); 200269369Sbr 201269369Sbr reg = READ4(sc, USB_DRD_PHYUTMICLKSEL); 202269369Sbr reg |= (PHYUTMICLKSEL_UTMI_CLKSEL); 203269369Sbr WRITE4(sc, USB_DRD_PHYUTMICLKSEL, reg); 204269369Sbr 205269369Sbr reg = READ4(sc, USB_DRD_PHYTEST); 206269369Sbr reg &= ~(PHYTEST_POWERDOWN_HSP); 207269369Sbr reg &= ~(PHYTEST_POWERDOWN_SSP); 208269369Sbr WRITE4(sc, USB_DRD_PHYTEST, reg); 209269369Sbr 210269369Sbr WRITE4(sc, USB_DRD_PHYUTMI, PHYUTMI_OTGDISABLE); 211269369Sbr 212269369Sbr /* Clock */ 213269369Sbr reg = (PHYCLKRST_REFCLKSEL_EXT_REFCLK); 214269369Sbr reg |= (PHYCLKRST_FSEL(PHYCLKRST_FSEL_24MHZ)); 215269369Sbr reg |= (PHYCLKRST_MPLL_MLTPR_24MHZ); 216269369Sbr reg |= (PHYCLKRST_SSC_REFCLKSEL(0x88)); 217269369Sbr reg |= (PHYCLKRST_RETENABLEN | 218269369Sbr PHYCLKRST_REF_SSP_EN | /* Super speed */ 219269369Sbr PHYCLKRST_SSC_EN | /* Spread spectrum */ 220269369Sbr PHYCLKRST_COMMONONN | 221269369Sbr PHYCLKRST_PORTRESET); 222269369Sbr 223269369Sbr WRITE4(sc, USB_DRD_PHYCLKRST, reg); 224269369Sbr DELAY(50000); 225269369Sbr reg &= ~PHYCLKRST_PORTRESET; 226269369Sbr WRITE4(sc, USB_DRD_PHYCLKRST, reg); 227269369Sbr 228269369Sbr return (0); 229269369Sbr} 230269369Sbr 231269369Sbrstatic int 232269369Sbrusb_phy_attach(device_t dev) 233269369Sbr{ 234269369Sbr struct usb_phy_softc *sc; 235269369Sbr 236269369Sbr sc = device_get_softc(dev); 237269369Sbr sc->dev = dev; 238269369Sbr 239269369Sbr if (bus_alloc_resources(dev, usb_phy_spec, sc->res)) { 240269369Sbr device_printf(dev, "could not allocate resources\n"); 241269369Sbr return (ENXIO); 242269369Sbr } 243269369Sbr 244269369Sbr /* Memory interface */ 245269369Sbr sc->bst = rman_get_bustag(sc->res[0]); 246269369Sbr sc->bsh = rman_get_bushandle(sc->res[0]); 247269369Sbr 248269369Sbr vbus_on(sc); 249269369Sbr 250269369Sbr usbdrd_phy_power_on(); 251269369Sbr 252269369Sbr DELAY(100); 253269369Sbr 254269369Sbr usb3_phy_init(sc); 255269369Sbr 256269369Sbr return (0); 257269369Sbr} 258269369Sbr 259269369Sbrstatic device_method_t usb_phy_methods[] = { 260269369Sbr DEVMETHOD(device_probe, usb_phy_probe), 261269369Sbr DEVMETHOD(device_attach, usb_phy_attach), 262269369Sbr { 0, 0 } 263269369Sbr}; 264269369Sbr 265269369Sbrstatic driver_t usb_phy_driver = { 266269369Sbr "usb_phy", 267269369Sbr usb_phy_methods, 268269369Sbr sizeof(struct usb_phy_softc), 269269369Sbr}; 270269369Sbr 271269369Sbrstatic devclass_t usb_phy_devclass; 272269369Sbr 273269369SbrDRIVER_MODULE(usb_phy, simplebus, usb_phy_driver, usb_phy_devclass, 0, 0); 274