exynos5_usb_phy.c revision 269369 
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * DWC3 USB 3.0 DRD (dual role device) PHY
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/exynos5_usb_phy.c 269369 2014-08-01 06:20:25Z br $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/rman.h>
41#include <sys/timeet.h>
42#include <sys/timetc.h>
43#include <sys/watchdog.h>
44#include <sys/gpio.h>
45
46#include <dev/fdt/fdt_common.h>
47#include <dev/ofw/openfirm.h>
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50
51#include <machine/bus.h>
52#include <machine/fdt.h>
53#include <machine/cpu.h>
54#include <machine/intr.h>
55
56#include <arm/samsung/exynos/exynos5_common.h>
57#include <arm/samsung/exynos/exynos5_pmu.h>
58
59#include "gpio_if.h"
60
61#define	USB_DRD_LINKSYSTEM			0x04
62#define	 LINKSYSTEM_FLADJ_MASK			(0x3f << 1)
63#define	 LINKSYSTEM_FLADJ(x)			((x) << 1)
64#define	 LINKSYSTEM_XHCI_VERSION_CTRL		(1 << 27)
65#define	USB_DRD_PHYUTMI				0x08
66#define	 PHYUTMI_OTGDISABLE			(1 << 6)
67#define	 PHYUTMI_FORCESUSPEND			(1 << 1)
68#define	 PHYUTMI_FORCESLEEP			(1 << 0)
69#define	USB_DRD_PHYPIPE				0x0c
70#define	USB_DRD_PHYCLKRST			0x10
71#define	 PHYCLKRST_PORTRESET			(1 << 1)
72#define	 PHYCLKRST_COMMONONN			(1 << 0)
73#define	 PHYCLKRST_EN_UTMISUSPEND		(1 << 31)
74#define	 PHYCLKRST_SSC_REFCLKSEL_MASK		(0xff << 23)
75#define	 PHYCLKRST_SSC_REFCLKSEL(x)		((x) << 23)
76#define	 PHYCLKRST_SSC_RANGE_MASK		(0x03 << 21)
77#define	 PHYCLKRST_SSC_RANGE(x)			((x) << 21)
78#define	 PHYCLKRST_SSC_EN			(1 << 20)
79#define	 PHYCLKRST_REF_SSP_EN			(1 << 19)
80#define	 PHYCLKRST_REF_CLKDIV2			(1 << 18)
81#define	 PHYCLKRST_MPLL_MLTPR_MASK		(0x7f << 11)
82#define	 PHYCLKRST_MPLL_MLTPR_100MHZ		(0x19 << 11)
83#define	 PHYCLKRST_MPLL_MLTPR_50M		(0x32 << 11)
84#define	 PHYCLKRST_MPLL_MLTPR_24MHZ		(0x68 << 11)
85#define	 PHYCLKRST_MPLL_MLTPR_20MHZ		(0x7d << 11)
86#define	 PHYCLKRST_MPLL_MLTPR_19200KHZ		(0x02 << 11)
87#define	 PHYCLKRST_FSEL_UTMI_MASK		(0x7 << 5)
88#define	 PHYCLKRST_FSEL_PIPE_MASK		(0x7 << 8)
89#define	 PHYCLKRST_FSEL(x)			((x) << 5)
90#define	 PHYCLKRST_FSEL_9MHZ6			0x0
91#define	 PHYCLKRST_FSEL_10MHZ			0x1
92#define	 PHYCLKRST_FSEL_12MHZ			0x2
93#define	 PHYCLKRST_FSEL_19MHZ2			0x3
94#define	 PHYCLKRST_FSEL_20MHZ			0x4
95#define	 PHYCLKRST_FSEL_24MHZ			0x5
96#define	 PHYCLKRST_FSEL_50MHZ			0x7
97#define	 PHYCLKRST_RETENABLEN			(1 << 4)
98#define	 PHYCLKRST_REFCLKSEL_MASK		(0x03 << 2)
99#define	 PHYCLKRST_REFCLKSEL_PAD_REFCLK		(0x2 << 2)
100#define	 PHYCLKRST_REFCLKSEL_EXT_REFCLK		(0x3 << 2)
101#define	USB_DRD_PHYREG0				0x14
102#define	USB_DRD_PHYREG1				0x18
103#define	USB_DRD_PHYPARAM0			0x1c
104#define	 PHYPARAM0_REF_USE_PAD			(1 << 31)
105#define	 PHYPARAM0_REF_LOSLEVEL_MASK		(0x1f << 26)
106#define	 PHYPARAM0_REF_LOSLEVEL			(0x9 << 26)
107#define	USB_DRD_PHYPARAM1			0x20
108#define	 PHYPARAM1_PCS_TXDEEMPH_MASK		(0x1f << 0)
109#define	 PHYPARAM1_PCS_TXDEEMPH			(0x1c)
110#define	USB_DRD_PHYTERM				0x24
111#define	USB_DRD_PHYTEST				0x28
112#define	 PHYTEST_POWERDOWN_SSP			(1 << 3)
113#define	 PHYTEST_POWERDOWN_HSP			(1 << 2)
114#define	USB_DRD_PHYADP				0x2c
115#define	USB_DRD_PHYUTMICLKSEL			0x30
116#define	 PHYUTMICLKSEL_UTMI_CLKSEL		(1 << 2)
117#define	USB_DRD_PHYRESUME			0x34
118#define	USB_DRD_LINKPORT			0x44
119
120struct usb_phy_softc {
121	struct resource		*res[1];
122	bus_space_tag_t		bst;
123	bus_space_handle_t	bsh;
124	device_t		dev;
125};
126
127static struct resource_spec usb_phy_spec[] = {
128	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
129	{ -1, 0 }
130};
131
132static int
133usb_phy_probe(device_t dev)
134{
135
136	if (!ofw_bus_status_okay(dev))
137		return (ENXIO);
138
139	if (!ofw_bus_is_compatible(dev, "samsung,exynos5420-usbdrd-phy"))
140		return (ENXIO);
141
142	device_set_desc(dev, "Samsung Exynos 5 USB PHY");
143	return (BUS_PROBE_DEFAULT);
144}
145
146static int
147vbus_on(struct usb_phy_softc *sc)
148{
149	pcell_t dts_value[3];
150	device_t gpio_dev;
151	phandle_t node;
152	pcell_t pin;
153	int len;
154
155	if ((node = ofw_bus_get_node(sc->dev)) == -1)
156		return (-1);
157
158	/* Power pin */
159	if ((len = OF_getproplen(node, "vbus-supply")) <= 0)
160		return (-1);
161	OF_getprop(node, "vbus-supply", &dts_value, len);
162	pin = fdt32_to_cpu(dts_value[0]);
163
164	gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
165	if (gpio_dev == NULL) {
166		device_printf(sc->dev, "cant find gpio_dev\n");
167		return (1);
168	}
169
170	GPIO_PIN_SETFLAGS(gpio_dev, pin, GPIO_PIN_OUTPUT);
171	GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_HIGH);
172
173	return (0);
174}
175
176static int
177usb3_phy_init(struct usb_phy_softc *sc)
178{
179	int reg;
180
181	/* Reset USB 3.0 PHY */
182	WRITE4(sc, USB_DRD_PHYREG0, 0);
183
184	reg = READ4(sc, USB_DRD_PHYPARAM0);
185	/* PHY CLK src */
186	reg &= ~(PHYPARAM0_REF_USE_PAD);
187	reg &= ~(PHYPARAM0_REF_LOSLEVEL_MASK);
188	reg |= (PHYPARAM0_REF_LOSLEVEL);
189	WRITE4(sc, USB_DRD_PHYPARAM0, reg);
190	WRITE4(sc, USB_DRD_PHYRESUME, 0);
191
192	reg = (LINKSYSTEM_XHCI_VERSION_CTRL |
193	    LINKSYSTEM_FLADJ(0x20));
194	WRITE4(sc, USB_DRD_LINKSYSTEM, reg);
195
196	reg = READ4(sc, USB_DRD_PHYPARAM1);
197	reg &= ~(PHYPARAM1_PCS_TXDEEMPH_MASK);
198	reg |= (PHYPARAM1_PCS_TXDEEMPH);
199	WRITE4(sc, USB_DRD_PHYPARAM1, reg);
200
201	reg = READ4(sc, USB_DRD_PHYUTMICLKSEL);
202	reg |= (PHYUTMICLKSEL_UTMI_CLKSEL);
203	WRITE4(sc, USB_DRD_PHYUTMICLKSEL, reg);
204
205	reg = READ4(sc, USB_DRD_PHYTEST);
206	reg &= ~(PHYTEST_POWERDOWN_HSP);
207	reg &= ~(PHYTEST_POWERDOWN_SSP);
208	WRITE4(sc, USB_DRD_PHYTEST, reg);
209
210	WRITE4(sc, USB_DRD_PHYUTMI, PHYUTMI_OTGDISABLE);
211
212	/* Clock */
213	reg = (PHYCLKRST_REFCLKSEL_EXT_REFCLK);
214	reg |= (PHYCLKRST_FSEL(PHYCLKRST_FSEL_24MHZ));
215	reg |= (PHYCLKRST_MPLL_MLTPR_24MHZ);
216	reg |= (PHYCLKRST_SSC_REFCLKSEL(0x88));
217	reg |= (PHYCLKRST_RETENABLEN |
218	    PHYCLKRST_REF_SSP_EN | /* Super speed */
219	    PHYCLKRST_SSC_EN | /* Spread spectrum */
220	    PHYCLKRST_COMMONONN |
221	    PHYCLKRST_PORTRESET);
222
223	WRITE4(sc, USB_DRD_PHYCLKRST, reg);
224	DELAY(50000);
225	reg &= ~PHYCLKRST_PORTRESET;
226	WRITE4(sc, USB_DRD_PHYCLKRST, reg);
227
228	return (0);
229}
230
231static int
232usb_phy_attach(device_t dev)
233{
234	struct usb_phy_softc *sc;
235
236	sc = device_get_softc(dev);
237	sc->dev = dev;
238
239	if (bus_alloc_resources(dev, usb_phy_spec, sc->res)) {
240		device_printf(dev, "could not allocate resources\n");
241		return (ENXIO);
242	}
243
244	/* Memory interface */
245	sc->bst = rman_get_bustag(sc->res[0]);
246	sc->bsh = rman_get_bushandle(sc->res[0]);
247
248	vbus_on(sc);
249
250	usbdrd_phy_power_on();
251
252	DELAY(100);
253
254	usb3_phy_init(sc);
255
256	return (0);
257}
258
259static device_method_t usb_phy_methods[] = {
260	DEVMETHOD(device_probe,		usb_phy_probe),
261	DEVMETHOD(device_attach,	usb_phy_attach),
262	{ 0, 0 }
263};
264
265static driver_t usb_phy_driver = {
266	"usb_phy",
267	usb_phy_methods,
268	sizeof(struct usb_phy_softc),
269};
270
271static devclass_t usb_phy_devclass;
272
273DRIVER_MODULE(usb_phy, simplebus, usb_phy_driver, usb_phy_devclass, 0, 0);
274