cpufunc.h revision 167752
1129198Scognet/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1997 Mark Brinicombe. 5129198Scognet * Copyright (c) 1997 Causality Limited 6129198Scognet * All rights reserved. 7129198Scognet * 8129198Scognet * Redistribution and use in source and binary forms, with or without 9129198Scognet * modification, are permitted provided that the following conditions 10129198Scognet * are met: 11129198Scognet * 1. Redistributions of source code must retain the above copyright 12129198Scognet * notice, this list of conditions and the following disclaimer. 13129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 14129198Scognet * notice, this list of conditions and the following disclaimer in the 15129198Scognet * documentation and/or other materials provided with the distribution. 16129198Scognet * 3. All advertising materials mentioning features or use of this software 17129198Scognet * must display the following acknowledgement: 18129198Scognet * This product includes software developed by Causality Limited. 19129198Scognet * 4. The name of Causality Limited may not be used to endorse or promote 20129198Scognet * products derived from this software without specific prior written 21129198Scognet * permission. 22129198Scognet * 23129198Scognet * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24129198Scognet * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25129198Scognet * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26129198Scognet * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33129198Scognet * SUCH DAMAGE. 34129198Scognet * 35129198Scognet * RiscBSD kernel project 36129198Scognet * 37129198Scognet * cpufunc.h 38129198Scognet * 39129198Scognet * Prototypes for cpu, mmu and tlb related functions. 40129198Scognet * 41129198Scognet * $FreeBSD: head/sys/arm/include/cpufunc.h 167752 2007-03-21 03:28:16Z kevlo $ 42129198Scognet */ 43129198Scognet 44129198Scognet#ifndef _MACHINE_CPUFUNC_H_ 45129198Scognet#define _MACHINE_CPUFUNC_H_ 46129198Scognet 47129198Scognet#ifdef _KERNEL 48129198Scognet 49129198Scognet#include <sys/types.h> 50129198Scognet#include <machine/cpuconf.h> 51132055Scognet#include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52129198Scognet 53132055Scognetstatic __inline void 54132055Scognetbreakpoint(void) 55132055Scognet{ 56137940Scognet __asm(".word 0xe7ffffff"); 57132055Scognet} 58132471Scognet 59129198Scognetstruct cpu_functions { 60129198Scognet 61129198Scognet /* CPU functions */ 62129198Scognet 63129198Scognet u_int (*cf_id) (void); 64129198Scognet void (*cf_cpwait) (void); 65129198Scognet 66129198Scognet /* MMU functions */ 67129198Scognet 68129198Scognet u_int (*cf_control) (u_int bic, u_int eor); 69129198Scognet void (*cf_domains) (u_int domains); 70129198Scognet void (*cf_setttb) (u_int ttb); 71129198Scognet u_int (*cf_faultstatus) (void); 72129198Scognet u_int (*cf_faultaddress) (void); 73129198Scognet 74129198Scognet /* TLB functions */ 75129198Scognet 76129198Scognet void (*cf_tlb_flushID) (void); 77129198Scognet void (*cf_tlb_flushID_SE) (u_int va); 78129198Scognet void (*cf_tlb_flushI) (void); 79129198Scognet void (*cf_tlb_flushI_SE) (u_int va); 80129198Scognet void (*cf_tlb_flushD) (void); 81129198Scognet void (*cf_tlb_flushD_SE) (u_int va); 82129198Scognet 83129198Scognet /* 84129198Scognet * Cache operations: 85129198Scognet * 86129198Scognet * We define the following primitives: 87129198Scognet * 88129198Scognet * icache_sync_all Synchronize I-cache 89129198Scognet * icache_sync_range Synchronize I-cache range 90129198Scognet * 91129198Scognet * dcache_wbinv_all Write-back and Invalidate D-cache 92129198Scognet * dcache_wbinv_range Write-back and Invalidate D-cache range 93129198Scognet * dcache_inv_range Invalidate D-cache range 94129198Scognet * dcache_wb_range Write-back D-cache range 95129198Scognet * 96129198Scognet * idcache_wbinv_all Write-back and Invalidate D-cache, 97129198Scognet * Invalidate I-cache 98129198Scognet * idcache_wbinv_range Write-back and Invalidate D-cache, 99129198Scognet * Invalidate I-cache range 100129198Scognet * 101129198Scognet * Note that the ARM term for "write-back" is "clean". We use 102129198Scognet * the term "write-back" since it's a more common way to describe 103129198Scognet * the operation. 104129198Scognet * 105129198Scognet * There are some rules that must be followed: 106129198Scognet * 107129198Scognet * I-cache Synch (all or range): 108129198Scognet * The goal is to synchronize the instruction stream, 109129198Scognet * so you may beed to write-back dirty D-cache blocks 110129198Scognet * first. If a range is requested, and you can't 111129198Scognet * synchronize just a range, you have to hit the whole 112129198Scognet * thing. 113129198Scognet * 114129198Scognet * D-cache Write-Back and Invalidate range: 115129198Scognet * If you can't WB-Inv a range, you must WB-Inv the 116129198Scognet * entire D-cache. 117129198Scognet * 118129198Scognet * D-cache Invalidate: 119129198Scognet * If you can't Inv the D-cache, you must Write-Back 120129198Scognet * and Invalidate. Code that uses this operation 121129198Scognet * MUST NOT assume that the D-cache will not be written 122129198Scognet * back to memory. 123129198Scognet * 124129198Scognet * D-cache Write-Back: 125129198Scognet * If you can't Write-back without doing an Inv, 126129198Scognet * that's fine. Then treat this as a WB-Inv. 127129198Scognet * Skipping the invalidate is merely an optimization. 128129198Scognet * 129129198Scognet * All operations: 130129198Scognet * Valid virtual addresses must be passed to each 131129198Scognet * cache operation. 132129198Scognet */ 133129198Scognet void (*cf_icache_sync_all) (void); 134129198Scognet void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135129198Scognet 136129198Scognet void (*cf_dcache_wbinv_all) (void); 137129198Scognet void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138129198Scognet void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139129198Scognet void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140129198Scognet 141129198Scognet void (*cf_idcache_wbinv_all) (void); 142129198Scognet void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 143129198Scognet 144129198Scognet /* Other functions */ 145129198Scognet 146129198Scognet void (*cf_flush_prefetchbuf) (void); 147129198Scognet void (*cf_drain_writebuf) (void); 148129198Scognet void (*cf_flush_brnchtgt_C) (void); 149129198Scognet void (*cf_flush_brnchtgt_E) (u_int va); 150129198Scognet 151129198Scognet void (*cf_sleep) (int mode); 152129198Scognet 153129198Scognet /* Soft functions */ 154129198Scognet 155129198Scognet int (*cf_dataabt_fixup) (void *arg); 156129198Scognet int (*cf_prefetchabt_fixup) (void *arg); 157129198Scognet 158129198Scognet void (*cf_context_switch) (void); 159129198Scognet 160129198Scognet void (*cf_setup) (char *string); 161129198Scognet}; 162129198Scognet 163129198Scognetextern struct cpu_functions cpufuncs; 164129198Scognetextern u_int cputype; 165129198Scognet 166129198Scognet#define cpu_id() cpufuncs.cf_id() 167129198Scognet#define cpu_cpwait() cpufuncs.cf_cpwait() 168129198Scognet 169129198Scognet#define cpu_control(c, e) cpufuncs.cf_control(c, e) 170129198Scognet#define cpu_domains(d) cpufuncs.cf_domains(d) 171129198Scognet#define cpu_setttb(t) cpufuncs.cf_setttb(t) 172129198Scognet#define cpu_faultstatus() cpufuncs.cf_faultstatus() 173129198Scognet#define cpu_faultaddress() cpufuncs.cf_faultaddress() 174129198Scognet 175129198Scognet#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 176129198Scognet#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 177129198Scognet#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 178129198Scognet#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 179129198Scognet#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 180129198Scognet#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 181129198Scognet 182129198Scognet#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 183129198Scognet#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 184129198Scognet 185129198Scognet#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 186129198Scognet#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 187129198Scognet#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 188129198Scognet#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 189129198Scognet 190129198Scognet#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 191129198Scognet#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 192129198Scognet 193129198Scognet#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 194129198Scognet#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 195129198Scognet#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 196129198Scognet#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 197129198Scognet 198129198Scognet#define cpu_sleep(m) cpufuncs.cf_sleep(m) 199129198Scognet 200129198Scognet#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 201129198Scognet#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 202129198Scognet#define ABORT_FIXUP_OK 0 /* fixup succeeded */ 203129198Scognet#define ABORT_FIXUP_FAILED 1 /* fixup failed */ 204129198Scognet#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 205129198Scognet 206129198Scognet#define cpu_setup(a) cpufuncs.cf_setup(a) 207129198Scognet 208129198Scognetint set_cpufuncs (void); 209129198Scognet#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 210129198Scognet#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 211129198Scognet 212129198Scognetvoid cpufunc_nullop (void); 213129198Scognetint cpufunc_null_fixup (void *); 214129198Scognetint early_abort_fixup (void *); 215129198Scognetint late_abort_fixup (void *); 216129198Scognetu_int cpufunc_id (void); 217129198Scognetu_int cpufunc_control (u_int clear, u_int bic); 218129198Scognetvoid cpufunc_domains (u_int domains); 219129198Scognetu_int cpufunc_faultstatus (void); 220129198Scognetu_int cpufunc_faultaddress (void); 221129198Scognet 222129198Scognet#ifdef CPU_ARM3 223129198Scognetu_int arm3_control (u_int clear, u_int bic); 224129198Scognetvoid arm3_cache_flush (void); 225129198Scognet#endif /* CPU_ARM3 */ 226129198Scognet 227129198Scognet#if defined(CPU_ARM6) || defined(CPU_ARM7) 228129198Scognetvoid arm67_setttb (u_int ttb); 229129198Scognetvoid arm67_tlb_flush (void); 230129198Scognetvoid arm67_tlb_purge (u_int va); 231129198Scognetvoid arm67_cache_flush (void); 232129198Scognetvoid arm67_context_switch (void); 233129198Scognet#endif /* CPU_ARM6 || CPU_ARM7 */ 234129198Scognet 235129198Scognet#ifdef CPU_ARM6 236129198Scognetvoid arm6_setup (char *string); 237129198Scognet#endif /* CPU_ARM6 */ 238129198Scognet 239129198Scognet#ifdef CPU_ARM7 240129198Scognetvoid arm7_setup (char *string); 241129198Scognet#endif /* CPU_ARM7 */ 242129198Scognet 243129198Scognet#ifdef CPU_ARM7TDMI 244129198Scognetint arm7_dataabt_fixup (void *arg); 245129198Scognetvoid arm7tdmi_setup (char *string); 246129198Scognetvoid arm7tdmi_setttb (u_int ttb); 247129198Scognetvoid arm7tdmi_tlb_flushID (void); 248129198Scognetvoid arm7tdmi_tlb_flushID_SE (u_int va); 249129198Scognetvoid arm7tdmi_cache_flushID (void); 250129198Scognetvoid arm7tdmi_context_switch (void); 251129198Scognet#endif /* CPU_ARM7TDMI */ 252129198Scognet 253129198Scognet#ifdef CPU_ARM8 254129198Scognetvoid arm8_setttb (u_int ttb); 255129198Scognetvoid arm8_tlb_flushID (void); 256129198Scognetvoid arm8_tlb_flushID_SE (u_int va); 257129198Scognetvoid arm8_cache_flushID (void); 258129198Scognetvoid arm8_cache_flushID_E (u_int entry); 259129198Scognetvoid arm8_cache_cleanID (void); 260129198Scognetvoid arm8_cache_cleanID_E (u_int entry); 261129198Scognetvoid arm8_cache_purgeID (void); 262129198Scognetvoid arm8_cache_purgeID_E (u_int entry); 263129198Scognet 264129198Scognetvoid arm8_cache_syncI (void); 265129198Scognetvoid arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 266129198Scognetvoid arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 267129198Scognetvoid arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 268129198Scognetvoid arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 269129198Scognetvoid arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 270129198Scognet 271129198Scognetvoid arm8_context_switch (void); 272129198Scognet 273129198Scognetvoid arm8_setup (char *string); 274129198Scognet 275129198Scognetu_int arm8_clock_config (u_int, u_int); 276129198Scognet#endif 277129198Scognet 278129198Scognet#ifdef CPU_SA110 279129198Scognetvoid sa110_setup (char *string); 280129198Scognetvoid sa110_context_switch (void); 281129198Scognet#endif /* CPU_SA110 */ 282129198Scognet 283129198Scognet#if defined(CPU_SA1100) || defined(CPU_SA1110) 284129198Scognetvoid sa11x0_drain_readbuf (void); 285129198Scognet 286129198Scognetvoid sa11x0_context_switch (void); 287129198Scognetvoid sa11x0_cpu_sleep (int mode); 288129198Scognet 289129198Scognetvoid sa11x0_setup (char *string); 290129198Scognet#endif 291129198Scognet 292129198Scognet#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 293129198Scognetvoid sa1_setttb (u_int ttb); 294129198Scognet 295129198Scognetvoid sa1_tlb_flushID_SE (u_int va); 296129198Scognet 297129198Scognetvoid sa1_cache_flushID (void); 298129198Scognetvoid sa1_cache_flushI (void); 299129198Scognetvoid sa1_cache_flushD (void); 300129198Scognetvoid sa1_cache_flushD_SE (u_int entry); 301129198Scognet 302129198Scognetvoid sa1_cache_cleanID (void); 303129198Scognetvoid sa1_cache_cleanD (void); 304129198Scognetvoid sa1_cache_cleanD_E (u_int entry); 305129198Scognet 306129198Scognetvoid sa1_cache_purgeID (void); 307129198Scognetvoid sa1_cache_purgeID_E (u_int entry); 308129198Scognetvoid sa1_cache_purgeD (void); 309129198Scognetvoid sa1_cache_purgeD_E (u_int entry); 310129198Scognet 311129198Scognetvoid sa1_cache_syncI (void); 312129198Scognetvoid sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 313129198Scognetvoid sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 314129198Scognetvoid sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 315129198Scognetvoid sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 316129198Scognetvoid sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 317129198Scognet 318129198Scognet#endif 319129198Scognet 320129198Scognet#ifdef CPU_ARM9 321129198Scognetvoid arm9_setttb (u_int); 322129198Scognet 323129198Scognetvoid arm9_tlb_flushID_SE (u_int va); 324129198Scognet 325167752Skevlovoid arm9_icache_sync_all (void); 326167752Skevlovoid arm9_icache_sync_range (vm_offset_t, vm_size_t); 327129198Scognet 328167752Skevlovoid arm9_dcache_wbinv_all (void); 329167752Skevlovoid arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 330167752Skevlovoid arm9_dcache_inv_range (vm_offset_t, vm_size_t); 331167752Skevlovoid arm9_dcache_wb_range (vm_offset_t, vm_size_t); 332129198Scognet 333167752Skevlovoid arm9_idcache_wbinv_all (void); 334167752Skevlovoid arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 335129198Scognet 336129198Scognetvoid arm9_context_switch (void); 337129198Scognet 338129198Scognetvoid arm9_setup (char *string); 339146948Scognet 340146948Scognetextern unsigned arm9_dcache_sets_max; 341146948Scognetextern unsigned arm9_dcache_sets_inc; 342146948Scognetextern unsigned arm9_dcache_index_max; 343146948Scognetextern unsigned arm9_dcache_index_inc; 344129198Scognet#endif 345129198Scognet 346129198Scognet#ifdef CPU_ARM10 347129198Scognetvoid arm10_setttb (u_int); 348129198Scognet 349129198Scognetvoid arm10_tlb_flushID_SE (u_int); 350129198Scognetvoid arm10_tlb_flushI_SE (u_int); 351129198Scognet 352129198Scognetvoid arm10_icache_sync_all (void); 353129198Scognetvoid arm10_icache_sync_range (vm_offset_t, vm_size_t); 354129198Scognet 355129198Scognetvoid arm10_dcache_wbinv_all (void); 356129198Scognetvoid arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 357129198Scognetvoid arm10_dcache_inv_range (vm_offset_t, vm_size_t); 358129198Scognetvoid arm10_dcache_wb_range (vm_offset_t, vm_size_t); 359129198Scognet 360129198Scognetvoid arm10_idcache_wbinv_all (void); 361129198Scognetvoid arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 362129198Scognet 363129198Scognetvoid arm10_context_switch (void); 364129198Scognet 365129198Scognetvoid arm10_setup (char *string); 366129198Scognet 367129198Scognetextern unsigned arm10_dcache_sets_max; 368129198Scognetextern unsigned arm10_dcache_sets_inc; 369129198Scognetextern unsigned arm10_dcache_index_max; 370129198Scognetextern unsigned arm10_dcache_index_inc; 371129198Scognet#endif 372129198Scognet 373129198Scognet#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ 374161592Scognet defined(CPU_SA1100) || defined(CPU_SA1110) || \ 375161592Scognet defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 376161592Scognet defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 377164080Scognet defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 378161592Scognet 379129198Scognetvoid armv4_tlb_flushID (void); 380129198Scognetvoid armv4_tlb_flushI (void); 381129198Scognetvoid armv4_tlb_flushD (void); 382129198Scognetvoid armv4_tlb_flushD_SE (u_int va); 383129198Scognet 384129198Scognetvoid armv4_drain_writebuf (void); 385129198Scognet#endif 386129198Scognet 387129198Scognet#if defined(CPU_IXP12X0) 388129198Scognetvoid ixp12x0_drain_readbuf (void); 389129198Scognetvoid ixp12x0_context_switch (void); 390129198Scognetvoid ixp12x0_setup (char *string); 391129198Scognet#endif 392129198Scognet 393161592Scognet#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 394161592Scognet defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 395164080Scognet defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 396129198Scognetvoid xscale_cpwait (void); 397129198Scognet 398129198Scognetvoid xscale_cpu_sleep (int mode); 399129198Scognet 400129198Scognetu_int xscale_control (u_int clear, u_int bic); 401129198Scognet 402129198Scognetvoid xscale_setttb (u_int ttb); 403129198Scognet 404129198Scognetvoid xscale_tlb_flushID_SE (u_int va); 405129198Scognet 406129198Scognetvoid xscale_cache_flushID (void); 407129198Scognetvoid xscale_cache_flushI (void); 408129198Scognetvoid xscale_cache_flushD (void); 409129198Scognetvoid xscale_cache_flushD_SE (u_int entry); 410129198Scognet 411129198Scognetvoid xscale_cache_cleanID (void); 412129198Scognetvoid xscale_cache_cleanD (void); 413129198Scognetvoid xscale_cache_cleanD_E (u_int entry); 414129198Scognet 415129198Scognetvoid xscale_cache_clean_minidata (void); 416129198Scognet 417129198Scognetvoid xscale_cache_purgeID (void); 418129198Scognetvoid xscale_cache_purgeID_E (u_int entry); 419129198Scognetvoid xscale_cache_purgeD (void); 420129198Scognetvoid xscale_cache_purgeD_E (u_int entry); 421129198Scognet 422129198Scognetvoid xscale_cache_syncI (void); 423129198Scognetvoid xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 424129198Scognetvoid xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 425129198Scognetvoid xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 426129198Scognetvoid xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 427129198Scognetvoid xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 428129198Scognetvoid xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 429129198Scognet 430129198Scognetvoid xscale_context_switch (void); 431129198Scognet 432129198Scognetvoid xscale_setup (char *string); 433161592Scognet#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 434161592Scognet CPU_XSCALE_80219 */ 435129198Scognet 436164080Scognet#ifdef CPU_XSCALE_81342 437164080Scognet 438164080Scognetvoid xscalec3_cache_cleanID (void); 439164080Scognetvoid xscalec3_cache_cleanD (void); 440164080Scognet 441164080Scognetvoid xscalec3_cache_purgeID (void); 442164080Scognetvoid xscalec3_cache_purgeID_E (u_int entry); 443164080Scognetvoid xscalec3_cache_purgeD (void); 444164080Scognetvoid xscalec3_cache_purgeD_E (u_int entry); 445164080Scognet 446164080Scognetvoid xscalec3_cache_syncI (void); 447164080Scognetvoid xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 448164080Scognetvoid xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 449164080Scognetvoid xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 450164080Scognetvoid xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 451164080Scognet 452164080Scognet 453164080Scognetvoid xscalec3_setttb (u_int ttb); 454164080Scognetvoid xscalec3_context_switch (void); 455164080Scognet 456164080Scognet#endif /* CPU_XSCALE_81342 */ 457164080Scognet 458129198Scognet#define tlb_flush cpu_tlb_flushID 459129198Scognet#define setttb cpu_setttb 460129198Scognet#define drain_writebuf cpu_drain_writebuf 461129198Scognet 462129198Scognet/* 463129198Scognet * Macros for manipulating CPU interrupts 464129198Scognet */ 465129198Scognetstatic __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 466129198Scognet 467129198Scognetstatic __inline u_int32_t 468129198Scognet__set_cpsr_c(u_int bic, u_int eor) 469129198Scognet{ 470129198Scognet u_int32_t tmp, ret; 471129198Scognet 472129198Scognet __asm __volatile( 473129198Scognet "mrs %0, cpsr\n" /* Get the CPSR */ 474129198Scognet "bic %1, %0, %2\n" /* Clear bits */ 475129198Scognet "eor %1, %1, %3\n" /* XOR bits */ 476129198Scognet "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 477129198Scognet : "=&r" (ret), "=&r" (tmp) 478137226Scognet : "r" (bic), "r" (eor) : "memory"); 479129198Scognet 480129198Scognet return ret; 481129198Scognet} 482129198Scognet 483129198Scognet#define disable_interrupts(mask) \ 484129198Scognet (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 485129198Scognet (mask) & (I32_bit | F32_bit))) 486129198Scognet 487129198Scognet#define enable_interrupts(mask) \ 488159145Scognet (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 489129198Scognet 490129198Scognet#define restore_interrupts(old_cpsr) \ 491129198Scognet (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 492129198Scognet 493137226Scognet#define intr_disable() \ 494137226Scognet disable_interrupts(I32_bit | F32_bit) 495137226Scognet#define intr_restore(s) \ 496137226Scognet restore_interrupts(s) 497129198Scognet/* Functions to manipulate the CPSR. */ 498129198Scognetu_int SetCPSR(u_int bic, u_int eor); 499129198Scognetu_int GetCPSR(void); 500129198Scognet 501129198Scognet/* 502129198Scognet * Functions to manipulate cpu r13 503129198Scognet * (in arm/arm32/setstack.S) 504129198Scognet */ 505129198Scognet 506167752Skevlovoid set_stackptr (u_int mode, u_int address); 507167752Skevlou_int get_stackptr (u_int mode); 508129198Scognet 509129198Scognet/* 510129198Scognet * Miscellany 511129198Scognet */ 512129198Scognet 513167752Skevloint get_pc_str_offset (void); 514129198Scognet 515129198Scognet/* 516129198Scognet * CPU functions from locore.S 517129198Scognet */ 518129198Scognet 519167752Skevlovoid cpu_reset (void) __attribute__((__noreturn__)); 520129198Scognet 521129198Scognet/* 522129198Scognet * Cache info variables. 523129198Scognet */ 524129198Scognet 525129198Scognet/* PRIMARY CACHE VARIABLES */ 526129198Scognetextern int arm_picache_size; 527129198Scognetextern int arm_picache_line_size; 528129198Scognetextern int arm_picache_ways; 529129198Scognet 530129198Scognetextern int arm_pdcache_size; /* and unified */ 531129198Scognetextern int arm_pdcache_line_size; 532129198Scognetextern int arm_pdcache_ways; 533129198Scognet 534129198Scognetextern int arm_pcache_type; 535129198Scognetextern int arm_pcache_unified; 536129198Scognet 537129198Scognetextern int arm_dcache_align; 538129198Scognetextern int arm_dcache_align_mask; 539129198Scognet 540129198Scognet#endif /* _KERNEL */ 541129198Scognet#endif /* _MACHINE_CPUFUNC_H_ */ 542129198Scognet 543129198Scognet/* End of cpufunc.h */ 544