1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD: releng/11.0/sys/arm/include/cpufunc.h 295319 2016-02-05 14:57:41Z mmel $ 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> 50#include <machine/armreg.h> 51#include <machine/cpuconf.h> 52 53static __inline void 54breakpoint(void) 55{ 56 __asm(".word 0xe7ffffff"); 57} 58 59struct cpu_functions { 60 61 /* CPU functions */ 62 63 void (*cf_cpwait) (void); 64 65 /* MMU functions */ 66 67 u_int (*cf_control) (u_int bic, u_int eor); 68 void (*cf_setttb) (u_int ttb); 69 70 /* TLB functions */ 71 72 void (*cf_tlb_flushID) (void); 73 void (*cf_tlb_flushID_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_range Synchronize I-cache range 83 * 84 * dcache_wbinv_all Write-back and Invalidate D-cache 85 * dcache_wbinv_range Write-back and Invalidate D-cache range 86 * dcache_inv_range Invalidate D-cache range 87 * dcache_wb_range Write-back D-cache range 88 * 89 * idcache_wbinv_all Write-back and Invalidate D-cache, 90 * Invalidate I-cache 91 * idcache_wbinv_range Write-back and Invalidate D-cache, 92 * Invalidate I-cache range 93 * 94 * Note that the ARM term for "write-back" is "clean". We use 95 * the term "write-back" since it's a more common way to describe 96 * the operation. 97 * 98 * There are some rules that must be followed: 99 * 100 * ID-cache Invalidate All: 101 * Unlike other functions, this one must never write back. 102 * It is used to intialize the MMU when it is in an unknown 103 * state (such as when it may have lines tagged as valid 104 * that belong to a previous set of mappings). 105 * 106 * I-cache Sync range: 107 * The goal is to synchronize the instruction stream, 108 * so you may beed to write-back dirty D-cache blocks 109 * first. If a range is requested, and you can't 110 * synchronize just a range, you have to hit the whole 111 * thing. 112 * 113 * D-cache Write-Back and Invalidate range: 114 * If you can't WB-Inv a range, you must WB-Inv the 115 * entire D-cache. 116 * 117 * D-cache Invalidate: 118 * If you can't Inv the D-cache, you must Write-Back 119 * and Invalidate. Code that uses this operation 120 * MUST NOT assume that the D-cache will not be written 121 * back to memory. 122 * 123 * D-cache Write-Back: 124 * If you can't Write-back without doing an Inv, 125 * that's fine. Then treat this as a WB-Inv. 126 * Skipping the invalidate is merely an optimization. 127 * 128 * All operations: 129 * Valid virtual addresses must be passed to each 130 * cache operation. 131 */ 132 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 133 134 void (*cf_dcache_wbinv_all) (void); 135 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 136 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 137 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 138 139 void (*cf_idcache_inv_all) (void); 140 void (*cf_idcache_wbinv_all) (void); 141 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 142 void (*cf_l2cache_wbinv_all) (void); 143 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 145 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_drain_writebuf) (void); 147 148 /* Other functions */ 149 150 void (*cf_drain_writebuf) (void); 151 152 void (*cf_sleep) (int mode); 153 154 /* Soft functions */ 155 156 void (*cf_context_switch) (void); 157 158 void (*cf_setup) (void); 159}; 160 161extern struct cpu_functions cpufuncs; 162extern u_int cputype; 163 164#if __ARM_ARCH < 6 165#define cpu_cpwait() cpufuncs.cf_cpwait() 166#endif 167 168#define cpu_control(c, e) cpufuncs.cf_control(c, e) 169#if __ARM_ARCH < 6 170#define cpu_setttb(t) cpufuncs.cf_setttb(t) 171 172#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 173#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 174#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 175#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 176 177#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 178 179#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 180#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 181#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 182#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 183 184#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 185#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 186#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 187#endif 188#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 189#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 190#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 191#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 192#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 193 194#if __ARM_ARCH < 6 195#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 196#endif 197#define cpu_sleep(m) cpufuncs.cf_sleep(m) 198 199#define cpu_setup() cpufuncs.cf_setup() 200 201int set_cpufuncs (void); 202#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204 205void cpufunc_nullop (void); 206u_int cpu_ident (void); 207u_int cpufunc_control (u_int clear, u_int bic); 208void cpu_domains (u_int domains); 209u_int cpu_faultstatus (void); 210u_int cpu_faultaddress (void); 211u_int cpu_get_control (void); 212u_int cpu_pfr (int); 213 214#if defined(CPU_FA526) 215void fa526_setup (void); 216void fa526_setttb (u_int ttb); 217void fa526_context_switch (void); 218void fa526_cpu_sleep (int); 219void fa526_tlb_flushID_SE (u_int); 220 221void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 222void fa526_dcache_wbinv_all (void); 223void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 224void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 225void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 226void fa526_idcache_wbinv_all(void); 227void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 228#endif 229 230 231#if defined(CPU_ARM9) || defined(CPU_ARM9E) 232void arm9_setttb (u_int); 233void arm9_tlb_flushID_SE (u_int va); 234void arm9_context_switch (void); 235#endif 236 237#if defined(CPU_ARM9) 238void arm9_icache_sync_range (vm_offset_t, vm_size_t); 239 240void arm9_dcache_wbinv_all (void); 241void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 242void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 243void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 244 245void arm9_idcache_wbinv_all (void); 246void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 247 248void arm9_setup (void); 249 250extern unsigned arm9_dcache_sets_max; 251extern unsigned arm9_dcache_sets_inc; 252extern unsigned arm9_dcache_index_max; 253extern unsigned arm9_dcache_index_inc; 254#endif 255 256#if defined(CPU_ARM9E) 257void arm10_setup (void); 258 259u_int sheeva_control_ext (u_int, u_int); 260void sheeva_cpu_sleep (int); 261void sheeva_setttb (u_int); 262void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 263void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 264void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 265void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 266 267void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 268void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 269void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 270void sheeva_l2cache_wbinv_all (void); 271#endif 272 273#if defined(CPU_MV_PJ4B) 274void armv6_idcache_wbinv_all (void); 275#endif 276#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 277void armv7_setttb (u_int); 278void armv7_tlb_flushID (void); 279void armv7_tlb_flushID_SE (u_int); 280void armv7_icache_sync_range (vm_offset_t, vm_size_t); 281void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 282void armv7_idcache_inv_all (void); 283void armv7_dcache_wbinv_all (void); 284void armv7_idcache_wbinv_all (void); 285void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 286void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 287void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 288void armv7_cpu_sleep (int); 289void armv7_setup (void); 290void armv7_context_switch (void); 291void armv7_drain_writebuf (void); 292void armv7_sev (void); 293u_int armv7_auxctrl (u_int, u_int); 294 295void armadaxp_idcache_wbinv_all (void); 296 297void cortexa_setup (void); 298#endif 299#if defined(CPU_MV_PJ4B) 300void pj4b_config (void); 301void pj4bv7_setup (void); 302#endif 303 304#if defined(CPU_ARM1176) 305void arm11_tlb_flushID (void); 306void arm11_tlb_flushID_SE (u_int); 307void arm11_tlb_flushD (void); 308void arm11_tlb_flushD_SE (u_int va); 309 310void arm11_context_switch (void); 311 312void arm11_drain_writebuf (void); 313 314void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 315void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 316void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 317 318void armv6_idcache_inv_all (void); 319 320void arm11x6_setttb (u_int); 321void arm11x6_idcache_wbinv_all (void); 322void arm11x6_dcache_wbinv_all (void); 323void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 324void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 325void arm11x6_setup (void); 326void arm11x6_sleep (int); /* no ref. for errata */ 327#endif 328 329#if defined(CPU_ARM9E) 330void armv5_ec_setttb(u_int); 331 332void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 333 334void armv5_ec_dcache_wbinv_all(void); 335void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 336void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 337void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 338 339void armv5_ec_idcache_wbinv_all(void); 340void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 341#endif 342 343#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 344 defined(CPU_FA526) || \ 345 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 346 defined(CPU_XSCALE_81342) 347 348void armv4_tlb_flushID (void); 349void armv4_tlb_flushD (void); 350void armv4_tlb_flushD_SE (u_int va); 351 352void armv4_drain_writebuf (void); 353void armv4_idcache_inv_all (void); 354#endif 355 356#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 357 defined(CPU_XSCALE_81342) 358void xscale_cpwait (void); 359 360void xscale_cpu_sleep (int mode); 361 362u_int xscale_control (u_int clear, u_int bic); 363 364void xscale_setttb (u_int ttb); 365 366void xscale_tlb_flushID_SE (u_int va); 367 368void xscale_cache_flushID (void); 369void xscale_cache_flushI (void); 370void xscale_cache_flushD (void); 371void xscale_cache_flushD_SE (u_int entry); 372 373void xscale_cache_cleanID (void); 374void xscale_cache_cleanD (void); 375void xscale_cache_cleanD_E (u_int entry); 376 377void xscale_cache_clean_minidata (void); 378 379void xscale_cache_purgeID (void); 380void xscale_cache_purgeID_E (u_int entry); 381void xscale_cache_purgeD (void); 382void xscale_cache_purgeD_E (u_int entry); 383 384void xscale_cache_syncI (void); 385void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 386void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 387void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 388void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 389void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 390void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 391 392void xscale_context_switch (void); 393 394void xscale_setup (void); 395#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 396 397#ifdef CPU_XSCALE_81342 398 399void xscalec3_l2cache_purge (void); 400void xscalec3_cache_purgeID (void); 401void xscalec3_cache_purgeD (void); 402void xscalec3_cache_cleanID (void); 403void xscalec3_cache_cleanD (void); 404void xscalec3_cache_syncI (void); 405 406void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 407void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 408void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 409void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 410void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 411 412void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 413void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 414void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 415 416 417void xscalec3_setttb (u_int ttb); 418void xscalec3_context_switch (void); 419 420#endif /* CPU_XSCALE_81342 */ 421 422/* 423 * Macros for manipulating CPU interrupts 424 */ 425#if __ARM_ARCH < 6 426#define __ARM_INTR_BITS (PSR_I | PSR_F) 427#else 428#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 429#endif 430 431static __inline uint32_t 432__set_cpsr(uint32_t bic, uint32_t eor) 433{ 434 uint32_t tmp, ret; 435 436 __asm __volatile( 437 "mrs %0, cpsr\n" /* Get the CPSR */ 438 "bic %1, %0, %2\n" /* Clear bits */ 439 "eor %1, %1, %3\n" /* XOR bits */ 440 "msr cpsr_xc, %1\n" /* Set the CPSR */ 441 : "=&r" (ret), "=&r" (tmp) 442 : "r" (bic), "r" (eor) : "memory"); 443 444 return ret; 445} 446 447static __inline uint32_t 448disable_interrupts(uint32_t mask) 449{ 450 451 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 452} 453 454static __inline uint32_t 455enable_interrupts(uint32_t mask) 456{ 457 458 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 459} 460 461static __inline uint32_t 462restore_interrupts(uint32_t old_cpsr) 463{ 464 465 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 466} 467 468static __inline register_t 469intr_disable(void) 470{ 471 472 return (disable_interrupts(PSR_I | PSR_F)); 473} 474 475static __inline void 476intr_restore(register_t s) 477{ 478 479 restore_interrupts(s); 480} 481#undef __ARM_INTR_BITS 482 483/* 484 * Functions to manipulate cpu r13 485 * (in arm/arm32/setstack.S) 486 */ 487 488void set_stackptr (u_int mode, u_int address); 489u_int get_stackptr (u_int mode); 490 491/* 492 * Miscellany 493 */ 494 495int get_pc_str_offset (void); 496 497/* 498 * CPU functions from locore.S 499 */ 500 501void cpu_reset (void) __attribute__((__noreturn__)); 502 503/* 504 * Cache info variables. 505 */ 506 507/* PRIMARY CACHE VARIABLES */ 508extern int arm_picache_size; 509extern int arm_picache_line_size; 510extern int arm_picache_ways; 511 512extern int arm_pdcache_size; /* and unified */ 513extern int arm_pdcache_line_size; 514extern int arm_pdcache_ways; 515 516extern int arm_pcache_type; 517extern int arm_pcache_unified; 518 519extern int arm_dcache_align; 520extern int arm_dcache_align_mask; 521 522extern u_int arm_cache_level; 523extern u_int arm_cache_loc; 524extern u_int arm_cache_type[14]; 525 526#endif /* _KERNEL */ 527#endif /* _MACHINE_CPUFUNC_H_ */ 528 529/* End of cpufunc.h */ 530