1129198Scognet/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1997 Mark Brinicombe. 5129198Scognet * Copyright (c) 1997 Causality Limited 6129198Scognet * All rights reserved. 7129198Scognet * 8129198Scognet * Redistribution and use in source and binary forms, with or without 9129198Scognet * modification, are permitted provided that the following conditions 10129198Scognet * are met: 11129198Scognet * 1. Redistributions of source code must retain the above copyright 12129198Scognet * notice, this list of conditions and the following disclaimer. 13129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 14129198Scognet * notice, this list of conditions and the following disclaimer in the 15129198Scognet * documentation and/or other materials provided with the distribution. 16129198Scognet * 3. All advertising materials mentioning features or use of this software 17129198Scognet * must display the following acknowledgement: 18129198Scognet * This product includes software developed by Causality Limited. 19129198Scognet * 4. The name of Causality Limited may not be used to endorse or promote 20129198Scognet * products derived from this software without specific prior written 21129198Scognet * permission. 22129198Scognet * 23129198Scognet * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24129198Scognet * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25129198Scognet * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26129198Scognet * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33129198Scognet * SUCH DAMAGE. 34129198Scognet * 35129198Scognet * RiscBSD kernel project 36129198Scognet * 37129198Scognet * cpufunc.h 38129198Scognet * 39129198Scognet * Prototypes for cpu, mmu and tlb related functions. 40129198Scognet * 41129198Scognet * $FreeBSD: releng/11.0/sys/arm/include/cpufunc.h 295319 2016-02-05 14:57:41Z mmel $ 42129198Scognet */ 43129198Scognet 44129198Scognet#ifndef _MACHINE_CPUFUNC_H_ 45129198Scognet#define _MACHINE_CPUFUNC_H_ 46129198Scognet 47129198Scognet#ifdef _KERNEL 48129198Scognet 49129198Scognet#include <sys/types.h> 50290661Smmel#include <machine/armreg.h> 51129198Scognet#include <machine/cpuconf.h> 52129198Scognet 53132055Scognetstatic __inline void 54132055Scognetbreakpoint(void) 55132055Scognet{ 56137940Scognet __asm(".word 0xe7ffffff"); 57132055Scognet} 58132471Scognet 59129198Scognetstruct cpu_functions { 60129198Scognet 61129198Scognet /* CPU functions */ 62290648Smmel 63129198Scognet void (*cf_cpwait) (void); 64129198Scognet 65129198Scognet /* MMU functions */ 66129198Scognet 67129198Scognet u_int (*cf_control) (u_int bic, u_int eor); 68129198Scognet void (*cf_setttb) (u_int ttb); 69129198Scognet 70129198Scognet /* TLB functions */ 71129198Scognet 72290648Smmel void (*cf_tlb_flushID) (void); 73290648Smmel void (*cf_tlb_flushID_SE) (u_int va); 74129198Scognet void (*cf_tlb_flushD) (void); 75290648Smmel void (*cf_tlb_flushD_SE) (u_int va); 76129198Scognet 77129198Scognet /* 78129198Scognet * Cache operations: 79129198Scognet * 80129198Scognet * We define the following primitives: 81129198Scognet * 82129198Scognet * icache_sync_range Synchronize I-cache range 83129198Scognet * 84129198Scognet * dcache_wbinv_all Write-back and Invalidate D-cache 85129198Scognet * dcache_wbinv_range Write-back and Invalidate D-cache range 86129198Scognet * dcache_inv_range Invalidate D-cache range 87129198Scognet * dcache_wb_range Write-back D-cache range 88129198Scognet * 89129198Scognet * idcache_wbinv_all Write-back and Invalidate D-cache, 90129198Scognet * Invalidate I-cache 91129198Scognet * idcache_wbinv_range Write-back and Invalidate D-cache, 92129198Scognet * Invalidate I-cache range 93129198Scognet * 94129198Scognet * Note that the ARM term for "write-back" is "clean". We use 95129198Scognet * the term "write-back" since it's a more common way to describe 96129198Scognet * the operation. 97129198Scognet * 98129198Scognet * There are some rules that must be followed: 99129198Scognet * 100262420Sian * ID-cache Invalidate All: 101262420Sian * Unlike other functions, this one must never write back. 102262420Sian * It is used to intialize the MMU when it is in an unknown 103262420Sian * state (such as when it may have lines tagged as valid 104262420Sian * that belong to a previous set of mappings). 105290648Smmel * 106295207Smmel * I-cache Sync range: 107129198Scognet * The goal is to synchronize the instruction stream, 108129198Scognet * so you may beed to write-back dirty D-cache blocks 109129198Scognet * first. If a range is requested, and you can't 110129198Scognet * synchronize just a range, you have to hit the whole 111129198Scognet * thing. 112129198Scognet * 113129198Scognet * D-cache Write-Back and Invalidate range: 114129198Scognet * If you can't WB-Inv a range, you must WB-Inv the 115129198Scognet * entire D-cache. 116129198Scognet * 117129198Scognet * D-cache Invalidate: 118129198Scognet * If you can't Inv the D-cache, you must Write-Back 119129198Scognet * and Invalidate. Code that uses this operation 120129198Scognet * MUST NOT assume that the D-cache will not be written 121129198Scognet * back to memory. 122129198Scognet * 123129198Scognet * D-cache Write-Back: 124129198Scognet * If you can't Write-back without doing an Inv, 125129198Scognet * that's fine. Then treat this as a WB-Inv. 126129198Scognet * Skipping the invalidate is merely an optimization. 127129198Scognet * 128129198Scognet * All operations: 129129198Scognet * Valid virtual addresses must be passed to each 130129198Scognet * cache operation. 131129198Scognet */ 132129198Scognet void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 133129198Scognet 134129198Scognet void (*cf_dcache_wbinv_all) (void); 135129198Scognet void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 136129198Scognet void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 137129198Scognet void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 138129198Scognet 139262420Sian void (*cf_idcache_inv_all) (void); 140129198Scognet void (*cf_idcache_wbinv_all) (void); 141129198Scognet void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 142171618Scognet void (*cf_l2cache_wbinv_all) (void); 143171618Scognet void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 144171618Scognet void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 145171618Scognet void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 146265870Sian void (*cf_l2cache_drain_writebuf) (void); 147129198Scognet 148129198Scognet /* Other functions */ 149129198Scognet 150129198Scognet void (*cf_drain_writebuf) (void); 151129198Scognet 152129198Scognet void (*cf_sleep) (int mode); 153129198Scognet 154129198Scognet /* Soft functions */ 155129198Scognet 156129198Scognet void (*cf_context_switch) (void); 157129198Scognet 158280823Sandrew void (*cf_setup) (void); 159129198Scognet}; 160129198Scognet 161129198Scognetextern struct cpu_functions cpufuncs; 162129198Scognetextern u_int cputype; 163129198Scognet 164295319Smmel#if __ARM_ARCH < 6 165129198Scognet#define cpu_cpwait() cpufuncs.cf_cpwait() 166295319Smmel#endif 167129198Scognet 168129198Scognet#define cpu_control(c, e) cpufuncs.cf_control(c, e) 169295319Smmel#if __ARM_ARCH < 6 170129198Scognet#define cpu_setttb(t) cpufuncs.cf_setttb(t) 171129198Scognet 172129198Scognet#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 173129198Scognet#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 174129198Scognet#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 175129198Scognet#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 176129198Scognet 177129198Scognet#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 178129198Scognet 179129198Scognet#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 180129198Scognet#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 181129198Scognet#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 182129198Scognet#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 183129198Scognet 184262420Sian#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 185129198Scognet#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 186129198Scognet#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 187295319Smmel#endif 188171618Scognet#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 189171618Scognet#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 190171618Scognet#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 191171618Scognet#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 192265870Sian#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 193129198Scognet 194295319Smmel#if __ARM_ARCH < 6 195129198Scognet#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 196295319Smmel#endif 197129198Scognet#define cpu_sleep(m) cpufuncs.cf_sleep(m) 198129198Scognet 199280823Sandrew#define cpu_setup() cpufuncs.cf_setup() 200129198Scognet 201129198Scognetint set_cpufuncs (void); 202129198Scognet#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203129198Scognet#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204129198Scognet 205129198Scognetvoid cpufunc_nullop (void); 206295096Smmelu_int cpu_ident (void); 207129198Scognetu_int cpufunc_control (u_int clear, u_int bic); 208295096Smmelvoid cpu_domains (u_int domains); 209295096Smmelu_int cpu_faultstatus (void); 210295096Smmelu_int cpu_faultaddress (void); 211295252Smmelu_int cpu_get_control (void); 212239268Sgonzou_int cpu_pfr (int); 213129198Scognet 214280842Sandrew#if defined(CPU_FA526) 215280823Sandrewvoid fa526_setup (void); 216201468Srpaulovoid fa526_setttb (u_int ttb); 217201468Srpaulovoid fa526_context_switch (void); 218201468Srpaulovoid fa526_cpu_sleep (int); 219201468Srpaulovoid fa526_tlb_flushID_SE (u_int); 220201468Srpaulo 221201468Srpaulovoid fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 222201468Srpaulovoid fa526_dcache_wbinv_all (void); 223201468Srpaulovoid fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 224201468Srpaulovoid fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 225201468Srpaulovoid fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 226201468Srpaulovoid fa526_idcache_wbinv_all(void); 227201468Srpaulovoid fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 228201468Srpaulo#endif 229201468Srpaulo 230201468Srpaulo 231295149Smmel#if defined(CPU_ARM9) || defined(CPU_ARM9E) 232129198Scognetvoid arm9_setttb (u_int); 233129198Scognetvoid arm9_tlb_flushID_SE (u_int va); 234295149Smmelvoid arm9_context_switch (void); 235295149Smmel#endif 236129198Scognet 237295207Smmel#if defined(CPU_ARM9) 238167752Skevlovoid arm9_icache_sync_range (vm_offset_t, vm_size_t); 239129198Scognet 240167752Skevlovoid arm9_dcache_wbinv_all (void); 241167752Skevlovoid arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 242167752Skevlovoid arm9_dcache_inv_range (vm_offset_t, vm_size_t); 243167752Skevlovoid arm9_dcache_wb_range (vm_offset_t, vm_size_t); 244129198Scognet 245167752Skevlovoid arm9_idcache_wbinv_all (void); 246167752Skevlovoid arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 247129198Scognet 248280823Sandrewvoid arm9_setup (void); 249146948Scognet 250146948Scognetextern unsigned arm9_dcache_sets_max; 251146948Scognetextern unsigned arm9_dcache_sets_inc; 252146948Scognetextern unsigned arm9_dcache_index_max; 253146948Scognetextern unsigned arm9_dcache_index_inc; 254129198Scognet#endif 255129198Scognet 256280809Sandrew#if defined(CPU_ARM9E) 257280823Sandrewvoid arm10_setup (void); 258129198Scognet 259186933Sraju_int sheeva_control_ext (u_int, u_int); 260212825Smavvoid sheeva_cpu_sleep (int); 261186933Srajvoid sheeva_setttb (u_int); 262186933Srajvoid sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 263186933Srajvoid sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 264186933Srajvoid sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 265186933Srajvoid sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 266183835Sraj 267186933Srajvoid sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 268186933Srajvoid sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 269186933Srajvoid sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 270186933Srajvoid sheeva_l2cache_wbinv_all (void); 271129198Scognet#endif 272129198Scognet 273280813Sandrew#if defined(CPU_MV_PJ4B) 274239268Sgonzovoid armv6_idcache_wbinv_all (void); 275280813Sandrew#endif 276280813Sandrew#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 277239268Sgonzovoid armv7_setttb (u_int); 278239268Sgonzovoid armv7_tlb_flushID (void); 279239268Sgonzovoid armv7_tlb_flushID_SE (u_int); 280239268Sgonzovoid armv7_icache_sync_range (vm_offset_t, vm_size_t); 281239268Sgonzovoid armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 282262420Sianvoid armv7_idcache_inv_all (void); 283239268Sgonzovoid armv7_dcache_wbinv_all (void); 284239268Sgonzovoid armv7_idcache_wbinv_all (void); 285239268Sgonzovoid armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 286239268Sgonzovoid armv7_dcache_inv_range (vm_offset_t, vm_size_t); 287239268Sgonzovoid armv7_dcache_wb_range (vm_offset_t, vm_size_t); 288239268Sgonzovoid armv7_cpu_sleep (int); 289280823Sandrewvoid armv7_setup (void); 290239268Sgonzovoid armv7_context_switch (void); 291239268Sgonzovoid armv7_drain_writebuf (void); 292239268Sgonzovoid armv7_sev (void); 293239268Sgonzou_int armv7_auxctrl (u_int, u_int); 294239268Sgonzo 295239268Sgonzovoid armadaxp_idcache_wbinv_all (void); 296239268Sgonzo 297280823Sandrewvoid cortexa_setup (void); 298172738Simp#endif 299280832Sandrew#if defined(CPU_MV_PJ4B) 300280832Sandrewvoid pj4b_config (void); 301280832Sandrewvoid pj4bv7_setup (void); 302280832Sandrew#endif 303172738Simp 304280824Sandrew#if defined(CPU_ARM1176) 305280813Sandrewvoid arm11_tlb_flushID (void); 306280813Sandrewvoid arm11_tlb_flushID_SE (u_int); 307280813Sandrewvoid arm11_tlb_flushD (void); 308280813Sandrewvoid arm11_tlb_flushD_SE (u_int va); 309280813Sandrew 310280813Sandrewvoid arm11_context_switch (void); 311280813Sandrew 312280813Sandrewvoid arm11_drain_writebuf (void); 313280813Sandrew 314280813Sandrewvoid armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 315280813Sandrewvoid armv6_dcache_inv_range (vm_offset_t, vm_size_t); 316280813Sandrewvoid armv6_dcache_wb_range (vm_offset_t, vm_size_t); 317280813Sandrew 318280813Sandrewvoid armv6_idcache_inv_all (void); 319280813Sandrew 320244480Sgonzovoid arm11x6_setttb (u_int); 321244480Sgonzovoid arm11x6_idcache_wbinv_all (void); 322244480Sgonzovoid arm11x6_dcache_wbinv_all (void); 323244480Sgonzovoid arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 324244480Sgonzovoid arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 325280823Sandrewvoid arm11x6_setup (void); 326244480Sgonzovoid arm11x6_sleep (int); /* no ref. for errata */ 327244480Sgonzo#endif 328244480Sgonzo 329280809Sandrew#if defined(CPU_ARM9E) 330172738Simpvoid armv5_ec_setttb(u_int); 331172738Simp 332172738Simpvoid armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 333172738Simp 334172738Simpvoid armv5_ec_dcache_wbinv_all(void); 335172738Simpvoid armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 336172738Simpvoid armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 337172738Simpvoid armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 338172738Simp 339172738Simpvoid armv5_ec_idcache_wbinv_all(void); 340172738Simpvoid armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 341172738Simp#endif 342172738Simp 343280809Sandrew#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 344280842Sandrew defined(CPU_FA526) || \ 345207611Skevlo defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 346295200Smmel defined(CPU_XSCALE_81342) 347236992Simp 348129198Scognetvoid armv4_tlb_flushID (void); 349129198Scognetvoid armv4_tlb_flushD (void); 350129198Scognetvoid armv4_tlb_flushD_SE (u_int va); 351129198Scognet 352129198Scognetvoid armv4_drain_writebuf (void); 353262420Sianvoid armv4_idcache_inv_all (void); 354129198Scognet#endif 355129198Scognet 356295200Smmel#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 357295200Smmel defined(CPU_XSCALE_81342) 358129198Scognetvoid xscale_cpwait (void); 359129198Scognet 360129198Scognetvoid xscale_cpu_sleep (int mode); 361129198Scognet 362129198Scognetu_int xscale_control (u_int clear, u_int bic); 363129198Scognet 364129198Scognetvoid xscale_setttb (u_int ttb); 365129198Scognet 366129198Scognetvoid xscale_tlb_flushID_SE (u_int va); 367129198Scognet 368129198Scognetvoid xscale_cache_flushID (void); 369129198Scognetvoid xscale_cache_flushI (void); 370129198Scognetvoid xscale_cache_flushD (void); 371129198Scognetvoid xscale_cache_flushD_SE (u_int entry); 372129198Scognet 373129198Scognetvoid xscale_cache_cleanID (void); 374129198Scognetvoid xscale_cache_cleanD (void); 375129198Scognetvoid xscale_cache_cleanD_E (u_int entry); 376129198Scognet 377129198Scognetvoid xscale_cache_clean_minidata (void); 378129198Scognet 379129198Scognetvoid xscale_cache_purgeID (void); 380129198Scognetvoid xscale_cache_purgeID_E (u_int entry); 381129198Scognetvoid xscale_cache_purgeD (void); 382129198Scognetvoid xscale_cache_purgeD_E (u_int entry); 383129198Scognet 384129198Scognetvoid xscale_cache_syncI (void); 385129198Scognetvoid xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 386129198Scognetvoid xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 387129198Scognetvoid xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 388129198Scognetvoid xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 389129198Scognetvoid xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 390129198Scognetvoid xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 391129198Scognet 392129198Scognetvoid xscale_context_switch (void); 393129198Scognet 394280823Sandrewvoid xscale_setup (void); 395295200Smmel#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 396129198Scognet 397164080Scognet#ifdef CPU_XSCALE_81342 398164080Scognet 399171618Scognetvoid xscalec3_l2cache_purge (void); 400171618Scognetvoid xscalec3_cache_purgeID (void); 401171618Scognetvoid xscalec3_cache_purgeD (void); 402164080Scognetvoid xscalec3_cache_cleanID (void); 403164080Scognetvoid xscalec3_cache_cleanD (void); 404171618Scognetvoid xscalec3_cache_syncI (void); 405164080Scognet 406171618Scognetvoid xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 407171618Scognetvoid xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 408171618Scognetvoid xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 409164080Scognetvoid xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 410171618Scognetvoid xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 411164080Scognet 412171618Scognetvoid xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 413171618Scognetvoid xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 414171618Scognetvoid xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 415164080Scognet 416171618Scognet 417164080Scognetvoid xscalec3_setttb (u_int ttb); 418164080Scognetvoid xscalec3_context_switch (void); 419164080Scognet 420164080Scognet#endif /* CPU_XSCALE_81342 */ 421164080Scognet 422129198Scognet/* 423129198Scognet * Macros for manipulating CPU interrupts 424129198Scognet */ 425290661Smmel#if __ARM_ARCH < 6 426290661Smmel#define __ARM_INTR_BITS (PSR_I | PSR_F) 427290661Smmel#else 428290661Smmel#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 429290661Smmel#endif 430129198Scognet 431290661Smmelstatic __inline uint32_t 432290661Smmel__set_cpsr(uint32_t bic, uint32_t eor) 433129198Scognet{ 434290661Smmel uint32_t tmp, ret; 435129198Scognet 436129198Scognet __asm __volatile( 437290661Smmel "mrs %0, cpsr\n" /* Get the CPSR */ 438290661Smmel "bic %1, %0, %2\n" /* Clear bits */ 439290661Smmel "eor %1, %1, %3\n" /* XOR bits */ 440290661Smmel "msr cpsr_xc, %1\n" /* Set the CPSR */ 441129198Scognet : "=&r" (ret), "=&r" (tmp) 442137226Scognet : "r" (bic), "r" (eor) : "memory"); 443129198Scognet 444129198Scognet return ret; 445129198Scognet} 446129198Scognet 447290661Smmelstatic __inline uint32_t 448290661Smmeldisable_interrupts(uint32_t mask) 449290661Smmel{ 450243576Smarcel 451290661Smmel return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 452290661Smmel} 453129198Scognet 454290661Smmelstatic __inline uint32_t 455290661Smmelenable_interrupts(uint32_t mask) 456290661Smmel{ 457129198Scognet 458290661Smmel return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 459290661Smmel} 460129198Scognet 461290661Smmelstatic __inline uint32_t 462290661Smmelrestore_interrupts(uint32_t old_cpsr) 463290661Smmel{ 464290661Smmel 465290661Smmel return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 466290661Smmel} 467290661Smmel 468243576Smarcelstatic __inline register_t 469243576Smarcelintr_disable(void) 470243576Smarcel{ 471243576Smarcel 472290661Smmel return (disable_interrupts(PSR_I | PSR_F)); 473243576Smarcel} 474243576Smarcel 475243576Smarcelstatic __inline void 476243576Smarcelintr_restore(register_t s) 477243576Smarcel{ 478243576Smarcel 479243576Smarcel restore_interrupts(s); 480243576Smarcel} 481290661Smmel#undef __ARM_INTR_BITS 482243576Smarcel 483129198Scognet/* 484129198Scognet * Functions to manipulate cpu r13 485129198Scognet * (in arm/arm32/setstack.S) 486129198Scognet */ 487129198Scognet 488167752Skevlovoid set_stackptr (u_int mode, u_int address); 489167752Skevlou_int get_stackptr (u_int mode); 490129198Scognet 491129198Scognet/* 492129198Scognet * Miscellany 493129198Scognet */ 494129198Scognet 495167752Skevloint get_pc_str_offset (void); 496129198Scognet 497129198Scognet/* 498129198Scognet * CPU functions from locore.S 499129198Scognet */ 500129198Scognet 501167752Skevlovoid cpu_reset (void) __attribute__((__noreturn__)); 502129198Scognet 503129198Scognet/* 504129198Scognet * Cache info variables. 505129198Scognet */ 506129198Scognet 507129198Scognet/* PRIMARY CACHE VARIABLES */ 508129198Scognetextern int arm_picache_size; 509129198Scognetextern int arm_picache_line_size; 510129198Scognetextern int arm_picache_ways; 511129198Scognet 512129198Scognetextern int arm_pdcache_size; /* and unified */ 513129198Scognetextern int arm_pdcache_line_size; 514236992Simpextern int arm_pdcache_ways; 515129198Scognet 516129198Scognetextern int arm_pcache_type; 517129198Scognetextern int arm_pcache_unified; 518129198Scognet 519129198Scognetextern int arm_dcache_align; 520129198Scognetextern int arm_dcache_align_mask; 521129198Scognet 522239268Sgonzoextern u_int arm_cache_level; 523239268Sgonzoextern u_int arm_cache_loc; 524239268Sgonzoextern u_int arm_cache_type[14]; 525239268Sgonzo 526129198Scognet#endif /* _KERNEL */ 527129198Scognet#endif /* _MACHINE_CPUFUNC_H_ */ 528129198Scognet 529129198Scognet/* End of cpufunc.h */ 530