1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* $FreeBSD: releng/11.0/sys/arm/at91/at91_pioreg.h 258820 2013-12-02 02:33:03Z ian $ */ 27 28#ifndef ARM_AT91_AT91_PIOREG_H 29#define ARM_AT91_AT91_PIOREG_H 30 31#ifndef ATMEL_ENV 32/* Registers */ 33#define PIO_PER 0x00 /* PIO Enable Register */ 34#define PIO_PDR 0x04 /* PIO Disable Register */ 35#define PIO_PSR 0x08 /* PIO Status Register */ 36 /* 0x0c reserved */ 37#define PIO_OER 0x10 /* PIO Output Enable Register */ 38#define PIO_ODR 0x14 /* PIO Output Disable Register */ 39#define PIO_OSR 0x18 /* PIO Output Status Register */ 40 /* 0x1c reserved */ 41#define PIO_IFER 0x20 /* PIO Glitch Input Enable Register */ 42#define PIO_IFDR 0x24 /* PIO Glitch Input Disable Register */ 43#define PIO_IFSR 0x28 /* PIO Glitch Input Status Register */ 44 /* 0x2c reserved */ 45#define PIO_SODR 0x30 /* PIO Set Output Data Register */ 46#define PIO_CODR 0x34 /* PIO Clear Output Data Register */ 47#define PIO_ODSR 0x38 /* PIO Output Data Status Register */ 48#define PIO_PDSR 0x3c /* PIO Pin Data Status Register */ 49#define PIO_IER 0x40 /* PIO Interrupt Enable Register */ 50#define PIO_IDR 0x44 /* PIO Interrupt Disable Register */ 51#define PIO_IMR 0x48 /* PIO Interrupt Mask Register */ 52#define PIO_ISR 0x4c /* PIO Interrupt Status Register */ 53#define PIO_MDER 0x50 /* PIO Multi-Driver Enable Register */ 54#define PIO_MDDR 0x54 /* PIO Multi-Driver Disable Register */ 55#define PIO_MDSR 0x58 /* PIO Multi-Driver Status Register */ 56 /* 0x5c reserved */ 57#define PIO_PUDR 0x60 /* PIO Pull-up Disable Register */ 58#define PIO_PUER 0x64 /* PIO Pull-up Enable Register */ 59#define PIO_PUSR 0x68 /* PIO Pull-up Status Register */ 60 /* 0x6c reserved */ 61#define PIO_ASR 0x70 /* PIO Peripheral A Select Register */ 62#define PIO_BSR 0x74 /* PIO Peripheral B Select Register */ 63#define PIO_ABSR 0x78 /* PIO AB Status Register */ 64 /* 0x7c-0x9c reserved */ 65#define PIO_OWER 0xa0 /* PIO Output Write Enable Register */ 66#define PIO_OWDR 0xa4 /* PIO Output Write Disable Register */ 67#define PIO_OWSR 0xa8 /* PIO Output Write Status Register */ 68 /* 0xac reserved */ 69#endif 70 71#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 72#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 73#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 74#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 75#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 76#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 77#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 78#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 79#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 80#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 81#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 82#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 83#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 84#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 85#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 86#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 87#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 88#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 89#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 90#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 91#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 92#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 93#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 94#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 95#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 96#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 97#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 98#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 99#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 100#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 101#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 102#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 103#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 104#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 105#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 106#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 107#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 108#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 109#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 110#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 111#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 112#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 113#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 114#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 115#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 116#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 117#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 118#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 119#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 120#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 121#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 122#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 123#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 124#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 125#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 126#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 127#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 128#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 129#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 130#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 131#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 132#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 133#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 134#define AT91C_PIO_PB31 ((unsigned int) 1 << 31) // Pin Controlled by PB31 135#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0 136#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1 137#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2 138#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) // Pin Controlled by PC3 139#define AT91C_PIO_PC4 ((unsigned int) 1 << 4) // Pin Controlled by PC4 140#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) // Pin Controlled by PC5 141#define AT91C_PIO_PC6 ((unsigned int) 1 << 6) // Pin Controlled by PC6 142#define AT91C_PIO_PC7 ((unsigned int) 1 << 7) // Pin Controlled by PC7 143#define AT91C_PIO_PC8 ((unsigned int) 1 << 8) // Pin Controlled by PC8 144#define AT91C_PIO_PC9 ((unsigned int) 1 << 9) // Pin Controlled by PC9 145#define AT91C_PIO_PC10 ((unsigned int) 1 << 10) // Pin Controlled by PC10 146#define AT91C_PIO_PC11 ((unsigned int) 1 << 11) // Pin Controlled by PC11 147#define AT91C_PIO_PC12 ((unsigned int) 1 << 12) // Pin Controlled by PC12 148#define AT91C_PIO_PC13 ((unsigned int) 1 << 13) // Pin Controlled by PC13 149#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) // Pin Controlled by PC14 150#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) // Pin Controlled by PC15 151#define AT91C_PIO_PC16 ((unsigned int) 1 << 16) // Pin Controlled by PC16 152#define AT91C_PIO_PC17 ((unsigned int) 1 << 17) // Pin Controlled by PC17 153#define AT91C_PIO_PC18 ((unsigned int) 1 << 18) // Pin Controlled by PC18 154#define AT91C_PIO_PC19 ((unsigned int) 1 << 19) // Pin Controlled by PC19 155#define AT91C_PIO_PC20 ((unsigned int) 1 << 20) // Pin Controlled by PC20 156#define AT91C_PIO_PC21 ((unsigned int) 1 << 21) // Pin Controlled by PC21 157#define AT91C_PIO_PC22 ((unsigned int) 1 << 22) // Pin Controlled by PC22 158#define AT91C_PIO_PC23 ((unsigned int) 1 << 23) // Pin Controlled by PC23 159#define AT91C_PIO_PC24 ((unsigned int) 1 << 24) // Pin Controlled by PC24 160#define AT91C_PIO_PC25 ((unsigned int) 1 << 25) // Pin Controlled by PC25 161#define AT91C_PIO_PC26 ((unsigned int) 1 << 26) // Pin Controlled by PC26 162#define AT91C_PIO_PC27 ((unsigned int) 1 << 27) // Pin Controlled by PC27 163#define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28 164#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 165#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 166#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 167#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0 168#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1 169#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2 170#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) // Pin Controlled by PD3 171#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) // Pin Controlled by PD4 172#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) // Pin Controlled by PD5 173#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) // Pin Controlled by PD6 174#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) // Pin Controlled by PD7 175#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) // Pin Controlled by PD8 176#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) // Pin Controlled by PD9 177#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) // Pin Controlled by PD10 178#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) // Pin Controlled by PD11 179#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) // Pin Controlled by PD12 180#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) // Pin Controlled by PD13 181#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) // Pin Controlled by PD14 182#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15 183#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) // Pin Controlled by PD16 184#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) // Pin Controlled by PD17 185#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) // Pin Controlled by PD18 186#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) // Pin Controlled by PD19 187#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) // Pin Controlled by PD20 188#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) // Pin Controlled by PD21 189#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) // Pin Controlled by PD22 190#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) // Pin Controlled by PD23 191#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) // Pin Controlled by PD24 192#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) // Pin Controlled by PD25 193#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) // Pin Controlled by PD26 194#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) // Pin Controlled by PD27 195#define AT91C_PIO_PD28 ((unsigned int) 1 << 28) // Pin Controlled by PD28 196#define AT91C_PIO_PD29 ((unsigned int) 1 << 29) // Pin Controlled by PD29 197#define AT91C_PIO_PD30 ((unsigned int) 1 << 30) // Pin Controlled by PD30 198#define AT91C_PIO_PD31 ((unsigned int) 1 << 31) // Pin Controlled by PD31 199#define AT91C_PIO_PE0 ((unsigned int) 1 << 0) // Pin Controlled by PE0 200#define AT91C_PIO_PE1 ((unsigned int) 1 << 1) // Pin Controlled by PE1 201#define AT91C_PIO_PE2 ((unsigned int) 1 << 2) // Pin Controlled by PE2 202#define AT91C_PIO_PE3 ((unsigned int) 1 << 3) // Pin Controlled by PE3 203#define AT91C_PIO_PE4 ((unsigned int) 1 << 4) // Pin Controlled by PE4 204#define AT91C_PIO_PE5 ((unsigned int) 1 << 5) // Pin Controlled by PE5 205#define AT91C_PIO_PE6 ((unsigned int) 1 << 6) // Pin Controlled by PE6 206#define AT91C_PIO_PE7 ((unsigned int) 1 << 7) // Pin Controlled by PE7 207#define AT91C_PIO_PE8 ((unsigned int) 1 << 8) // Pin Controlled by PE8 208#define AT91C_PIO_PE9 ((unsigned int) 1 << 9) // Pin Controlled by PE9 209#define AT91C_PIO_PE10 ((unsigned int) 1 << 10) // Pin Controlled by PE10 210#define AT91C_PIO_PE11 ((unsigned int) 1 << 11) // Pin Controlled by PE11 211#define AT91C_PIO_PE12 ((unsigned int) 1 << 12) // Pin Controlled by PE12 212#define AT91C_PIO_PE13 ((unsigned int) 1 << 13) // Pin Controlled by PE13 213#define AT91C_PIO_PE14 ((unsigned int) 1 << 14) // Pin Controlled by PE14 214#define AT91C_PIO_PE15 ((unsigned int) 1 << 15) // Pin Controlled by PE15 215#define AT91C_PIO_PE16 ((unsigned int) 1 << 16) // Pin Controlled by PE16 216#define AT91C_PIO_PE17 ((unsigned int) 1 << 17) // Pin Controlled by PE17 217#define AT91C_PIO_PE18 ((unsigned int) 1 << 18) // Pin Controlled by PE18 218#define AT91C_PIO_PE19 ((unsigned int) 1 << 19) // Pin Controlled by PE19 219#define AT91C_PIO_PE20 ((unsigned int) 1 << 20) // Pin Controlled by PE20 220#define AT91C_PIO_PE21 ((unsigned int) 1 << 21) // Pin Controlled by PE21 221#define AT91C_PIO_PE22 ((unsigned int) 1 << 22) // Pin Controlled by PE22 222#define AT91C_PIO_PE23 ((unsigned int) 1 << 23) // Pin Controlled by PE23 223#define AT91C_PIO_PE24 ((unsigned int) 1 << 24) // Pin Controlled by PE24 224#define AT91C_PIO_PE25 ((unsigned int) 1 << 25) // Pin Controlled by PE25 225#define AT91C_PIO_PE26 ((unsigned int) 1 << 26) // Pin Controlled by PE26 226#define AT91C_PIO_PE27 ((unsigned int) 1 << 27) // Pin Controlled by PE27 227#define AT91C_PIO_PE28 ((unsigned int) 1 << 28) // Pin Controlled by PE28 228#define AT91C_PIO_PE29 ((unsigned int) 1 << 29) // Pin Controlled by PE29 229#define AT91C_PIO_PE30 ((unsigned int) 1 << 30) // Pin Controlled by PE30 230#define AT91C_PIO_PE31 ((unsigned int) 1 << 31) // Pin Controlled by PE31 231 232#endif /* ARM_AT91_AT91_PIOREG_H */ 233