if_emac.c revision 281669
1/*- 2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/arm/allwinner/if_emac.c 281669 2015-04-17 22:17:22Z loos $ 27 */ 28 29/* A10/A20 EMAC driver */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/arm/allwinner/if_emac.c 281669 2015-04-17 22:17:22Z loos $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/lock.h> 40#include <sys/mbuf.h> 41#include <sys/mutex.h> 42#include <sys/rman.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/gpio.h> 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50#include <machine/intr.h> 51 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_arp.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_mib.h> 59#include <net/ethernet.h> 60#include <net/if_vlan_var.h> 61 62#ifdef INET 63#include <netinet/in.h> 64#include <netinet/in_systm.h> 65#include <netinet/in_var.h> 66#include <netinet/ip.h> 67#endif 68 69#include <net/bpf.h> 70#include <net/bpfdesc.h> 71 72#include <dev/fdt/fdt_common.h> 73#include <dev/ofw/ofw_bus.h> 74#include <dev/ofw/ofw_bus_subr.h> 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <arm/allwinner/if_emacreg.h> 80 81#include "miibus_if.h" 82 83#include "gpio_if.h" 84 85#include "a10_clk.h" 86#include "a10_sramc.h" 87#include "a10_gpio.h" 88 89struct emac_softc { 90 struct ifnet *emac_ifp; 91 device_t emac_dev; 92 device_t emac_miibus; 93 bus_space_handle_t emac_handle; 94 bus_space_tag_t emac_tag; 95 struct resource *emac_res; 96 struct resource *emac_irq; 97 void *emac_intrhand; 98 int emac_if_flags; 99 struct mtx emac_mtx; 100 struct callout emac_tick_ch; 101 int emac_watchdog_timer; 102 int emac_rx_process_limit; 103 int emac_link; 104}; 105 106static int emac_probe(device_t); 107static int emac_attach(device_t); 108static int emac_detach(device_t); 109static int emac_shutdown(device_t); 110static int emac_suspend(device_t); 111static int emac_resume(device_t); 112 113static void emac_sys_setup(void); 114static void emac_reset(struct emac_softc *); 115 116static void emac_init_locked(struct emac_softc *); 117static void emac_start_locked(struct ifnet *); 118static void emac_init(void *); 119static void emac_stop_locked(struct emac_softc *); 120static void emac_intr(void *); 121static int emac_ioctl(struct ifnet *, u_long, caddr_t); 122 123static void emac_rxeof(struct emac_softc *, int); 124static void emac_txeof(struct emac_softc *); 125 126static int emac_miibus_readreg(device_t, int, int); 127static int emac_miibus_writereg(device_t, int, int, int); 128static void emac_miibus_statchg(device_t); 129 130static int emac_ifmedia_upd(struct ifnet *); 131static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 134static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 135 136#define EMAC_READ_REG(sc, reg) \ 137 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 138#define EMAC_WRITE_REG(sc, reg, val) \ 139 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 140 141static void 142emac_sys_setup(void) 143{ 144 int i; 145 146 a10_clk_emac_activate(); 147 148 /* 149 * Configure pin mux settings for MII. 150 * Pins PA0 from PA17. 151 */ 152 for (i = 0; i <= 17; i++) 153 a10_emac_gpio_config(i); 154 /* Map sram */ 155 a10_map_to_emac(); 156} 157 158static void 159emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 160{ 161 uint32_t val0, val1, rnd; 162 163 /* 164 * Try to get MAC address from running hardware. 165 * If there is something non-zero there just use it. 166 * 167 * Otherwise set the address to a convenient locally assigned address, 168 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 169 * assigned bit set, and the broadcast/multicast bit clear. 170 */ 171 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 172 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 173 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 174 hwaddr[0] = (val1 >> 16) & 0xff; 175 hwaddr[1] = (val1 >> 8) & 0xff; 176 hwaddr[2] = (val1 >> 0) & 0xff; 177 hwaddr[3] = (val0 >> 16) & 0xff; 178 hwaddr[4] = (val0 >> 8) & 0xff; 179 hwaddr[5] = (val0 >> 0) & 0xff; 180 } else { 181 rnd = arc4random() & 0x00ffffff; 182 hwaddr[0] = 'b'; 183 hwaddr[1] = 's'; 184 hwaddr[2] = 'd'; 185 hwaddr[3] = (rnd >> 16) & 0xff; 186 hwaddr[4] = (rnd >> 8) & 0xff; 187 hwaddr[5] = (rnd >> 0) & 0xff; 188 } 189 if (bootverbose) 190 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 191} 192 193static void 194emac_set_rx_mode(struct emac_softc *sc) 195{ 196 struct ifnet *ifp; 197 struct ifmultiaddr *ifma; 198 uint32_t h, hashes[2]; 199 uint32_t rcr = 0; 200 201 EMAC_ASSERT_LOCKED(sc); 202 203 ifp = sc->emac_ifp; 204 205 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 206 207 /* Unicast packet and DA filtering */ 208 rcr |= EMAC_RX_UCAD; 209 rcr |= EMAC_RX_DAF; 210 211 hashes[0] = 0; 212 hashes[1] = 0; 213 if (ifp->if_flags & IFF_ALLMULTI) { 214 hashes[0] = 0xffffffff; 215 hashes[1] = 0xffffffff; 216 } else { 217 if_maddr_rlock(ifp); 218 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) { 219 if (ifma->ifma_addr->sa_family != AF_LINK) 220 continue; 221 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 222 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 223 hashes[h >> 5] |= 1 << (h & 0x1f); 224 } 225 if_maddr_runlock(ifp); 226 } 227 rcr |= EMAC_RX_MCO; 228 rcr |= EMAC_RX_MHF; 229 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 230 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 231 232 if (ifp->if_flags & IFF_BROADCAST) { 233 rcr |= EMAC_RX_BCO; 234 rcr |= EMAC_RX_MCO; 235 } 236 237 if (ifp->if_flags & IFF_PROMISC) 238 rcr |= EMAC_RX_PA; 239 else 240 rcr |= EMAC_RX_UCAD; 241 242 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 243} 244 245static void 246emac_reset(struct emac_softc *sc) 247{ 248 249 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 250 DELAY(200); 251 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 252 DELAY(200); 253} 254 255static void 256emac_txeof(struct emac_softc *sc) 257{ 258 struct ifnet *ifp; 259 260 EMAC_ASSERT_LOCKED(sc); 261 262 ifp = sc->emac_ifp; 263 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 264 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 265 266 /* Unarm watchdog timer if no TX */ 267 sc->emac_watchdog_timer = 0; 268} 269 270static void 271emac_rxeof(struct emac_softc *sc, int count) 272{ 273 struct ifnet *ifp; 274 struct mbuf *m, *m0; 275 uint32_t reg_val, rxcount; 276 int16_t len; 277 uint16_t status; 278 int good_packet, i; 279 280 ifp = sc->emac_ifp; 281 for (; count > 0 && 282 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 283 /* 284 * Race warning: The first packet might arrive with 285 * the interrupts disabled, but the second will fix 286 */ 287 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 288 if (!rxcount) { 289 /* Had one stuck? */ 290 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 291 if (!rxcount) 292 return; 293 } 294 /* Check packet header */ 295 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 296 if (reg_val != EMAC_PACKET_HEADER) { 297 /* Packet header is wrong */ 298 if (bootverbose) 299 if_printf(ifp, "wrong packet header\n"); 300 /* Disable RX */ 301 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 302 reg_val &= ~EMAC_CTL_RX_EN; 303 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 304 305 /* Flush RX FIFO */ 306 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 307 reg_val |= EMAC_RX_FLUSH_FIFO; 308 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 309 for (i = 100; i > 0; i--) { 310 DELAY(100); 311 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 312 EMAC_RX_FLUSH_FIFO) == 0) 313 break; 314 } 315 if (i == 0) { 316 device_printf(sc->emac_dev, 317 "flush FIFO timeout\n"); 318 /* Reinitialize controller */ 319 emac_init_locked(sc); 320 return; 321 } 322 /* Enable RX */ 323 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 324 reg_val |= EMAC_CTL_RX_EN; 325 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 326 327 return; 328 } 329 330 good_packet = 1; 331 332 /* Get packet size and status */ 333 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 334 len = reg_val & 0xffff; 335 status = (reg_val >> 16) & 0xffff; 336 337 if (len < 64) { 338 good_packet = 0; 339 if (bootverbose) 340 if_printf(ifp, 341 "bad packet: len = %i status = %i\n", 342 len, status); 343 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 344 } 345#if 0 346 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 347 good_packet = 0; 348 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 349 if (status & EMAC_CRCERR) 350 if_printf(ifp, "crc error\n"); 351 if (status & EMAC_LENERR) 352 if_printf(ifp, "length error\n"); 353 } 354#endif 355 if (good_packet) { 356 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 357 if (m == NULL) 358 return; 359 m->m_len = m->m_pkthdr.len = MCLBYTES; 360 361 /* Copy entire frame to mbuf first. */ 362 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 363 EMAC_RX_IO_DATA, mtod(m, uint32_t *), 364 roundup2(len, 4) / 4); 365 366 m->m_pkthdr.rcvif = ifp; 367 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 368 369 /* 370 * Emac controller needs strict aligment, so to avoid 371 * copying over an entire frame to align, we allocate 372 * a new mbuf and copy ethernet header + IP header to 373 * the new mbuf. The new mbuf is prepended into the 374 * existing mbuf chain. 375 */ 376 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 377 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, 378 m->m_len); 379 m->m_data += ETHER_HDR_LEN; 380 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 381 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 382 MGETHDR(m0, M_NOWAIT, MT_DATA); 383 if (m0 != NULL) { 384 len = ETHER_HDR_LEN + 385 m->m_pkthdr.l2hlen; 386 bcopy(m->m_data, m0->m_data, len); 387 m->m_data += len; 388 m->m_len -= len; 389 m0->m_len = len; 390 M_MOVE_PKTHDR(m0, m); 391 m0->m_next = m; 392 m = m0; 393 } else { 394 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 395 m_freem(m); 396 m = NULL; 397 continue; 398 } 399 } else if (m->m_len > EMAC_MAC_MAXF) { 400 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 401 m_freem(m); 402 m = NULL; 403 continue; 404 } 405 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 406 EMAC_UNLOCK(sc); 407 (*ifp->if_input)(ifp, m); 408 EMAC_LOCK(sc); 409 } 410 } 411} 412 413static void 414emac_watchdog(struct emac_softc *sc) 415{ 416 struct ifnet *ifp; 417 418 EMAC_ASSERT_LOCKED(sc); 419 420 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 421 return; 422 423 ifp = sc->emac_ifp; 424 425 if (sc->emac_link == 0) { 426 if (bootverbose) 427 if_printf(sc->emac_ifp, "watchdog timeout " 428 "(missed link)\n"); 429 } else 430 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 431 432 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 433 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 434 emac_init_locked(sc); 435 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 436 emac_start_locked(ifp); 437} 438 439static void 440emac_tick(void *arg) 441{ 442 struct emac_softc *sc; 443 struct mii_data *mii; 444 445 sc = (struct emac_softc *)arg; 446 mii = device_get_softc(sc->emac_miibus); 447 mii_tick(mii); 448 449 emac_watchdog(sc); 450 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 451} 452 453static void 454emac_init(void *xcs) 455{ 456 struct emac_softc *sc; 457 458 sc = (struct emac_softc *)xcs; 459 EMAC_LOCK(sc); 460 emac_init_locked(sc); 461 EMAC_UNLOCK(sc); 462} 463 464static void 465emac_init_locked(struct emac_softc *sc) 466{ 467 struct ifnet *ifp; 468 struct mii_data *mii; 469 uint32_t reg_val; 470 uint8_t *eaddr; 471 472 EMAC_ASSERT_LOCKED(sc); 473 474 ifp = sc->emac_ifp; 475 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 476 return; 477 478 /* Flush RX FIFO */ 479 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 480 reg_val |= EMAC_RX_FLUSH_FIFO; 481 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 482 DELAY(1); 483 484 /* Soft reset MAC */ 485 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 486 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 487 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 488 489 /* Set MII clock */ 490 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 491 reg_val &= (~(0xf << 2)); 492 reg_val |= (0xd << 2); 493 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 494 495 /* Clear RX counter */ 496 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 497 498 /* Disable all interrupt and clear interrupt status */ 499 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 500 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 501 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 502 DELAY(1); 503 504 /* Set up TX */ 505 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 506 reg_val |= EMAC_TX_AB_M; 507 reg_val &= EMAC_TX_TM; 508 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 509 510 /* Set up RX */ 511 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 512 reg_val |= EMAC_RX_SETUP; 513 reg_val &= EMAC_RX_TM; 514 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 515 516 /* Set up MAC CTL0. */ 517 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 518 reg_val |= EMAC_MAC_CTL0_SETUP; 519 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 520 521 /* Set up MAC CTL1. */ 522 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 523 reg_val |= EMAC_MAC_CTL1_SETUP; 524 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 525 526 /* Set up IPGT */ 527 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 528 529 /* Set up IPGR */ 530 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 531 (EMAC_MAC_NBTB_IPG1 << 8)); 532 533 /* Set up Collison window */ 534 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 535 536 /* Set up Max Frame Length */ 537 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 538 539 /* Setup ethernet address */ 540 eaddr = IF_LLADDR(ifp); 541 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 542 eaddr[1] << 8 | eaddr[2]); 543 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 544 eaddr[4] << 8 | eaddr[5]); 545 546 /* Setup rx filter */ 547 emac_set_rx_mode(sc); 548 549 /* Enable RX/TX0/RX Hlevel interrupt */ 550 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 551 reg_val |= EMAC_INT_EN; 552 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 553 554 ifp->if_drv_flags |= IFF_DRV_RUNNING; 555 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 556 557 sc->emac_link = 0; 558 559 /* Switch to the current media. */ 560 mii = device_get_softc(sc->emac_miibus); 561 mii_mediachg(mii); 562 563 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 564} 565 566 567static void 568emac_start(struct ifnet *ifp) 569{ 570 struct emac_softc *sc; 571 572 sc = ifp->if_softc; 573 EMAC_LOCK(sc); 574 emac_start_locked(ifp); 575 EMAC_UNLOCK(sc); 576} 577 578static void 579emac_start_locked(struct ifnet *ifp) 580{ 581 struct emac_softc *sc; 582 struct mbuf *m, *m0; 583 uint32_t reg_val; 584 585 sc = ifp->if_softc; 586 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 587 return; 588 if (sc->emac_link == 0) 589 return; 590 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 591 if (m == NULL) 592 return; 593 594 /* Select channel */ 595 EMAC_WRITE_REG(sc, EMAC_TX_INS, 0); 596 597 /* 598 * Emac controller wants 4 byte aligned TX buffers. 599 * We have to copy pretty much all the time. 600 */ 601 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 602 m0 = m_defrag(m, M_NOWAIT); 603 if (m0 == NULL) { 604 m_freem(m); 605 m = NULL; 606 return; 607 } 608 m = m0; 609 } 610 /* Write data */ 611 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 612 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 613 roundup2(m->m_len, 4) / 4); 614 615 /* Send the data lengh. */ 616 EMAC_WRITE_REG(sc, EMAC_TX_PL0, m->m_len); 617 618 /* Start translate from fifo to phy. */ 619 reg_val = EMAC_READ_REG(sc, EMAC_TX_CTL0); 620 reg_val |= 1; 621 EMAC_WRITE_REG(sc, EMAC_TX_CTL0, reg_val); 622 623 /* Set timeout */ 624 sc->emac_watchdog_timer = 5; 625 626 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 627 BPF_MTAP(ifp, m); 628 m_freem(m); 629} 630 631static void 632emac_stop_locked(struct emac_softc *sc) 633{ 634 struct ifnet *ifp; 635 uint32_t reg_val; 636 637 EMAC_ASSERT_LOCKED(sc); 638 639 ifp = sc->emac_ifp; 640 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 641 sc->emac_link = 0; 642 643 /* Disable all interrupt and clear interrupt status */ 644 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 645 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 646 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 647 648 /* Disable RX/TX */ 649 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 650 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 651 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 652 653 callout_stop(&sc->emac_tick_ch); 654} 655 656static void 657emac_intr(void *arg) 658{ 659 struct emac_softc *sc; 660 struct ifnet *ifp; 661 uint32_t reg_val; 662 663 sc = (struct emac_softc *)arg; 664 EMAC_LOCK(sc); 665 666 /* Disable all interrupts */ 667 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 668 /* Get EMAC interrupt status */ 669 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 670 /* Clear ISR status */ 671 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 672 673 /* Received incoming packet */ 674 if (reg_val & EMAC_INT_STA_RX) 675 emac_rxeof(sc, sc->emac_rx_process_limit); 676 677 /* Transmit Interrupt check */ 678 if (reg_val & EMAC_INT_STA_TX) { 679 emac_txeof(sc); 680 ifp = sc->emac_ifp; 681 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 682 emac_start_locked(ifp); 683 } 684 685 /* Re-enable interrupt mask */ 686 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 687 reg_val |= EMAC_INT_EN; 688 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 689 EMAC_UNLOCK(sc); 690} 691 692static int 693emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 694{ 695 struct emac_softc *sc; 696 struct mii_data *mii; 697 struct ifreq *ifr; 698 int error = 0; 699 700 sc = ifp->if_softc; 701 ifr = (struct ifreq *)data; 702 703 switch (command) { 704 case SIOCSIFFLAGS: 705 EMAC_LOCK(sc); 706 if (ifp->if_flags & IFF_UP) { 707 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 708 if ((ifp->if_flags ^ sc->emac_if_flags) & 709 (IFF_PROMISC | IFF_ALLMULTI)) 710 emac_set_rx_mode(sc); 711 } else 712 emac_init_locked(sc); 713 } else { 714 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 715 emac_stop_locked(sc); 716 } 717 sc->emac_if_flags = ifp->if_flags; 718 EMAC_UNLOCK(sc); 719 break; 720 case SIOCADDMULTI: 721 case SIOCDELMULTI: 722 EMAC_LOCK(sc); 723 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 724 emac_set_rx_mode(sc); 725 } 726 EMAC_UNLOCK(sc); 727 break; 728 case SIOCGIFMEDIA: 729 case SIOCSIFMEDIA: 730 mii = device_get_softc(sc->emac_miibus); 731 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 732 break; 733 default: 734 error = ether_ioctl(ifp, command, data); 735 break; 736 } 737 return (error); 738} 739 740static int 741emac_probe(device_t dev) 742{ 743 744 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-emac")) 745 return (ENXIO); 746 747 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 748 return (BUS_PROBE_DEFAULT); 749} 750 751static int 752emac_detach(device_t dev) 753{ 754 struct emac_softc *sc; 755 756 sc = device_get_softc(dev); 757 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 758 if (device_is_attached(dev)) { 759 ether_ifdetach(sc->emac_ifp); 760 EMAC_LOCK(sc); 761 emac_stop_locked(sc); 762 EMAC_UNLOCK(sc); 763 callout_drain(&sc->emac_tick_ch); 764 } 765 766 if (sc->emac_intrhand != NULL) 767 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 768 sc->emac_intrhand); 769 770 if (sc->emac_miibus != NULL) { 771 device_delete_child(sc->emac_dev, sc->emac_miibus); 772 bus_generic_detach(sc->emac_dev); 773 } 774 775 if (sc->emac_res != NULL) 776 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 777 778 if (sc->emac_irq != NULL) 779 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 780 781 if (sc->emac_ifp != NULL) 782 if_free(sc->emac_ifp); 783 784 if (mtx_initialized(&sc->emac_mtx)) 785 mtx_destroy(&sc->emac_mtx); 786 787 return (0); 788} 789 790static int 791emac_shutdown(device_t dev) 792{ 793 794 return (emac_suspend(dev)); 795} 796 797static int 798emac_suspend(device_t dev) 799{ 800 struct emac_softc *sc; 801 struct ifnet *ifp; 802 803 sc = device_get_softc(dev); 804 805 EMAC_LOCK(sc); 806 ifp = sc->emac_ifp; 807 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 808 emac_stop_locked(sc); 809 EMAC_UNLOCK(sc); 810 811 return (0); 812} 813 814static int 815emac_resume(device_t dev) 816{ 817 struct emac_softc *sc; 818 struct ifnet *ifp; 819 820 sc = device_get_softc(dev); 821 822 EMAC_LOCK(sc); 823 ifp = sc->emac_ifp; 824 if ((ifp->if_flags & IFF_UP) != 0) { 825 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 826 emac_init_locked(sc); 827 } 828 EMAC_UNLOCK(sc); 829 830 return (0); 831} 832 833static int 834emac_attach(device_t dev) 835{ 836 struct emac_softc *sc; 837 struct ifnet *ifp; 838 int error, rid; 839 uint8_t eaddr[ETHER_ADDR_LEN]; 840 841 sc = device_get_softc(dev); 842 sc->emac_dev = dev; 843 844 error = 0; 845 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 846 MTX_DEF); 847 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 848 849 rid = 0; 850 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 851 RF_ACTIVE); 852 if (sc->emac_res == NULL) { 853 device_printf(dev, "unable to map memory\n"); 854 error = ENXIO; 855 goto fail; 856 } 857 858 sc->emac_tag = rman_get_bustag(sc->emac_res); 859 sc->emac_handle = rman_get_bushandle(sc->emac_res); 860 861 rid = 0; 862 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 863 RF_SHAREABLE | RF_ACTIVE); 864 if (sc->emac_irq == NULL) { 865 device_printf(dev, "cannot allocate IRQ resources.\n"); 866 error = ENXIO; 867 goto fail; 868 } 869 /* Create device sysctl node. */ 870 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 871 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 872 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 873 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 874 "max number of Rx events to process"); 875 876 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 877 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 878 "process_limit", &sc->emac_rx_process_limit); 879 if (error == 0) { 880 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 881 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 882 device_printf(dev, "process_limit value out of range; " 883 "using default: %d\n", EMAC_PROC_DEFAULT); 884 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 885 } 886 } 887 /* Setup EMAC */ 888 emac_sys_setup(); 889 emac_reset(sc); 890 891 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 892 if (ifp == NULL) { 893 device_printf(dev, "unable to allocate ifp\n"); 894 error = ENOSPC; 895 goto fail; 896 } 897 ifp->if_softc = sc; 898 899 /* Setup MII */ 900 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 901 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 902 if (error != 0) { 903 device_printf(dev, "PHY probe failed\n"); 904 goto fail; 905 } 906 907 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 908 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 909 ifp->if_start = emac_start; 910 ifp->if_ioctl = emac_ioctl; 911 ifp->if_init = emac_init; 912 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 913 914 /* Get MAC address */ 915 emac_get_hwaddr(sc, eaddr); 916 ether_ifattach(ifp, eaddr); 917 918 /* VLAN capability setup. */ 919 ifp->if_capabilities |= IFCAP_VLAN_MTU; 920 ifp->if_capenable = ifp->if_capabilities; 921 /* Tell the upper layer we support VLAN over-sized frames. */ 922 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 923 924 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 925 NULL, emac_intr, sc, &sc->emac_intrhand); 926 if (error != 0) { 927 device_printf(dev, "could not set up interrupt handler.\n"); 928 ether_ifdetach(ifp); 929 goto fail; 930 } 931 932fail: 933 if (error != 0) 934 emac_detach(dev); 935 return (error); 936} 937 938static boolean_t 939emac_miibus_iowait(struct emac_softc *sc) 940{ 941 uint32_t timeout; 942 943 for (timeout = 100; timeout != 0; --timeout) { 944 DELAY(100); 945 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 946 return (true); 947 } 948 949 return (false); 950} 951 952/* 953 * The MII bus interface 954 */ 955static int 956emac_miibus_readreg(device_t dev, int phy, int reg) 957{ 958 struct emac_softc *sc; 959 int rval; 960 961 sc = device_get_softc(dev); 962 963 /* Issue phy address and reg */ 964 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 965 /* Pull up the phy io line */ 966 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 967 if (!emac_miibus_iowait(sc)) { 968 device_printf(dev, "timeout waiting for mii read\n"); 969 return (0); 970 } 971 /* Push down the phy io line */ 972 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 973 /* Read data */ 974 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 975 976 return (rval); 977} 978 979static int 980emac_miibus_writereg(device_t dev, int phy, int reg, int data) 981{ 982 struct emac_softc *sc; 983 984 sc = device_get_softc(dev); 985 986 /* Issue phy address and reg */ 987 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 988 /* Write data */ 989 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 990 /* Pull up the phy io line */ 991 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 992 if (!emac_miibus_iowait(sc)) { 993 device_printf(dev, "timeout waiting for mii write\n"); 994 return (0); 995 } 996 /* Push down the phy io line */ 997 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 998 999 return (0); 1000} 1001 1002static void 1003emac_miibus_statchg(device_t dev) 1004{ 1005 struct emac_softc *sc; 1006 struct mii_data *mii; 1007 struct ifnet *ifp; 1008 uint32_t reg_val; 1009 1010 sc = device_get_softc(dev); 1011 1012 mii = device_get_softc(sc->emac_miibus); 1013 ifp = sc->emac_ifp; 1014 if (mii == NULL || ifp == NULL || 1015 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1016 return; 1017 1018 sc->emac_link = 0; 1019 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1020 (IFM_ACTIVE | IFM_AVALID)) { 1021 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1022 case IFM_10_T: 1023 case IFM_100_TX: 1024 sc->emac_link = 1; 1025 break; 1026 default: 1027 break; 1028 } 1029 } 1030 /* Program MACs with resolved speed/duplex. */ 1031 if (sc->emac_link != 0) { 1032 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1033 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1034 reg_val &= ~EMAC_MAC_IPGT_HD; 1035 reg_val |= EMAC_MAC_IPGT_FD; 1036 } else { 1037 reg_val &= ~EMAC_MAC_IPGT_FD; 1038 reg_val |= EMAC_MAC_IPGT_HD; 1039 } 1040 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1041 /* Enable RX/TX */ 1042 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1043 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1044 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1045 } else { 1046 /* Disable RX/TX */ 1047 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1048 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1049 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1050 } 1051} 1052 1053static int 1054emac_ifmedia_upd(struct ifnet *ifp) 1055{ 1056 struct emac_softc *sc; 1057 struct mii_data *mii; 1058 struct mii_softc *miisc; 1059 int error; 1060 1061 sc = ifp->if_softc; 1062 mii = device_get_softc(sc->emac_miibus); 1063 EMAC_LOCK(sc); 1064 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1065 PHY_RESET(miisc); 1066 error = mii_mediachg(mii); 1067 EMAC_UNLOCK(sc); 1068 1069 return (error); 1070} 1071 1072static void 1073emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1074{ 1075 struct emac_softc *sc; 1076 struct mii_data *mii; 1077 1078 sc = ifp->if_softc; 1079 mii = device_get_softc(sc->emac_miibus); 1080 1081 EMAC_LOCK(sc); 1082 mii_pollstat(mii); 1083 ifmr->ifm_active = mii->mii_media_active; 1084 ifmr->ifm_status = mii->mii_media_status; 1085 EMAC_UNLOCK(sc); 1086} 1087 1088static device_method_t emac_methods[] = { 1089 /* Device interface */ 1090 DEVMETHOD(device_probe, emac_probe), 1091 DEVMETHOD(device_attach, emac_attach), 1092 DEVMETHOD(device_detach, emac_detach), 1093 DEVMETHOD(device_shutdown, emac_shutdown), 1094 DEVMETHOD(device_suspend, emac_suspend), 1095 DEVMETHOD(device_resume, emac_resume), 1096 1097 /* bus interface, for miibus */ 1098 DEVMETHOD(bus_print_child, bus_generic_print_child), 1099 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1100 1101 /* MII interface */ 1102 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1103 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1104 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1105 1106 DEVMETHOD_END 1107}; 1108 1109static driver_t emac_driver = { 1110 "emac", 1111 emac_methods, 1112 sizeof(struct emac_softc) 1113}; 1114 1115static devclass_t emac_devclass; 1116 1117DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1118DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1119MODULE_DEPEND(emac, miibus, 1, 1, 1); 1120MODULE_DEPEND(emac, ether, 1, 1, 1); 1121 1122static int 1123sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1124{ 1125 int error, value; 1126 1127 if (arg1 == NULL) 1128 return (EINVAL); 1129 value = *(int *)arg1; 1130 error = sysctl_handle_int(oidp, &value, 0, req); 1131 if (error || req->newptr == NULL) 1132 return (error); 1133 if (value < low || value > high) 1134 return (EINVAL); 1135 *(int *)arg1 = value; 1136 1137 return (0); 1138} 1139 1140static int 1141sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1142{ 1143 1144 return (sysctl_int_range(oidp, arg1, arg2, req, 1145 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1146} 1147