1//===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the main function for LLVM's TableGen. 11// 12//===----------------------------------------------------------------------===// 13 14#include "TableGenBackends.h" // Declares all backends. 15#include "llvm/Support/CommandLine.h" 16#include "llvm/Support/ManagedStatic.h" 17#include "llvm/Support/PrettyStackTrace.h" 18#include "llvm/Support/Signals.h" 19#include "llvm/TableGen/Error.h" 20#include "llvm/TableGen/Main.h" 21#include "llvm/TableGen/Record.h" 22#include "llvm/TableGen/SetTheory.h" 23 24using namespace llvm; 25 26enum ActionType { 27 PrintRecords, 28 GenEmitter, 29 GenRegisterInfo, 30 GenInstrInfo, 31 GenAsmWriter, 32 GenAsmMatcher, 33 GenDisassembler, 34 GenPseudoLowering, 35 GenCallingConv, 36 GenDAGISel, 37 GenDFAPacketizer, 38 GenFastISel, 39 GenSubtarget, 40 GenIntrinsic, 41 GenTgtIntrinsic, 42 PrintEnums, 43 PrintSets, 44 GenOptParserDefs, 45 GenCTags, 46 GenAttributes 47}; 48 49namespace { 50 cl::opt<ActionType> 51 Action(cl::desc("Action to perform:"), 52 cl::values(clEnumValN(PrintRecords, "print-records", 53 "Print all records to stdout (default)"), 54 clEnumValN(GenEmitter, "gen-emitter", 55 "Generate machine code emitter"), 56 clEnumValN(GenRegisterInfo, "gen-register-info", 57 "Generate registers and register classes info"), 58 clEnumValN(GenInstrInfo, "gen-instr-info", 59 "Generate instruction descriptions"), 60 clEnumValN(GenCallingConv, "gen-callingconv", 61 "Generate calling convention descriptions"), 62 clEnumValN(GenAsmWriter, "gen-asm-writer", 63 "Generate assembly writer"), 64 clEnumValN(GenDisassembler, "gen-disassembler", 65 "Generate disassembler"), 66 clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", 67 "Generate pseudo instruction lowering"), 68 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 69 "Generate assembly instruction matcher"), 70 clEnumValN(GenDAGISel, "gen-dag-isel", 71 "Generate a DAG instruction selector"), 72 clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer", 73 "Generate DFA Packetizer for VLIW targets"), 74 clEnumValN(GenFastISel, "gen-fast-isel", 75 "Generate a \"fast\" instruction selector"), 76 clEnumValN(GenSubtarget, "gen-subtarget", 77 "Generate subtarget enumerations"), 78 clEnumValN(GenIntrinsic, "gen-intrinsic", 79 "Generate intrinsic information"), 80 clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", 81 "Generate target intrinsic information"), 82 clEnumValN(PrintEnums, "print-enums", 83 "Print enum values for a class"), 84 clEnumValN(PrintSets, "print-sets", 85 "Print expanded sets for testing DAG exprs"), 86 clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", 87 "Generate option definitions"), 88 clEnumValN(GenCTags, "gen-ctags", 89 "Generate ctags-compatible index"), 90 clEnumValN(GenAttributes, "gen-attrs", 91 "Generate attributes"), 92 clEnumValEnd)); 93 94 cl::opt<std::string> 95 Class("class", cl::desc("Print Enum list for this class"), 96 cl::value_desc("class name")); 97 98bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 99 switch (Action) { 100 case PrintRecords: 101 OS << Records; // No argument, dump all contents 102 break; 103 case GenEmitter: 104 EmitCodeEmitter(Records, OS); 105 break; 106 case GenRegisterInfo: 107 EmitRegisterInfo(Records, OS); 108 break; 109 case GenInstrInfo: 110 EmitInstrInfo(Records, OS); 111 break; 112 case GenCallingConv: 113 EmitCallingConv(Records, OS); 114 break; 115 case GenAsmWriter: 116 EmitAsmWriter(Records, OS); 117 break; 118 case GenAsmMatcher: 119 EmitAsmMatcher(Records, OS); 120 break; 121 case GenDisassembler: 122 EmitDisassembler(Records, OS); 123 break; 124 case GenPseudoLowering: 125 EmitPseudoLowering(Records, OS); 126 break; 127 case GenDAGISel: 128 EmitDAGISel(Records, OS); 129 break; 130 case GenDFAPacketizer: 131 EmitDFAPacketizer(Records, OS); 132 break; 133 case GenFastISel: 134 EmitFastISel(Records, OS); 135 break; 136 case GenSubtarget: 137 EmitSubtarget(Records, OS); 138 break; 139 case GenIntrinsic: 140 EmitIntrinsics(Records, OS); 141 break; 142 case GenTgtIntrinsic: 143 EmitIntrinsics(Records, OS, true); 144 break; 145 case GenOptParserDefs: 146 EmitOptParser(Records, OS); 147 break; 148 case PrintEnums: 149 { 150 for (Record *Rec : Records.getAllDerivedDefinitions(Class)) 151 OS << Rec->getName() << ", "; 152 OS << "\n"; 153 break; 154 } 155 case PrintSets: 156 { 157 SetTheory Sets; 158 Sets.addFieldExpander("Set", "Elements"); 159 for (Record *Rec : Records.getAllDerivedDefinitions("Set")) { 160 OS << Rec->getName() << " = ["; 161 const std::vector<Record*> *Elts = Sets.expand(Rec); 162 assert(Elts && "Couldn't expand Set instance"); 163 for (Record *Elt : *Elts) 164 OS << ' ' << Elt->getName(); 165 OS << " ]\n"; 166 } 167 break; 168 } 169 case GenCTags: 170 EmitCTags(Records, OS); 171 break; 172 case GenAttributes: 173 EmitAttributes(Records, OS); 174 break; 175 } 176 177 return false; 178} 179} 180 181int main(int argc, char **argv) { 182 sys::PrintStackTraceOnErrorSignal(); 183 PrettyStackTraceProgram X(argc, argv); 184 cl::ParseCommandLineOptions(argc, argv); 185 186 llvm_shutdown_obj Y; 187 188 return TableGenMain(argv[0], &LLVMTableGenMain); 189} 190 191#ifdef __has_feature 192#if __has_feature(address_sanitizer) 193#include <sanitizer/lsan_interface.h> 194// Disable LeakSanitizer for this binary as it has too many leaks that are not 195// very interesting to fix. See compiler-rt/include/sanitizer/lsan_interface.h . 196int __lsan_is_turned_off() { return 1; } 197#endif // __has_feature(address_sanitizer) 198#endif // defined(__has_feature) 199