X86TargetMachine.cpp revision 261991
1117397Skan//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2117397Skan// 3169691Skan// The LLVM Compiler Infrastructure 4117397Skan// 5117397Skan// This file is distributed under the University of Illinois Open Source 6117397Skan// License. See LICENSE.TXT for details. 7117397Skan// 8117397Skan//===----------------------------------------------------------------------===// 9117397Skan// 10117397Skan// This file defines the X86 specific subclass of TargetMachine. 11117397Skan// 12117397Skan//===----------------------------------------------------------------------===// 13117397Skan 14117397Skan#include "X86TargetMachine.h" 15117397Skan#include "X86.h" 16117397Skan#include "llvm/CodeGen/MachineFunction.h" 17117397Skan#include "llvm/CodeGen/Passes.h" 18169691Skan#include "llvm/PassManager.h" 19117397Skan#include "llvm/Support/CommandLine.h" 20117397Skan#include "llvm/Support/FormattedStream.h" 21117397Skan#include "llvm/Support/TargetRegistry.h" 22117397Skan#include "llvm/Target/TargetOptions.h" 23117397Skanusing namespace llvm; 24117397Skan 25117397Skanextern "C" void LLVMInitializeX86Target() { 26117397Skan // Register the target. 27117397Skan RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); 28117397Skan RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); 29117397Skan} 30117397Skan 31117397Skanvoid X86_32TargetMachine::anchor() { } 32117397Skan 33117397SkanX86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, 34117397Skan StringRef CPU, StringRef FS, 35117397Skan const TargetOptions &Options, 36117397Skan Reloc::Model RM, CodeModel::Model CM, 37117397Skan CodeGenOpt::Level OL) 38117397Skan : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 39117397Skan DL(getSubtargetImpl()->isTargetDarwin() ? 40117397Skan "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-" 41117397Skan "n8:16:32-S128" : 42117397Skan (getSubtargetImpl()->isTargetCygMing() || 43117397Skan getSubtargetImpl()->isTargetWindows()) ? 44117397Skan "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-" 45117397Skan "n8:16:32-S32" : 46117397Skan "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-" 47117397Skan "n8:16:32-S128"), 48117397Skan InstrInfo(*this), 49117397Skan TLInfo(*this), 50117397Skan TSInfo(*this), 51117397Skan JITInfo(*this) { 52117397Skan initAsmInfo(); 53117397Skan} 54117397Skan 55117397Skanvoid X86_64TargetMachine::anchor() { } 56117397Skan 57117397SkanX86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, 58117397Skan StringRef CPU, StringRef FS, 59117397Skan const TargetOptions &Options, 60117397Skan Reloc::Model RM, CodeModel::Model CM, 61132720Skan CodeGenOpt::Level OL) 62132720Skan : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 63117397Skan // The x32 ABI dictates the ILP32 programming model for x64. 64169691Skan DL(getSubtargetImpl()->isTarget64BitILP32() ? 65169691Skan "e-p:32:32-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" 66117397Skan "n8:16:32:64-S128" : 67117397Skan "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" 68169691Skan "n8:16:32:64-S128"), 69117397Skan InstrInfo(*this), 70117397Skan TLInfo(*this), 71117397Skan TSInfo(*this), 72132720Skan JITInfo(*this) { 73117397Skan initAsmInfo(); 74117397Skan} 75117397Skan 76169691Skan/// X86TargetMachine ctor - Create an X86 target. 77132720Skan/// 78169691SkanX86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, 79169691Skan StringRef CPU, StringRef FS, 80132720Skan const TargetOptions &Options, 81169691Skan Reloc::Model RM, CodeModel::Model CM, 82169691Skan CodeGenOpt::Level OL, 83132720Skan bool is64Bit) 84132720Skan : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 85132720Skan Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit), 86117397Skan FrameLowering(*this, Subtarget), 87117397Skan InstrItins(Subtarget.getInstrItineraryData()){ 88132720Skan // Determine the PICStyle based on the target selected. 89117397Skan if (getRelocationModel() == Reloc::Static) { 90169691Skan // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 91169691Skan Subtarget.setPICStyle(PICStyles::None); 92117397Skan } else if (Subtarget.is64Bit()) { 93117397Skan // PIC in 64 bit mode is always rip-rel. 94169691Skan Subtarget.setPICStyle(PICStyles::RIPRel); 95169691Skan } else if (Subtarget.isTargetCOFF()) { 96169691Skan Subtarget.setPICStyle(PICStyles::None); 97169691Skan } else if (Subtarget.isTargetDarwin()) { 98169691Skan if (getRelocationModel() == Reloc::PIC_) 99169691Skan Subtarget.setPICStyle(PICStyles::StubPIC); 100169691Skan else { 101117397Skan assert(getRelocationModel() == Reloc::DynamicNoPIC); 102117397Skan Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 103169691Skan } 104117397Skan } else if (Subtarget.isTargetELF()) { 105132720Skan Subtarget.setPICStyle(PICStyles::GOT); 106117397Skan } 107169691Skan 108169691Skan // default to hard float ABI 109117397Skan if (Options.FloatABIType == FloatABI::Default) 110117397Skan this->Options.FloatABIType = FloatABI::Hard; 111117397Skan} 112132720Skan 113132720Skan//===----------------------------------------------------------------------===// 114169691Skan// Command line options for x86 115117397Skan//===----------------------------------------------------------------------===// 116117397Skanstatic cl::opt<bool> 117132720SkanUseVZeroUpper("x86-use-vzeroupper", cl::Hidden, 118117397Skan cl::desc("Minimize AVX to SSE transition penalty"), 119169691Skan cl::init(true)); 120169691Skan 121117397Skan// Temporary option to control early if-conversion for x86 while adding machine 122117397Skan// models. 123169691Skanstatic cl::opt<bool> 124169691SkanX86EarlyIfConv("x86-early-ifcvt", cl::Hidden, 125169691Skan cl::desc("Enable early if-conversion on X86")); 126117397Skan 127117397Skan//===----------------------------------------------------------------------===// 128132720Skan// X86 Analysis Pass Setup 129117397Skan//===----------------------------------------------------------------------===// 130169691Skan 131169691Skanvoid X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) { 132169691Skan // Add first the target-independent BasicTTI pass, then our X86 pass. This 133117397Skan // allows the X86 pass to delegate to the target independent layer when 134117397Skan // appropriate. 135169691Skan PM.add(createBasicTargetTransformInfoPass(this)); 136169691Skan PM.add(createX86TargetTransformInfoPass(this)); 137169691Skan} 138169691Skan 139169691Skan 140169691Skan//===----------------------------------------------------------------------===// 141169691Skan// Pass Pipeline Configuration 142169691Skan//===----------------------------------------------------------------------===// 143169691Skan 144169691Skannamespace { 145169691Skan/// X86 Code Generator Pass Configuration Options. 146169691Skanclass X86PassConfig : public TargetPassConfig { 147169691Skanpublic: 148169691Skan X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) 149169691Skan : TargetPassConfig(TM, PM) {} 150169691Skan 151169691Skan X86TargetMachine &getX86TargetMachine() const { 152169691Skan return getTM<X86TargetMachine>(); 153169691Skan } 154169691Skan 155169691Skan const X86Subtarget &getX86Subtarget() const { 156169691Skan return *getX86TargetMachine().getSubtargetImpl(); 157169691Skan } 158169691Skan 159169691Skan virtual bool addInstSelector(); 160169691Skan virtual bool addILPOpts(); 161169691Skan virtual bool addPreRegAlloc(); 162169691Skan virtual bool addPostRegAlloc(); 163169691Skan virtual bool addPreEmitPass(); 164169691Skan}; 165117397Skan} // namespace 166117397Skan 167132720SkanTargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { 168117397Skan return new X86PassConfig(this, PM); 169117397Skan} 170169691Skan 171117397Skanbool X86PassConfig::addInstSelector() { 172117397Skan // Install an instruction selector. 173117397Skan addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); 174169691Skan 175169691Skan // For ELF, cleanup any local-dynamic TLS accesses. 176169691Skan if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None) 177169691Skan addPass(createCleanupLocalDynamicTLSPass()); 178117397Skan 179169691Skan // For 32-bit, prepend instructions to set the "global base reg" for PIC. 180169691Skan if (!getX86Subtarget().is64Bit()) 181169691Skan addPass(createGlobalBaseRegPass()); 182169691Skan 183169691Skan return false; 184169691Skan} 185169691Skan 186117397Skanbool X86PassConfig::addILPOpts() { 187169691Skan if (X86EarlyIfConv && getX86Subtarget().hasCMov()) { 188117397Skan addPass(&EarlyIfConverterID); 189132720Skan return true; 190169691Skan } 191169691Skan return false; 192169691Skan} 193169691Skan 194169691Skanbool X86PassConfig::addPreRegAlloc() { 195169691Skan return false; // -print-machineinstr shouldn't print after this. 196117397Skan} 197169691Skan 198169691Skanbool X86PassConfig::addPostRegAlloc() { 199169691Skan addPass(createX86FloatingPointStackifierPass()); 200169691Skan return true; // -print-machineinstr should print after this. 201169691Skan} 202169691Skan 203169691Skanbool X86PassConfig::addPreEmitPass() { 204169691Skan bool ShouldPrint = false; 205117397Skan if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { 206169691Skan addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); 207169691Skan ShouldPrint = true; 208169691Skan } 209169691Skan 210169691Skan if (getX86Subtarget().hasAVX() && UseVZeroUpper) { 211169691Skan addPass(createX86IssueVZeroUpperPass()); 212169691Skan ShouldPrint = true; 213117397Skan } 214169691Skan 215169691Skan if (getOptLevel() != CodeGenOpt::None && 216169691Skan getX86Subtarget().padShortFunctions()) { 217169691Skan addPass(createX86PadShortFunctions()); 218169691Skan ShouldPrint = true; 219169691Skan } 220169691Skan if (getOptLevel() != CodeGenOpt::None && 221169691Skan getX86Subtarget().LEAusesAG()){ 222169691Skan addPass(createX86FixupLEAs()); 223169691Skan ShouldPrint = true; 224169691Skan } 225169691Skan 226169691Skan return ShouldPrint; 227169691Skan} 228169691Skan 229169691Skanbool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 230169691Skan JITCodeEmitter &JCE) { 231169691Skan PM.add(createX86JITCodeEmitterPass(*this, JCE)); 232169691Skan 233169691Skan return false; 234169691Skan} 235169691Skan