X86TargetMachine.cpp revision 243830
1287225Simp//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2287225Simp// 3287225Simp// The LLVM Compiler Infrastructure 4287225Simp// 5287225Simp// This file is distributed under the University of Illinois Open Source 6287225Simp// License. See LICENSE.TXT for details. 7287225Simp// 8287225Simp//===----------------------------------------------------------------------===// 9287225Simp// 10287225Simp// This file defines the X86 specific subclass of TargetMachine. 11287225Simp// 12287225Simp//===----------------------------------------------------------------------===// 13287225Simp 14287225Simp#include "X86TargetMachine.h" 15287225Simp#include "X86.h" 16287225Simp#include "llvm/PassManager.h" 17287225Simp#include "llvm/CodeGen/MachineFunction.h" 18287225Simp#include "llvm/CodeGen/Passes.h" 19287225Simp#include "llvm/Support/CommandLine.h" 20287225Simp#include "llvm/Support/FormattedStream.h" 21287225Simp#include "llvm/Target/TargetOptions.h" 22287225Simp#include "llvm/Support/TargetRegistry.h" 23287225Simpusing namespace llvm; 24287225Simp 25287225Simpextern "C" void LLVMInitializeX86Target() { 26287225Simp // Register the target. 27287225Simp RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); 28287225Simp RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); 29287225Simp} 30287225Simp 31287225Simpvoid X86_32TargetMachine::anchor() { } 32287225Simp 33287225SimpX86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, 34287225Simp StringRef CPU, StringRef FS, 35287225Simp const TargetOptions &Options, 36287225Simp Reloc::Model RM, CodeModel::Model CM, 37287225Simp CodeGenOpt::Level OL) 38287225Simp : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 39287225Simp DL(getSubtargetImpl()->isTargetDarwin() ? 40287225Simp "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-" 41287225Simp "n8:16:32-S128" : 42287225Simp (getSubtargetImpl()->isTargetCygMing() || 43287225Simp getSubtargetImpl()->isTargetWindows()) ? 44287225Simp "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-" 45287225Simp "n8:16:32-S32" : 46287225Simp "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-" 47287225Simp "n8:16:32-S128"), 48287225Simp InstrInfo(*this), 49287225Simp TSInfo(*this), 50287225Simp TLInfo(*this), 51287225Simp JITInfo(*this), 52287225Simp STTI(&TLInfo), VTTI(&TLInfo) { 53287225Simp} 54287225Simp 55287225Simpvoid X86_64TargetMachine::anchor() { } 56287225Simp 57287225SimpX86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, 58287225Simp StringRef CPU, StringRef FS, 59287225Simp const TargetOptions &Options, 60287225Simp Reloc::Model RM, CodeModel::Model CM, 61287225Simp CodeGenOpt::Level OL) 62287225Simp : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 63287225Simp DL("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" 64287225Simp "n8:16:32:64-S128"), 65287225Simp InstrInfo(*this), 66287225Simp TSInfo(*this), 67287225Simp TLInfo(*this), 68287225Simp JITInfo(*this), 69287225Simp STTI(&TLInfo), VTTI(&TLInfo){ 70287225Simp} 71287225Simp 72287225Simp/// X86TargetMachine ctor - Create an X86 target. 73287225Simp/// 74287225SimpX86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, 75287225Simp StringRef CPU, StringRef FS, 76287225Simp const TargetOptions &Options, 77287225Simp Reloc::Model RM, CodeModel::Model CM, 78 CodeGenOpt::Level OL, 79 bool is64Bit) 80 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 81 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit), 82 FrameLowering(*this, Subtarget), 83 InstrItins(Subtarget.getInstrItineraryData()){ 84 // Determine the PICStyle based on the target selected. 85 if (getRelocationModel() == Reloc::Static) { 86 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 87 Subtarget.setPICStyle(PICStyles::None); 88 } else if (Subtarget.is64Bit()) { 89 // PIC in 64 bit mode is always rip-rel. 90 Subtarget.setPICStyle(PICStyles::RIPRel); 91 } else if (Subtarget.isTargetCygMing()) { 92 Subtarget.setPICStyle(PICStyles::None); 93 } else if (Subtarget.isTargetDarwin()) { 94 if (getRelocationModel() == Reloc::PIC_) 95 Subtarget.setPICStyle(PICStyles::StubPIC); 96 else { 97 assert(getRelocationModel() == Reloc::DynamicNoPIC); 98 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 99 } 100 } else if (Subtarget.isTargetELF()) { 101 Subtarget.setPICStyle(PICStyles::GOT); 102 } 103 104 // default to hard float ABI 105 if (Options.FloatABIType == FloatABI::Default) 106 this->Options.FloatABIType = FloatABI::Hard; 107} 108 109//===----------------------------------------------------------------------===// 110// Command line options for x86 111//===----------------------------------------------------------------------===// 112static cl::opt<bool> 113UseVZeroUpper("x86-use-vzeroupper", 114 cl::desc("Minimize AVX to SSE transition penalty"), 115 cl::init(true)); 116 117// Temporary option to control early if-conversion for x86 while adding machine 118// models. 119static cl::opt<bool> 120X86EarlyIfConv("x86-early-ifcvt", 121 cl::desc("Enable early if-conversion on X86")); 122 123//===----------------------------------------------------------------------===// 124// Pass Pipeline Configuration 125//===----------------------------------------------------------------------===// 126 127namespace { 128/// X86 Code Generator Pass Configuration Options. 129class X86PassConfig : public TargetPassConfig { 130public: 131 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) 132 : TargetPassConfig(TM, PM) {} 133 134 X86TargetMachine &getX86TargetMachine() const { 135 return getTM<X86TargetMachine>(); 136 } 137 138 const X86Subtarget &getX86Subtarget() const { 139 return *getX86TargetMachine().getSubtargetImpl(); 140 } 141 142 virtual bool addInstSelector(); 143 virtual bool addPreRegAlloc(); 144 virtual bool addPostRegAlloc(); 145 virtual bool addPreEmitPass(); 146}; 147} // namespace 148 149TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { 150 X86PassConfig *PC = new X86PassConfig(this, PM); 151 152 if (X86EarlyIfConv && Subtarget.hasCMov()) 153 PC->enablePass(&EarlyIfConverterID); 154 155 return PC; 156} 157 158bool X86PassConfig::addInstSelector() { 159 // Install an instruction selector. 160 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); 161 162 // For ELF, cleanup any local-dynamic TLS accesses. 163 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None) 164 addPass(createCleanupLocalDynamicTLSPass()); 165 166 // For 32-bit, prepend instructions to set the "global base reg" for PIC. 167 if (!getX86Subtarget().is64Bit()) 168 addPass(createGlobalBaseRegPass()); 169 170 return false; 171} 172 173bool X86PassConfig::addPreRegAlloc() { 174 addPass(createX86MaxStackAlignmentHeuristicPass()); 175 return false; // -print-machineinstr shouldn't print after this. 176} 177 178bool X86PassConfig::addPostRegAlloc() { 179 addPass(createX86FloatingPointStackifierPass()); 180 return true; // -print-machineinstr should print after this. 181} 182 183bool X86PassConfig::addPreEmitPass() { 184 bool ShouldPrint = false; 185 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { 186 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); 187 ShouldPrint = true; 188 } 189 190 if (getX86Subtarget().hasAVX() && UseVZeroUpper) { 191 addPass(createX86IssueVZeroUpperPass()); 192 ShouldPrint = true; 193 } 194 195 return ShouldPrint; 196} 197 198bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 199 JITCodeEmitter &JCE) { 200 PM.add(createX86JITCodeEmitterPass(*this, JCE)); 201 202 return false; 203} 204