X86ISelLowering.h revision 206124
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26 27namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 61 /// integer source in memory and FP reg result. This corresponds to the 62 /// X86::FILD*m instructions. It has three inputs (token chain, address, 63 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 64 /// also produces a flag). 65 FILD, 66 FILD_FLAG, 67 68 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 69 /// integer destination in memory and a FP reg source. This corresponds 70 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 71 /// has two inputs (token chain and address) and two outputs (int value 72 /// and token chain). 73 FP_TO_INT16_IN_MEM, 74 FP_TO_INT32_IN_MEM, 75 FP_TO_INT64_IN_MEM, 76 77 /// FLD - This instruction implements an extending load to FP stack slots. 78 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 79 /// operand, ptr to load from, and a ValueType node indicating the type 80 /// to load to. 81 FLD, 82 83 /// FST - This instruction implements a truncating store to FP stack 84 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 85 /// chain operand, value to store, address, and a ValueType to store it 86 /// as. 87 FST, 88 89 /// CALL - These operations represent an abstract X86 call 90 /// instruction, which includes a bunch of information. In particular the 91 /// operands of these node are: 92 /// 93 /// #0 - The incoming token chain 94 /// #1 - The callee 95 /// #2 - The number of arg bytes the caller pushes on the stack. 96 /// #3 - The number of arg bytes the callee pops off the stack. 97 /// #4 - The value to pass in AL/AX/EAX (optional) 98 /// #5 - The value to pass in DL/DX/EDX (optional) 99 /// 100 /// The result values of these nodes are: 101 /// 102 /// #0 - The outgoing token chain 103 /// #1 - The first register result value (optional) 104 /// #2 - The second register result value (optional) 105 /// 106 CALL, 107 108 /// RDTSC_DAG - This operation implements the lowering for 109 /// readcyclecounter 110 RDTSC_DAG, 111 112 /// X86 compare and logical compare instructions. 113 CMP, COMI, UCOMI, 114 115 /// X86 bit-test instructions. 116 BT, 117 118 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 119 /// operand produced by a CMP instruction. 120 SETCC, 121 122 // Same as SETCC except it's materialized with a sbb and the value is all 123 // one's or all zero's. 124 SETCC_CARRY, 125 126 /// X86 conditional moves. Operand 0 and operand 1 are the two values 127 /// to select from. Operand 2 is the condition code, and operand 3 is the 128 /// flag operand produced by a CMP or TEST instruction. It also writes a 129 /// flag result. 130 CMOV, 131 132 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 133 /// is the block to branch if condition is true, operand 2 is the 134 /// condition code, and operand 3 is the flag operand produced by a CMP 135 /// or TEST instruction. 136 BRCOND, 137 138 /// Return with a flag operand. Operand 0 is the chain operand, operand 139 /// 1 is the number of bytes of stack to pop. 140 RET_FLAG, 141 142 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 143 REP_STOS, 144 145 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 146 REP_MOVS, 147 148 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 149 /// at function entry, used for PIC code. 150 GlobalBaseReg, 151 152 /// Wrapper - A wrapper node for TargetConstantPool, 153 /// TargetExternalSymbol, and TargetGlobalAddress. 154 Wrapper, 155 156 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 157 /// relative displacements. 158 WrapperRIP, 159 160 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector. 161 /// Can be used to move a vector value from a MMX register to a XMM 162 /// register. 163 MOVQ2DQ, 164 165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 166 /// i32, corresponds to X86::PEXTRB. 167 PEXTRB, 168 169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 170 /// i32, corresponds to X86::PEXTRW. 171 PEXTRW, 172 173 /// INSERTPS - Insert any element of a 4 x float vector into any element 174 /// of a destination 4 x floatvector. 175 INSERTPS, 176 177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 178 /// corresponds to X86::PINSRB. 179 PINSRB, 180 181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 182 /// corresponds to X86::PINSRW. 183 PINSRW, MMX_PINSRW, 184 185 /// PSHUFB - Shuffle 16 8-bit values within a vector. 186 PSHUFB, 187 188 /// FMAX, FMIN - Floating point max and min. 189 /// 190 FMAX, FMIN, 191 192 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 193 /// approximation. Note that these typically require refinement 194 /// in order to obtain suitable precision. 195 FRSQRT, FRCP, 196 197 // TLSADDR - Thread Local Storage. 198 TLSADDR, 199 200 // SegmentBaseAddress - The address segment:0 201 SegmentBaseAddress, 202 203 // EH_RETURN - Exception Handling helpers. 204 EH_RETURN, 205 206 /// TC_RETURN - Tail call return. 207 /// operand #0 chain 208 /// operand #1 callee (register or absolute) 209 /// operand #2 stack adjustment 210 /// operand #3 optional in flag 211 TC_RETURN, 212 213 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 214 LCMPXCHG_DAG, 215 LCMPXCHG8_DAG, 216 217 // FNSTCW16m - Store FP control world into i16 memory. 218 FNSTCW16m, 219 220 // VZEXT_MOVL - Vector move low and zero extend. 221 VZEXT_MOVL, 222 223 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 224 VZEXT_LOAD, 225 226 // VSHL, VSRL - Vector logical left / right shift. 227 VSHL, VSRL, 228 229 // CMPPD, CMPPS - Vector double/float comparison. 230 // CMPPD, CMPPS - Vector double/float comparison. 231 CMPPD, CMPPS, 232 233 // PCMP* - Vector integer comparisons. 234 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 235 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 236 237 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 238 ADD, SUB, SMUL, UMUL, 239 INC, DEC, OR, XOR, AND, 240 241 // MUL_IMM - X86 specific multiply by immediate. 242 MUL_IMM, 243 244 // PTEST - Vector bitwise comparisons 245 PTEST, 246 247 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 248 // according to %al. An operator is needed so that this can be expanded 249 // with control flow. 250 VASTART_SAVE_XMM_REGS, 251 252 // MINGW_ALLOCA - MingW's __alloca call to do stack probing. 253 MINGW_ALLOCA, 254 255 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 256 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 257 // Atomic 64-bit binary operations. 258 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 259 ATOMSUB64_DAG, 260 ATOMOR64_DAG, 261 ATOMXOR64_DAG, 262 ATOMAND64_DAG, 263 ATOMNAND64_DAG, 264 ATOMSWAP64_DAG 265 266 // WARNING: Do not add anything in the end unless you want the node to 267 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 268 // thought as target memory ops! 269 }; 270 } 271 272 /// Define some predicates that are used for node matching. 273 namespace X86 { 274 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 275 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 276 bool isPSHUFDMask(ShuffleVectorSDNode *N); 277 278 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 279 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 280 bool isPSHUFHWMask(ShuffleVectorSDNode *N); 281 282 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 283 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 284 bool isPSHUFLWMask(ShuffleVectorSDNode *N); 285 286 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 287 /// specifies a shuffle of elements that is suitable for input to SHUFP*. 288 bool isSHUFPMask(ShuffleVectorSDNode *N); 289 290 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 291 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 292 bool isMOVHLPSMask(ShuffleVectorSDNode *N); 293 294 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 295 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 296 /// <2, 3, 2, 3> 297 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 298 299 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 300 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 301 bool isMOVLPMask(ShuffleVectorSDNode *N); 302 303 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 304 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 305 /// as well as MOVLHPS. 306 bool isMOVLHPSMask(ShuffleVectorSDNode *N); 307 308 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 309 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 310 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 311 312 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 313 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 314 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 315 316 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 317 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 318 /// <0, 0, 1, 1> 319 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 320 321 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 322 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 323 /// <2, 2, 3, 3> 324 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 325 326 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 327 /// specifies a shuffle of elements that is suitable for input to MOVSS, 328 /// MOVSD, and MOVD, i.e. setting the lowest element. 329 bool isMOVLMask(ShuffleVectorSDNode *N); 330 331 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 332 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 333 bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 334 335 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 336 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 337 bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 338 339 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 340 /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 341 bool isMOVDDUPMask(ShuffleVectorSDNode *N); 342 343 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 344 /// specifies a shuffle of elements that is suitable for input to PALIGNR. 345 bool isPALIGNRMask(ShuffleVectorSDNode *N); 346 347 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 348 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 349 /// instructions. 350 unsigned getShuffleSHUFImmediate(SDNode *N); 351 352 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 353 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 354 unsigned getShufflePSHUFHWImmediate(SDNode *N); 355 356 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 357 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 358 unsigned getShufflePSHUFLWImmediate(SDNode *N); 359 360 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 361 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 362 unsigned getShufflePALIGNRImmediate(SDNode *N); 363 364 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 365 /// constant +0.0. 366 bool isZeroNode(SDValue Elt); 367 368 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 369 /// fit into displacement field of the instruction. 370 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 371 bool hasSymbolicDisplacement = true); 372 } 373 374 //===--------------------------------------------------------------------===// 375 // X86TargetLowering - X86 Implementation of the TargetLowering interface 376 class X86TargetLowering : public TargetLowering { 377 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 378 int RegSaveFrameIndex; // X86-64 vararg func register save area. 379 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. 380 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. 381 int BytesToPopOnReturn; // Number of arg bytes ret should pop. 382 383 public: 384 explicit X86TargetLowering(X86TargetMachine &TM); 385 386 /// getPICBaseSymbol - Return the X86-32 PIC base. 387 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const; 388 389 virtual unsigned getJumpTableEncoding() const; 390 391 virtual const MCExpr * 392 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 393 const MachineBasicBlock *MBB, unsigned uid, 394 MCContext &Ctx) const; 395 396 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 397 /// jumptable. 398 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 399 SelectionDAG &DAG) const; 400 virtual const MCExpr * 401 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 402 unsigned JTI, MCContext &Ctx) const; 403 404 // Return the number of bytes that a function should pop when it returns (in 405 // addition to the space used by the return address). 406 // 407 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } 408 409 /// getStackPtrReg - Return the stack pointer register we are using: either 410 /// ESP or RSP. 411 unsigned getStackPtrReg() const { return X86StackPtr; } 412 413 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 414 /// function arguments in the caller parameter area. For X86, aggregates 415 /// that contains are placed at 16-byte boundaries while the rest are at 416 /// 4-byte boundaries. 417 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 418 419 /// getOptimalMemOpType - Returns the target specific optimal type for load 420 /// and store operations as a result of memset, memcpy, and memmove 421 /// lowering. If DstAlign is zero that means it's safe to destination 422 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 423 /// means there isn't a need to check it against alignment requirement, 424 /// probably because the source does not need to be loaded. If 425 /// 'NonScalarIntSafe' is true, that means it's safe to return a 426 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 427 /// from memory. It returns EVT::Other if SelectionDAG should be responsible 428 /// for determining it. 429 virtual EVT 430 getOptimalMemOpType(uint64_t Size, 431 unsigned DstAlign, unsigned SrcAlign, 432 bool NonScalarIntSafe, SelectionDAG &DAG) const; 433 434 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 435 /// unaligned memory accesses. of the specified type. 436 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 437 return true; 438 } 439 440 /// LowerOperation - Provide custom lowering hooks for some operations. 441 /// 442 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 443 444 /// ReplaceNodeResults - Replace the results of node with an illegal result 445 /// type with new values built out of custom code. 446 /// 447 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 448 SelectionDAG &DAG); 449 450 451 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 452 453 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 454 MachineBasicBlock *MBB, 455 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 456 457 458 /// getTargetNodeName - This method returns the name of a target specific 459 /// DAG node. 460 virtual const char *getTargetNodeName(unsigned Opcode) const; 461 462 /// getSetCCResultType - Return the ISD::SETCC ValueType 463 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 464 465 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 466 /// in Mask are known to be either zero or one and return them in the 467 /// KnownZero/KnownOne bitsets. 468 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 469 const APInt &Mask, 470 APInt &KnownZero, 471 APInt &KnownOne, 472 const SelectionDAG &DAG, 473 unsigned Depth = 0) const; 474 475 virtual bool 476 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 477 478 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); 479 480 virtual bool ExpandInlineAsm(CallInst *CI) const; 481 482 ConstraintType getConstraintType(const std::string &Constraint) const; 483 484 std::vector<unsigned> 485 getRegClassForInlineAsmConstraint(const std::string &Constraint, 486 EVT VT) const; 487 488 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 489 490 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 491 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 492 /// true it means one of the asm constraint of the inline asm instruction 493 /// being processed is 'm'. 494 virtual void LowerAsmOperandForConstraint(SDValue Op, 495 char ConstraintLetter, 496 bool hasMemory, 497 std::vector<SDValue> &Ops, 498 SelectionDAG &DAG) const; 499 500 /// getRegForInlineAsmConstraint - Given a physical register constraint 501 /// (e.g. {edx}), return the register number and the register class for the 502 /// register. This should only be used for C_Register constraints. On 503 /// error, this returns a register number of 0. 504 std::pair<unsigned, const TargetRegisterClass*> 505 getRegForInlineAsmConstraint(const std::string &Constraint, 506 EVT VT) const; 507 508 /// isLegalAddressingMode - Return true if the addressing mode represented 509 /// by AM is legal for this target, for a load/store of the specified type. 510 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 511 512 /// isTruncateFree - Return true if it's free to truncate a value of 513 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 514 /// register EAX to i16 by referencing its sub-register AX. 515 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 516 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 517 518 /// isZExtFree - Return true if any actual instruction that defines a 519 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 520 /// register. This does not necessarily include registers defined in 521 /// unknown ways, such as incoming arguments, or copies from unknown 522 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 523 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 524 /// all instructions that define 32-bit values implicit zero-extend the 525 /// result out to 64 bits. 526 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 527 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 528 529 /// isNarrowingProfitable - Return true if it's profitable to narrow 530 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 531 /// from i32 to i8 but not from i32 to i16. 532 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 533 534 /// isFPImmLegal - Returns true if the target can instruction select the 535 /// specified FP immediate natively. If false, the legalizer will 536 /// materialize the FP immediate as a load from a constant pool. 537 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 538 539 /// isShuffleMaskLegal - Targets can use this to indicate that they only 540 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 541 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 542 /// values are assumed to be legal. 543 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 544 EVT VT) const; 545 546 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 547 /// used by Targets can use this to indicate if there is a suitable 548 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 549 /// pool entry. 550 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 551 EVT VT) const; 552 553 /// ShouldShrinkFPConstant - If true, then instruction selection should 554 /// seek to shrink the FP constant of the specified type to a smaller type 555 /// in order to save space and / or reduce runtime. 556 virtual bool ShouldShrinkFPConstant(EVT VT) const { 557 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 558 // expensive than a straight movsd. On the other hand, it's important to 559 // shrink long double fp constant since fldt is very slow. 560 return !X86ScalarSSEf64 || VT == MVT::f80; 561 } 562 563 virtual const X86Subtarget* getSubtarget() { 564 return Subtarget; 565 } 566 567 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 568 /// computed in an SSE register, not on the X87 floating point stack. 569 bool isScalarFPTypeInSSEReg(EVT VT) const { 570 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 571 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 572 } 573 574 /// createFastISel - This method returns a target specific FastISel object, 575 /// or null if the target does not support "fast" ISel. 576 virtual FastISel * 577 createFastISel(MachineFunction &mf, 578 MachineModuleInfo *mmi, DwarfWriter *dw, 579 DenseMap<const Value *, unsigned> &, 580 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 581 DenseMap<const AllocaInst *, int> & 582#ifndef NDEBUG 583 , SmallSet<Instruction*, 8> & 584#endif 585 ); 586 587 /// getFunctionAlignment - Return the Log2 alignment of this function. 588 virtual unsigned getFunctionAlignment(const Function *F) const; 589 590 private: 591 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 592 /// make the right decision when generating code for different targets. 593 const X86Subtarget *Subtarget; 594 const X86RegisterInfo *RegInfo; 595 const TargetData *TD; 596 597 /// X86StackPtr - X86 physical register used as stack ptr. 598 unsigned X86StackPtr; 599 600 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 601 /// floating point ops. 602 /// When SSE is available, use it for f32 operations. 603 /// When SSE2 is available, use it for f64 operations. 604 bool X86ScalarSSEf32; 605 bool X86ScalarSSEf64; 606 607 /// LegalFPImmediates - A list of legal fp immediates. 608 std::vector<APFloat> LegalFPImmediates; 609 610 /// addLegalFPImmediate - Indicate that this x86 target can instruction 611 /// select the specified FP immediate natively. 612 void addLegalFPImmediate(const APFloat& Imm) { 613 LegalFPImmediates.push_back(Imm); 614 } 615 616 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 617 CallingConv::ID CallConv, bool isVarArg, 618 const SmallVectorImpl<ISD::InputArg> &Ins, 619 DebugLoc dl, SelectionDAG &DAG, 620 SmallVectorImpl<SDValue> &InVals); 621 SDValue LowerMemArgument(SDValue Chain, 622 CallingConv::ID CallConv, 623 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 624 DebugLoc dl, SelectionDAG &DAG, 625 const CCValAssign &VA, MachineFrameInfo *MFI, 626 unsigned i); 627 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 628 DebugLoc dl, SelectionDAG &DAG, 629 const CCValAssign &VA, 630 ISD::ArgFlagsTy Flags); 631 632 // Call lowering helpers. 633 634 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 635 /// for tail call optimization. Targets which want to do tail call 636 /// optimization should implement this function. 637 bool IsEligibleForTailCallOptimization(SDValue Callee, 638 CallingConv::ID CalleeCC, 639 bool isVarArg, 640 bool isCalleeStructRet, 641 bool isCallerStructRet, 642 const SmallVectorImpl<ISD::OutputArg> &Outs, 643 const SmallVectorImpl<ISD::InputArg> &Ins, 644 SelectionDAG& DAG) const; 645 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); 646 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 647 SDValue Chain, bool IsTailCall, bool Is64Bit, 648 int FPDiff, DebugLoc dl); 649 650 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 651 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); 652 653 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 654 bool isSigned); 655 656 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 657 SelectionDAG &DAG); 658 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 659 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG); 660 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 661 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 662 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 663 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 664 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 665 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 666 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 667 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 668 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 669 int64_t Offset, SelectionDAG &DAG) const; 670 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 671 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 672 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); 673 SDValue LowerShift(SDValue Op, SelectionDAG &DAG); 674 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 675 SelectionDAG &DAG); 676 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 677 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); 678 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); 679 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); 680 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 681 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); 682 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); 683 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); 684 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); 685 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 686 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); 687 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); 688 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); 689 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); 690 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 691 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 692 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); 693 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); 694 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); 695 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 696 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 697 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 698 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); 699 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); 700 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 701 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 702 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); 703 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); 704 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); 705 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); 706 707 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); 708 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); 709 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); 710 711 virtual SDValue 712 LowerFormalArguments(SDValue Chain, 713 CallingConv::ID CallConv, bool isVarArg, 714 const SmallVectorImpl<ISD::InputArg> &Ins, 715 DebugLoc dl, SelectionDAG &DAG, 716 SmallVectorImpl<SDValue> &InVals); 717 virtual SDValue 718 LowerCall(SDValue Chain, SDValue Callee, 719 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 720 const SmallVectorImpl<ISD::OutputArg> &Outs, 721 const SmallVectorImpl<ISD::InputArg> &Ins, 722 DebugLoc dl, SelectionDAG &DAG, 723 SmallVectorImpl<SDValue> &InVals); 724 725 virtual SDValue 726 LowerReturn(SDValue Chain, 727 CallingConv::ID CallConv, bool isVarArg, 728 const SmallVectorImpl<ISD::OutputArg> &Outs, 729 DebugLoc dl, SelectionDAG &DAG); 730 731 virtual bool 732 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 733 const SmallVectorImpl<EVT> &OutTys, 734 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 735 SelectionDAG &DAG); 736 737 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 738 SelectionDAG &DAG, unsigned NewOp); 739 740 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 741 SDValue Chain, 742 SDValue Dst, SDValue Src, 743 SDValue Size, unsigned Align, 744 const Value *DstSV, uint64_t DstSVOff); 745 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 746 SDValue Chain, 747 SDValue Dst, SDValue Src, 748 SDValue Size, unsigned Align, 749 bool AlwaysInline, 750 const Value *DstSV, uint64_t DstSVOff, 751 const Value *SrcSV, uint64_t SrcSVOff); 752 753 /// Utility function to emit string processing sse4.2 instructions 754 /// that return in xmm0. 755 /// This takes the instruction to expand, the associated machine basic 756 /// block, the number of args, and whether or not the second arg is 757 /// in memory or not. 758 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 759 unsigned argNum, bool inMem) const; 760 761 /// Utility function to emit atomic bitwise operations (and, or, xor). 762 /// It takes the bitwise instruction to expand, the associated machine basic 763 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 764 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 765 MachineInstr *BInstr, 766 MachineBasicBlock *BB, 767 unsigned regOpc, 768 unsigned immOpc, 769 unsigned loadOpc, 770 unsigned cxchgOpc, 771 unsigned copyOpc, 772 unsigned notOpc, 773 unsigned EAXreg, 774 TargetRegisterClass *RC, 775 bool invSrc = false) const; 776 777 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 778 MachineInstr *BInstr, 779 MachineBasicBlock *BB, 780 unsigned regOpcL, 781 unsigned regOpcH, 782 unsigned immOpcL, 783 unsigned immOpcH, 784 bool invSrc = false) const; 785 786 /// Utility function to emit atomic min and max. It takes the min/max 787 /// instruction to expand, the associated basic block, and the associated 788 /// cmov opcode for moving the min or max value. 789 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 790 MachineBasicBlock *BB, 791 unsigned cmovOpc) const; 792 793 /// Utility function to emit the xmm reg save portion of va_start. 794 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 795 MachineInstr *BInstr, 796 MachineBasicBlock *BB) const; 797 798 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 799 MachineBasicBlock *BB, 800 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 801 802 MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI, 803 MachineBasicBlock *BB, 804 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 805 806 /// Emit nodes that will be selected as "test Op0,Op0", or something 807 /// equivalent, for use with the given x86 condition code. 808 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); 809 810 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 811 /// equivalent, for use with the given x86 condition code. 812 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 813 SelectionDAG &DAG); 814 }; 815 816 namespace X86 { 817 FastISel *createFastISel(MachineFunction &mf, 818 MachineModuleInfo *mmi, DwarfWriter *dw, 819 DenseMap<const Value *, unsigned> &, 820 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 821 DenseMap<const AllocaInst *, int> & 822#ifndef NDEBUG 823 , SmallSet<Instruction*, 8> & 824#endif 825 ); 826 } 827} 828 829#endif // X86ISELLOWERING_H 830