X86ISelLowering.h revision 200581
1193323Sed//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the interfaces that X86 uses to lower LLVM code into a 11193323Sed// selection DAG. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef X86ISELLOWERING_H 16193323Sed#define X86ISELLOWERING_H 17193323Sed 18193323Sed#include "X86Subtarget.h" 19193323Sed#include "X86RegisterInfo.h" 20193323Sed#include "X86MachineFunctionInfo.h" 21193323Sed#include "llvm/Target/TargetLowering.h" 22193323Sed#include "llvm/CodeGen/FastISel.h" 23193323Sed#include "llvm/CodeGen/SelectionDAG.h" 24193323Sed#include "llvm/CodeGen/CallingConvLower.h" 25193323Sed 26193323Sednamespace llvm { 27193323Sed namespace X86ISD { 28193323Sed // X86 Specific DAG Nodes 29193323Sed enum NodeType { 30193323Sed // Start the numbering where the builtin ops leave off. 31193323Sed FIRST_NUMBER = ISD::BUILTIN_OP_END, 32193323Sed 33193323Sed /// BSF - Bit scan forward. 34193323Sed /// BSR - Bit scan reverse. 35193323Sed BSF, 36193323Sed BSR, 37193323Sed 38193323Sed /// SHLD, SHRD - Double shift instructions. These correspond to 39193323Sed /// X86::SHLDxx and X86::SHRDxx instructions. 40193323Sed SHLD, 41193323Sed SHRD, 42193323Sed 43193323Sed /// FAND - Bitwise logical AND of floating point values. This corresponds 44193323Sed /// to X86::ANDPS or X86::ANDPD. 45193323Sed FAND, 46193323Sed 47193323Sed /// FOR - Bitwise logical OR of floating point values. This corresponds 48193323Sed /// to X86::ORPS or X86::ORPD. 49193323Sed FOR, 50193323Sed 51193323Sed /// FXOR - Bitwise logical XOR of floating point values. This corresponds 52193323Sed /// to X86::XORPS or X86::XORPD. 53193323Sed FXOR, 54193323Sed 55193323Sed /// FSRL - Bitwise logical right shift of floating point values. These 56193323Sed /// corresponds to X86::PSRLDQ. 57193323Sed FSRL, 58193323Sed 59193323Sed /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 60193323Sed /// integer source in memory and FP reg result. This corresponds to the 61193323Sed /// X86::FILD*m instructions. It has three inputs (token chain, address, 62193323Sed /// and source type) and two outputs (FP value and token chain). FILD_FLAG 63193323Sed /// also produces a flag). 64193323Sed FILD, 65193323Sed FILD_FLAG, 66193323Sed 67193323Sed /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 68193323Sed /// integer destination in memory and a FP reg source. This corresponds 69193323Sed /// to the X86::FIST*m instructions and the rounding mode change stuff. It 70193323Sed /// has two inputs (token chain and address) and two outputs (int value 71193323Sed /// and token chain). 72193323Sed FP_TO_INT16_IN_MEM, 73193323Sed FP_TO_INT32_IN_MEM, 74193323Sed FP_TO_INT64_IN_MEM, 75193323Sed 76193323Sed /// FLD - This instruction implements an extending load to FP stack slots. 77193323Sed /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 78193323Sed /// operand, ptr to load from, and a ValueType node indicating the type 79193323Sed /// to load to. 80193323Sed FLD, 81193323Sed 82193323Sed /// FST - This instruction implements a truncating store to FP stack 83193323Sed /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 84193323Sed /// chain operand, value to store, address, and a ValueType to store it 85193323Sed /// as. 86193323Sed FST, 87193323Sed 88198090Srdivacky /// CALL - These operations represent an abstract X86 call 89193323Sed /// instruction, which includes a bunch of information. In particular the 90193323Sed /// operands of these node are: 91193323Sed /// 92193323Sed /// #0 - The incoming token chain 93193323Sed /// #1 - The callee 94193323Sed /// #2 - The number of arg bytes the caller pushes on the stack. 95193323Sed /// #3 - The number of arg bytes the callee pops off the stack. 96193323Sed /// #4 - The value to pass in AL/AX/EAX (optional) 97193323Sed /// #5 - The value to pass in DL/DX/EDX (optional) 98193323Sed /// 99193323Sed /// The result values of these nodes are: 100193323Sed /// 101193323Sed /// #0 - The outgoing token chain 102193323Sed /// #1 - The first register result value (optional) 103193323Sed /// #2 - The second register result value (optional) 104193323Sed /// 105193323Sed CALL, 106198090Srdivacky 107193323Sed /// RDTSC_DAG - This operation implements the lowering for 108193323Sed /// readcyclecounter 109193323Sed RDTSC_DAG, 110193323Sed 111193323Sed /// X86 compare and logical compare instructions. 112193323Sed CMP, COMI, UCOMI, 113193323Sed 114193323Sed /// X86 bit-test instructions. 115193323Sed BT, 116193323Sed 117193323Sed /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 118193323Sed /// operand produced by a CMP instruction. 119193323Sed SETCC, 120193323Sed 121200581Srdivacky // Same as SETCC except it's materialized with a sbb and the value is all 122200581Srdivacky // one's or all zero's. 123200581Srdivacky SETCC_CARRY, 124200581Srdivacky 125193323Sed /// X86 conditional moves. Operand 0 and operand 1 are the two values 126193323Sed /// to select from. Operand 2 is the condition code, and operand 3 is the 127193323Sed /// flag operand produced by a CMP or TEST instruction. It also writes a 128193323Sed /// flag result. 129193323Sed CMOV, 130193323Sed 131193323Sed /// X86 conditional branches. Operand 0 is the chain operand, operand 1 132193323Sed /// is the block to branch if condition is true, operand 2 is the 133193323Sed /// condition code, and operand 3 is the flag operand produced by a CMP 134193323Sed /// or TEST instruction. 135193323Sed BRCOND, 136193323Sed 137193323Sed /// Return with a flag operand. Operand 0 is the chain operand, operand 138193323Sed /// 1 is the number of bytes of stack to pop. 139193323Sed RET_FLAG, 140193323Sed 141193323Sed /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 142193323Sed REP_STOS, 143193323Sed 144193323Sed /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 145193323Sed REP_MOVS, 146193323Sed 147193323Sed /// GlobalBaseReg - On Darwin, this node represents the result of the popl 148193323Sed /// at function entry, used for PIC code. 149193323Sed GlobalBaseReg, 150193323Sed 151193323Sed /// Wrapper - A wrapper node for TargetConstantPool, 152193323Sed /// TargetExternalSymbol, and TargetGlobalAddress. 153193323Sed Wrapper, 154193323Sed 155193323Sed /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 156193323Sed /// relative displacements. 157193323Sed WrapperRIP, 158193323Sed 159193323Sed /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 160193323Sed /// i32, corresponds to X86::PEXTRB. 161193323Sed PEXTRB, 162193323Sed 163193323Sed /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 164193323Sed /// i32, corresponds to X86::PEXTRW. 165193323Sed PEXTRW, 166193323Sed 167193323Sed /// INSERTPS - Insert any element of a 4 x float vector into any element 168193323Sed /// of a destination 4 x floatvector. 169193323Sed INSERTPS, 170193323Sed 171193323Sed /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 172193323Sed /// corresponds to X86::PINSRB. 173193323Sed PINSRB, 174193323Sed 175193323Sed /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 176193323Sed /// corresponds to X86::PINSRW. 177193323Sed PINSRW, 178193323Sed 179193323Sed /// PSHUFB - Shuffle 16 8-bit values within a vector. 180193323Sed PSHUFB, 181193323Sed 182193323Sed /// FMAX, FMIN - Floating point max and min. 183193323Sed /// 184193323Sed FMAX, FMIN, 185193323Sed 186193323Sed /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 187193323Sed /// approximation. Note that these typically require refinement 188193323Sed /// in order to obtain suitable precision. 189193323Sed FRSQRT, FRCP, 190193323Sed 191193323Sed // TLSADDR - Thread Local Storage. 192193323Sed TLSADDR, 193193323Sed 194193323Sed // SegmentBaseAddress - The address segment:0 195193323Sed SegmentBaseAddress, 196193323Sed 197193323Sed // EH_RETURN - Exception Handling helpers. 198193323Sed EH_RETURN, 199193323Sed 200193323Sed /// TC_RETURN - Tail call return. 201193323Sed /// operand #0 chain 202193323Sed /// operand #1 callee (register or absolute) 203193323Sed /// operand #2 stack adjustment 204193323Sed /// operand #3 optional in flag 205193323Sed TC_RETURN, 206193323Sed 207193323Sed // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 208193323Sed LCMPXCHG_DAG, 209193323Sed LCMPXCHG8_DAG, 210193323Sed 211193323Sed // FNSTCW16m - Store FP control world into i16 memory. 212193323Sed FNSTCW16m, 213193323Sed 214193323Sed // VZEXT_MOVL - Vector move low and zero extend. 215193323Sed VZEXT_MOVL, 216193323Sed 217193323Sed // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 218193323Sed VZEXT_LOAD, 219193323Sed 220193323Sed // VSHL, VSRL - Vector logical left / right shift. 221193323Sed VSHL, VSRL, 222193323Sed 223193323Sed // CMPPD, CMPPS - Vector double/float comparison. 224193323Sed // CMPPD, CMPPS - Vector double/float comparison. 225193323Sed CMPPD, CMPPS, 226193323Sed 227193323Sed // PCMP* - Vector integer comparisons. 228193323Sed PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 229193323Sed PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 230193323Sed 231193323Sed // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 232193323Sed ADD, SUB, SMUL, UMUL, 233198090Srdivacky INC, DEC, OR, XOR, AND, 234193323Sed 235193323Sed // MUL_IMM - X86 specific multiply by immediate. 236198090Srdivacky MUL_IMM, 237198090Srdivacky 238198090Srdivacky // PTEST - Vector bitwise comparisons 239198090Srdivacky PTEST, 240198090Srdivacky 241198090Srdivacky // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 242198090Srdivacky // according to %al. An operator is needed so that this can be expanded 243198090Srdivacky // with control flow. 244198090Srdivacky VASTART_SAVE_XMM_REGS, 245198090Srdivacky 246198090Srdivacky // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 247198090Srdivacky // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 248198090Srdivacky // Atomic 64-bit binary operations. 249198090Srdivacky ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 250198090Srdivacky ATOMSUB64_DAG, 251198090Srdivacky ATOMOR64_DAG, 252198090Srdivacky ATOMXOR64_DAG, 253198090Srdivacky ATOMAND64_DAG, 254198090Srdivacky ATOMNAND64_DAG, 255198090Srdivacky ATOMSWAP64_DAG 256193323Sed }; 257193323Sed } 258193323Sed 259193323Sed /// Define some predicates that are used for node matching. 260193323Sed namespace X86 { 261193323Sed /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 262193323Sed /// specifies a shuffle of elements that is suitable for input to PSHUFD. 263193323Sed bool isPSHUFDMask(ShuffleVectorSDNode *N); 264193323Sed 265193323Sed /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 266193323Sed /// specifies a shuffle of elements that is suitable for input to PSHUFD. 267193323Sed bool isPSHUFHWMask(ShuffleVectorSDNode *N); 268193323Sed 269193323Sed /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 270193323Sed /// specifies a shuffle of elements that is suitable for input to PSHUFD. 271193323Sed bool isPSHUFLWMask(ShuffleVectorSDNode *N); 272193323Sed 273193323Sed /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 274193323Sed /// specifies a shuffle of elements that is suitable for input to SHUFP*. 275193323Sed bool isSHUFPMask(ShuffleVectorSDNode *N); 276193323Sed 277193323Sed /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 278193323Sed /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 279193323Sed bool isMOVHLPSMask(ShuffleVectorSDNode *N); 280193323Sed 281193323Sed /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 282193323Sed /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 283193323Sed /// <2, 3, 2, 3> 284193323Sed bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 285193323Sed 286193323Sed /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 287193323Sed /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 288193323Sed bool isMOVLPMask(ShuffleVectorSDNode *N); 289193323Sed 290193323Sed /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 291193323Sed /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 292193323Sed /// as well as MOVLHPS. 293199481Srdivacky bool isMOVLHPSMask(ShuffleVectorSDNode *N); 294193323Sed 295193323Sed /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 296193323Sed /// specifies a shuffle of elements that is suitable for input to UNPCKL. 297193323Sed bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 298193323Sed 299193323Sed /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 300193323Sed /// specifies a shuffle of elements that is suitable for input to UNPCKH. 301193323Sed bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 302193323Sed 303193323Sed /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 304193323Sed /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 305193323Sed /// <0, 0, 1, 1> 306193323Sed bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 307193323Sed 308193323Sed /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 309193323Sed /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 310193323Sed /// <2, 2, 3, 3> 311193323Sed bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 312193323Sed 313193323Sed /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 314193323Sed /// specifies a shuffle of elements that is suitable for input to MOVSS, 315193323Sed /// MOVSD, and MOVD, i.e. setting the lowest element. 316193323Sed bool isMOVLMask(ShuffleVectorSDNode *N); 317193323Sed 318193323Sed /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 319193323Sed /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 320193323Sed bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 321193323Sed 322193323Sed /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 323193323Sed /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 324193323Sed bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 325193323Sed 326193323Sed /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 327193323Sed /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 328193323Sed bool isMOVDDUPMask(ShuffleVectorSDNode *N); 329193323Sed 330198396Srdivacky /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 331198396Srdivacky /// specifies a shuffle of elements that is suitable for input to PALIGNR. 332198396Srdivacky bool isPALIGNRMask(ShuffleVectorSDNode *N); 333198396Srdivacky 334193323Sed /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 335193323Sed /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 336193323Sed /// instructions. 337193323Sed unsigned getShuffleSHUFImmediate(SDNode *N); 338193323Sed 339193323Sed /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 340198396Srdivacky /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 341193323Sed unsigned getShufflePSHUFHWImmediate(SDNode *N); 342193323Sed 343198396Srdivacky /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 344198396Srdivacky /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 345193323Sed unsigned getShufflePSHUFLWImmediate(SDNode *N); 346198090Srdivacky 347198396Srdivacky /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 348198396Srdivacky /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 349198396Srdivacky unsigned getShufflePALIGNRImmediate(SDNode *N); 350198396Srdivacky 351198090Srdivacky /// isZeroNode - Returns true if Elt is a constant zero or a floating point 352198090Srdivacky /// constant +0.0. 353198090Srdivacky bool isZeroNode(SDValue Elt); 354198090Srdivacky 355198090Srdivacky /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 356198090Srdivacky /// fit into displacement field of the instruction. 357198090Srdivacky bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 358198090Srdivacky bool hasSymbolicDisplacement = true); 359193323Sed } 360193323Sed 361193323Sed //===--------------------------------------------------------------------===// 362193323Sed // X86TargetLowering - X86 Implementation of the TargetLowering interface 363193323Sed class X86TargetLowering : public TargetLowering { 364193323Sed int VarArgsFrameIndex; // FrameIndex for start of varargs area. 365193323Sed int RegSaveFrameIndex; // X86-64 vararg func register save area. 366193323Sed unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. 367193323Sed unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. 368193323Sed int BytesToPopOnReturn; // Number of arg bytes ret should pop. 369193323Sed int BytesCallerReserves; // Number of arg bytes caller makes. 370193323Sed 371193323Sed public: 372193323Sed explicit X86TargetLowering(X86TargetMachine &TM); 373193323Sed 374193323Sed /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 375193323Sed /// jumptable. 376193323Sed SDValue getPICJumpTableRelocBase(SDValue Table, 377193323Sed SelectionDAG &DAG) const; 378193323Sed 379193323Sed // Return the number of bytes that a function should pop when it returns (in 380193323Sed // addition to the space used by the return address). 381193323Sed // 382193323Sed unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } 383193323Sed 384193323Sed // Return the number of bytes that the caller reserves for arguments passed 385193323Sed // to this function. 386193323Sed unsigned getBytesCallerReserves() const { return BytesCallerReserves; } 387193323Sed 388193323Sed /// getStackPtrReg - Return the stack pointer register we are using: either 389193323Sed /// ESP or RSP. 390193323Sed unsigned getStackPtrReg() const { return X86StackPtr; } 391193323Sed 392193323Sed /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 393193323Sed /// function arguments in the caller parameter area. For X86, aggregates 394193323Sed /// that contains are placed at 16-byte boundaries while the rest are at 395193323Sed /// 4-byte boundaries. 396193323Sed virtual unsigned getByValTypeAlignment(const Type *Ty) const; 397193323Sed 398193323Sed /// getOptimalMemOpType - Returns the target specific optimal type for load 399193323Sed /// and store operations as a result of memset, memcpy, and memmove 400198090Srdivacky /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for 401193323Sed /// determining it. 402198090Srdivacky virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 403198090Srdivacky bool isSrcConst, bool isSrcStr, 404198090Srdivacky SelectionDAG &DAG) const; 405195340Sed 406198090Srdivacky /// allowsUnalignedMemoryAccesses - Returns true if the target allows 407198090Srdivacky /// unaligned memory accesses. of the specified type. 408198090Srdivacky virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 409198090Srdivacky return true; 410198090Srdivacky } 411198090Srdivacky 412193323Sed /// LowerOperation - Provide custom lowering hooks for some operations. 413193323Sed /// 414193323Sed virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 415193323Sed 416193323Sed /// ReplaceNodeResults - Replace the results of node with an illegal result 417193323Sed /// type with new values built out of custom code. 418193323Sed /// 419193323Sed virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 420193323Sed SelectionDAG &DAG); 421193323Sed 422193323Sed 423193323Sed virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 424193323Sed 425193323Sed virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 426198090Srdivacky MachineBasicBlock *MBB, 427198090Srdivacky DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 428193323Sed 429193323Sed 430193323Sed /// getTargetNodeName - This method returns the name of a target specific 431193323Sed /// DAG node. 432193323Sed virtual const char *getTargetNodeName(unsigned Opcode) const; 433193323Sed 434193323Sed /// getSetCCResultType - Return the ISD::SETCC ValueType 435198090Srdivacky virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 436193323Sed 437193323Sed /// computeMaskedBitsForTargetNode - Determine which of the bits specified 438193323Sed /// in Mask are known to be either zero or one and return them in the 439193323Sed /// KnownZero/KnownOne bitsets. 440193323Sed virtual void computeMaskedBitsForTargetNode(const SDValue Op, 441193323Sed const APInt &Mask, 442193323Sed APInt &KnownZero, 443193323Sed APInt &KnownOne, 444193323Sed const SelectionDAG &DAG, 445193323Sed unsigned Depth = 0) const; 446193323Sed 447193323Sed virtual bool 448193323Sed isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 449193323Sed 450193323Sed SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); 451193323Sed 452198090Srdivacky virtual bool ExpandInlineAsm(CallInst *CI) const; 453198090Srdivacky 454193323Sed ConstraintType getConstraintType(const std::string &Constraint) const; 455193323Sed 456193323Sed std::vector<unsigned> 457193323Sed getRegClassForInlineAsmConstraint(const std::string &Constraint, 458198090Srdivacky EVT VT) const; 459193323Sed 460198090Srdivacky virtual const char *LowerXConstraint(EVT ConstraintVT) const; 461193323Sed 462193323Sed /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 463193323Sed /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 464193323Sed /// true it means one of the asm constraint of the inline asm instruction 465193323Sed /// being processed is 'm'. 466193323Sed virtual void LowerAsmOperandForConstraint(SDValue Op, 467193323Sed char ConstraintLetter, 468193323Sed bool hasMemory, 469193323Sed std::vector<SDValue> &Ops, 470193323Sed SelectionDAG &DAG) const; 471193323Sed 472193323Sed /// getRegForInlineAsmConstraint - Given a physical register constraint 473193323Sed /// (e.g. {edx}), return the register number and the register class for the 474193323Sed /// register. This should only be used for C_Register constraints. On 475193323Sed /// error, this returns a register number of 0. 476193323Sed std::pair<unsigned, const TargetRegisterClass*> 477193323Sed getRegForInlineAsmConstraint(const std::string &Constraint, 478198090Srdivacky EVT VT) const; 479193323Sed 480193323Sed /// isLegalAddressingMode - Return true if the addressing mode represented 481193323Sed /// by AM is legal for this target, for a load/store of the specified type. 482193323Sed virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 483193323Sed 484193323Sed /// isTruncateFree - Return true if it's free to truncate a value of 485193323Sed /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 486193323Sed /// register EAX to i16 by referencing its sub-register AX. 487193323Sed virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 488198090Srdivacky virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 489193323Sed 490193323Sed /// isZExtFree - Return true if any actual instruction that defines a 491193323Sed /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 492193323Sed /// register. This does not necessarily include registers defined in 493193323Sed /// unknown ways, such as incoming arguments, or copies from unknown 494193323Sed /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 495193323Sed /// does not necessarily apply to truncate instructions. e.g. on x86-64, 496193323Sed /// all instructions that define 32-bit values implicit zero-extend the 497193323Sed /// result out to 64 bits. 498193323Sed virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 499198090Srdivacky virtual bool isZExtFree(EVT VT1, EVT VT2) const; 500193323Sed 501193323Sed /// isNarrowingProfitable - Return true if it's profitable to narrow 502193323Sed /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 503193323Sed /// from i32 to i8 but not from i32 to i16. 504198090Srdivacky virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 505193323Sed 506198892Srdivacky /// isFPImmLegal - Returns true if the target can instruction select the 507198892Srdivacky /// specified FP immediate natively. If false, the legalizer will 508198892Srdivacky /// materialize the FP immediate as a load from a constant pool. 509198892Srdivacky virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 510198892Srdivacky 511193323Sed /// isShuffleMaskLegal - Targets can use this to indicate that they only 512193323Sed /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 513193323Sed /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 514193323Sed /// values are assumed to be legal. 515193323Sed virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 516198090Srdivacky EVT VT) const; 517193323Sed 518193323Sed /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 519193323Sed /// used by Targets can use this to indicate if there is a suitable 520193323Sed /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 521193323Sed /// pool entry. 522193323Sed virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 523198090Srdivacky EVT VT) const; 524193323Sed 525193323Sed /// ShouldShrinkFPConstant - If true, then instruction selection should 526193323Sed /// seek to shrink the FP constant of the specified type to a smaller type 527193323Sed /// in order to save space and / or reduce runtime. 528198090Srdivacky virtual bool ShouldShrinkFPConstant(EVT VT) const { 529193323Sed // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 530193323Sed // expensive than a straight movsd. On the other hand, it's important to 531193323Sed // shrink long double fp constant since fldt is very slow. 532193323Sed return !X86ScalarSSEf64 || VT == MVT::f80; 533193323Sed } 534193323Sed 535193323Sed /// IsEligibleForTailCallOptimization - Check whether the call is eligible 536198090Srdivacky /// for tail call optimization. Targets which want to do tail call 537193323Sed /// optimization should implement this function. 538198090Srdivacky virtual bool 539198090Srdivacky IsEligibleForTailCallOptimization(SDValue Callee, 540198090Srdivacky CallingConv::ID CalleeCC, 541198090Srdivacky bool isVarArg, 542198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 543198090Srdivacky SelectionDAG& DAG) const; 544193323Sed 545193323Sed virtual const X86Subtarget* getSubtarget() { 546193323Sed return Subtarget; 547193323Sed } 548193323Sed 549193323Sed /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 550193323Sed /// computed in an SSE register, not on the X87 floating point stack. 551198090Srdivacky bool isScalarFPTypeInSSEReg(EVT VT) const { 552193323Sed return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 553193323Sed (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 554193323Sed } 555193323Sed 556193323Sed /// getWidenVectorType: given a vector type, returns the type to widen 557193323Sed /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 558198090Srdivacky /// If there is no vector type that we want to widen to, returns EVT::Other 559193323Sed /// When and were to widen is target dependent based on the cost of 560193323Sed /// scalarizing vs using the wider vector type. 561198090Srdivacky virtual EVT getWidenVectorType(EVT VT) const; 562193323Sed 563193323Sed /// createFastISel - This method returns a target specific FastISel object, 564193323Sed /// or null if the target does not support "fast" ISel. 565193323Sed virtual FastISel * 566193323Sed createFastISel(MachineFunction &mf, 567193323Sed MachineModuleInfo *mmi, DwarfWriter *dw, 568193323Sed DenseMap<const Value *, unsigned> &, 569193323Sed DenseMap<const BasicBlock *, MachineBasicBlock *> &, 570193323Sed DenseMap<const AllocaInst *, int> & 571193323Sed#ifndef NDEBUG 572193323Sed , SmallSet<Instruction*, 8> & 573193323Sed#endif 574193323Sed ); 575195340Sed 576195340Sed /// getFunctionAlignment - Return the Log2 alignment of this function. 577195340Sed virtual unsigned getFunctionAlignment(const Function *F) const; 578195340Sed 579193323Sed private: 580193323Sed /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 581193323Sed /// make the right decision when generating code for different targets. 582193323Sed const X86Subtarget *Subtarget; 583193323Sed const X86RegisterInfo *RegInfo; 584193323Sed const TargetData *TD; 585193323Sed 586193323Sed /// X86StackPtr - X86 physical register used as stack ptr. 587193323Sed unsigned X86StackPtr; 588193323Sed 589193323Sed /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 590193323Sed /// floating point ops. 591193323Sed /// When SSE is available, use it for f32 operations. 592193323Sed /// When SSE2 is available, use it for f64 operations. 593193323Sed bool X86ScalarSSEf32; 594193323Sed bool X86ScalarSSEf64; 595193323Sed 596198892Srdivacky /// LegalFPImmediates - A list of legal fp immediates. 597198892Srdivacky std::vector<APFloat> LegalFPImmediates; 598198892Srdivacky 599198892Srdivacky /// addLegalFPImmediate - Indicate that this x86 target can instruction 600198892Srdivacky /// select the specified FP immediate natively. 601198892Srdivacky void addLegalFPImmediate(const APFloat& Imm) { 602198892Srdivacky LegalFPImmediates.push_back(Imm); 603198892Srdivacky } 604198892Srdivacky 605198090Srdivacky SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 606198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 607198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 608198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 609198090Srdivacky SmallVectorImpl<SDValue> &InVals); 610198090Srdivacky SDValue LowerMemArgument(SDValue Chain, 611198090Srdivacky CallingConv::ID CallConv, 612198090Srdivacky const SmallVectorImpl<ISD::InputArg> &ArgInfo, 613198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 614198090Srdivacky const CCValAssign &VA, MachineFrameInfo *MFI, 615198090Srdivacky unsigned i); 616198090Srdivacky SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 617198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 618198090Srdivacky const CCValAssign &VA, 619198090Srdivacky ISD::ArgFlagsTy Flags); 620193323Sed 621193323Sed // Call lowering helpers. 622198090Srdivacky bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); 623193323Sed SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 624193323Sed SDValue Chain, bool IsTailCall, bool Is64Bit, 625193323Sed int FPDiff, DebugLoc dl); 626193323Sed 627198090Srdivacky CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 628198090Srdivacky NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv); 629193323Sed unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); 630193323Sed 631193323Sed std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 632193323Sed bool isSigned); 633200581Srdivacky 634200581Srdivacky SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 635200581Srdivacky SelectionDAG &DAG); 636193323Sed SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 637193323Sed SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 638193323Sed SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 639193323Sed SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 640193323Sed SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 641193323Sed SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 642193323Sed SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 643193323Sed SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 644198892Srdivacky SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 645193323Sed SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 646193323Sed int64_t Offset, SelectionDAG &DAG) const; 647193323Sed SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 648193323Sed SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 649193323Sed SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); 650193323Sed SDValue LowerShift(SDValue Op, SelectionDAG &DAG); 651198090Srdivacky SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 652193323Sed SelectionDAG &DAG); 653193323Sed SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 654193323Sed SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); 655193323Sed SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); 656193323Sed SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); 657193323Sed SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 658193323Sed SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); 659193323Sed SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); 660193323Sed SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); 661193323Sed SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); 662193323Sed SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 663193323Sed SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); 664193323Sed SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); 665193323Sed SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); 666193323Sed SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); 667193323Sed SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 668193323Sed SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 669193323Sed SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); 670193323Sed SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); 671193323Sed SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); 672193323Sed SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 673193323Sed SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 674193323Sed SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 675193323Sed SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); 676193323Sed SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); 677193323Sed SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 678193323Sed SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 679193323Sed SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); 680193323Sed SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); 681193323Sed SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); 682193323Sed SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); 683193323Sed 684193323Sed SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); 685193323Sed SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); 686193323Sed SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); 687193323Sed 688198090Srdivacky virtual SDValue 689198090Srdivacky LowerFormalArguments(SDValue Chain, 690198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 691198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 692198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 693198090Srdivacky SmallVectorImpl<SDValue> &InVals); 694198090Srdivacky virtual SDValue 695198090Srdivacky LowerCall(SDValue Chain, SDValue Callee, 696198090Srdivacky CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 697198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 698198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 699198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 700198090Srdivacky SmallVectorImpl<SDValue> &InVals); 701198090Srdivacky 702198090Srdivacky virtual SDValue 703198090Srdivacky LowerReturn(SDValue Chain, 704198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 705198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 706198090Srdivacky DebugLoc dl, SelectionDAG &DAG); 707198090Srdivacky 708199481Srdivacky virtual bool 709199481Srdivacky CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 710199481Srdivacky const SmallVectorImpl<EVT> &OutTys, 711199481Srdivacky const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 712199481Srdivacky SelectionDAG &DAG); 713199481Srdivacky 714193323Sed void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 715193323Sed SelectionDAG &DAG, unsigned NewOp); 716193323Sed 717193323Sed SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 718193323Sed SDValue Chain, 719193323Sed SDValue Dst, SDValue Src, 720193323Sed SDValue Size, unsigned Align, 721193323Sed const Value *DstSV, uint64_t DstSVOff); 722193323Sed SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 723193323Sed SDValue Chain, 724193323Sed SDValue Dst, SDValue Src, 725193323Sed SDValue Size, unsigned Align, 726193323Sed bool AlwaysInline, 727193323Sed const Value *DstSV, uint64_t DstSVOff, 728193323Sed const Value *SrcSV, uint64_t SrcSVOff); 729193323Sed 730198090Srdivacky /// Utility function to emit string processing sse4.2 instructions 731198090Srdivacky /// that return in xmm0. 732198090Srdivacky /// This takes the instruction to expand, the associated machine basic 733198090Srdivacky /// block, the number of args, and whether or not the second arg is 734198090Srdivacky /// in memory or not. 735198090Srdivacky MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 736198090Srdivacky unsigned argNum, bool inMem) const; 737198090Srdivacky 738193323Sed /// Utility function to emit atomic bitwise operations (and, or, xor). 739198090Srdivacky /// It takes the bitwise instruction to expand, the associated machine basic 740198090Srdivacky /// block, and the associated X86 opcodes for reg/reg and reg/imm. 741193323Sed MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 742193323Sed MachineInstr *BInstr, 743193323Sed MachineBasicBlock *BB, 744193323Sed unsigned regOpc, 745193323Sed unsigned immOpc, 746193323Sed unsigned loadOpc, 747193323Sed unsigned cxchgOpc, 748193323Sed unsigned copyOpc, 749193323Sed unsigned notOpc, 750193323Sed unsigned EAXreg, 751193323Sed TargetRegisterClass *RC, 752193323Sed bool invSrc = false) const; 753193323Sed 754193323Sed MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 755193323Sed MachineInstr *BInstr, 756193323Sed MachineBasicBlock *BB, 757193323Sed unsigned regOpcL, 758193323Sed unsigned regOpcH, 759193323Sed unsigned immOpcL, 760193323Sed unsigned immOpcH, 761193323Sed bool invSrc = false) const; 762193323Sed 763193323Sed /// Utility function to emit atomic min and max. It takes the min/max 764193323Sed /// instruction to expand, the associated basic block, and the associated 765193323Sed /// cmov opcode for moving the min or max value. 766193323Sed MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 767193323Sed MachineBasicBlock *BB, 768193323Sed unsigned cmovOpc) const; 769193323Sed 770198090Srdivacky /// Utility function to emit the xmm reg save portion of va_start. 771198090Srdivacky MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 772198090Srdivacky MachineInstr *BInstr, 773198090Srdivacky MachineBasicBlock *BB) const; 774198090Srdivacky 775198090Srdivacky MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 776198090Srdivacky MachineBasicBlock *BB, 777198090Srdivacky DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 778198090Srdivacky 779193323Sed /// Emit nodes that will be selected as "test Op0,Op0", or something 780193323Sed /// equivalent, for use with the given x86 condition code. 781193323Sed SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); 782193323Sed 783193323Sed /// Emit nodes that will be selected as "cmp Op0,Op1", or something 784193323Sed /// equivalent, for use with the given x86 condition code. 785193323Sed SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 786193323Sed SelectionDAG &DAG); 787193323Sed }; 788193323Sed 789193323Sed namespace X86 { 790193323Sed FastISel *createFastISel(MachineFunction &mf, 791193323Sed MachineModuleInfo *mmi, DwarfWriter *dw, 792193323Sed DenseMap<const Value *, unsigned> &, 793193323Sed DenseMap<const BasicBlock *, MachineBasicBlock *> &, 794193323Sed DenseMap<const AllocaInst *, int> & 795193323Sed#ifndef NDEBUG 796193323Sed , SmallSet<Instruction*, 8> & 797193323Sed#endif 798193323Sed ); 799193323Sed } 800193323Sed} 801193323Sed 802193323Sed#endif // X86ISELLOWERING_H 803