X86ISelLowering.h revision 200581
1139749Simp//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 218781Sgibbs// 318781Sgibbs// The LLVM Compiler Infrastructure 418781Sgibbs// 555945Sgibbs// This file is distributed under the University of Illinois Open Source 618781Sgibbs// License. See LICENSE.TXT for details. 718781Sgibbs// 818781Sgibbs//===----------------------------------------------------------------------===// 918781Sgibbs// 1018781Sgibbs// This file defines the interfaces that X86 uses to lower LLVM code into a 1118781Sgibbs// selection DAG. 1239217Sgibbs// 1339217Sgibbs//===----------------------------------------------------------------------===// 1418781Sgibbs 1518781Sgibbs#ifndef X86ISELLOWERING_H 1618781Sgibbs#define X86ISELLOWERING_H 1718781Sgibbs 1818781Sgibbs#include "X86Subtarget.h" 1918781Sgibbs#include "X86RegisterInfo.h" 2018781Sgibbs#include "X86MachineFunctionInfo.h" 2118781Sgibbs#include "llvm/Target/TargetLowering.h" 2218781Sgibbs#include "llvm/CodeGen/FastISel.h" 2318781Sgibbs#include "llvm/CodeGen/SelectionDAG.h" 2418781Sgibbs#include "llvm/CodeGen/CallingConvLower.h" 2518781Sgibbs 2618781Sgibbsnamespace llvm { 2718781Sgibbs namespace X86ISD { 2818781Sgibbs // X86 Specific DAG Nodes 2918781Sgibbs enum NodeType { 3018781Sgibbs // Start the numbering where the builtin ops leave off. 3118781Sgibbs FIRST_NUMBER = ISD::BUILTIN_OP_END, 3250477Speter 3318781Sgibbs /// BSF - Bit scan forward. 34139749Simp /// BSR - Bit scan reverse. 3518781Sgibbs BSF, 3618781Sgibbs BSR, 3718781Sgibbs 3818781Sgibbs /// SHLD, SHRD - Double shift instructions. These correspond to 3918781Sgibbs /// X86::SHLDxx and X86::SHRDxx instructions. 4018781Sgibbs SHLD, 4118781Sgibbs SHRD, 4218781Sgibbs 4318781Sgibbs /// FAND - Bitwise logical AND of floating point values. This corresponds 4418781Sgibbs /// to X86::ANDPS or X86::ANDPD. 4518781Sgibbs FAND, 4618781Sgibbs 4739217Sgibbs /// FOR - Bitwise logical OR of floating point values. This corresponds 4839217Sgibbs /// to X86::ORPS or X86::ORPD. 4939217Sgibbs FOR, 5039217Sgibbs 5139217Sgibbs /// FXOR - Bitwise logical XOR of floating point values. This corresponds 5239217Sgibbs /// to X86::XORPS or X86::XORPD. 5351164Sgibbs FXOR, 5439217Sgibbs 5518781Sgibbs /// FSRL - Bitwise logical right shift of floating point values. These 5618781Sgibbs /// corresponds to X86::PSRLDQ. 5739217Sgibbs FSRL, 5839217Sgibbs 5939217Sgibbs /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 6018781Sgibbs /// integer source in memory and FP reg result. This corresponds to the 61195534Sscottl /// X86::FILD*m instructions. It has three inputs (token chain, address, 62195534Sscottl /// and source type) and two outputs (FP value and token chain). FILD_FLAG 6318781Sgibbs /// also produces a flag). 6418781Sgibbs FILD, 6518781Sgibbs FILD_FLAG, 6639217Sgibbs 6739217Sgibbs /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 6839217Sgibbs /// integer destination in memory and a FP reg source. This corresponds 6939217Sgibbs /// to the X86::FIST*m instructions and the rounding mode change stuff. It 7039217Sgibbs /// has two inputs (token chain and address) and two outputs (int value 7139217Sgibbs /// and token chain). 7239217Sgibbs FP_TO_INT16_IN_MEM, 7339217Sgibbs FP_TO_INT32_IN_MEM, 7439217Sgibbs FP_TO_INT64_IN_MEM, 7539217Sgibbs 7639217Sgibbs /// FLD - This instruction implements an extending load to FP stack slots. 7718781Sgibbs /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 7818781Sgibbs /// operand, ptr to load from, and a ValueType node indicating the type 7955945Sgibbs /// to load to. 8055945Sgibbs FLD, 8155945Sgibbs 8255945Sgibbs /// FST - This instruction implements a truncating store to FP stack 8355945Sgibbs /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 8455945Sgibbs /// chain operand, value to store, address, and a ValueType to store it 8539217Sgibbs /// as. 8618781Sgibbs FST, 8739217Sgibbs 8839217Sgibbs /// CALL - These operations represent an abstract X86 call 8939217Sgibbs /// instruction, which includes a bunch of information. In particular the 9039217Sgibbs /// operands of these node are: 9155945Sgibbs /// 9239217Sgibbs /// #0 - The incoming token chain 9339217Sgibbs /// #1 - The callee 9439217Sgibbs /// #2 - The number of arg bytes the caller pushes on the stack. 9539217Sgibbs /// #3 - The number of arg bytes the callee pops off the stack. 9639217Sgibbs /// #4 - The value to pass in AL/AX/EAX (optional) 97241492Sjhb /// #5 - The value to pass in DL/DX/EDX (optional) 9855945Sgibbs /// 9960938Sjake /// The result values of these nodes are: 10039217Sgibbs /// 10139217Sgibbs /// #0 - The outgoing token chain 10239217Sgibbs /// #1 - The first register result value (optional) 10339217Sgibbs /// #2 - The second register result value (optional) 10418781Sgibbs /// 10518781Sgibbs CALL, 10618781Sgibbs 10718781Sgibbs /// RDTSC_DAG - This operation implements the lowering for 10839217Sgibbs /// readcyclecounter 10918781Sgibbs RDTSC_DAG, 11018781Sgibbs 11118781Sgibbs /// X86 compare and logical compare instructions. 11218781Sgibbs CMP, COMI, UCOMI, 11318781Sgibbs 11439217Sgibbs /// X86 bit-test instructions. 11539217Sgibbs BT, 11618781Sgibbs 11718781Sgibbs /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 11818781Sgibbs /// operand produced by a CMP instruction. 11918781Sgibbs SETCC, 12018781Sgibbs 12118781Sgibbs // Same as SETCC except it's materialized with a sbb and the value is all 12218781Sgibbs // one's or all zero's. 12318781Sgibbs SETCC_CARRY, 12418781Sgibbs 12518781Sgibbs /// X86 conditional moves. Operand 0 and operand 1 are the two values 12618781Sgibbs /// to select from. Operand 2 is the condition code, and operand 3 is the 12718781Sgibbs /// flag operand produced by a CMP or TEST instruction. It also writes a 12818781Sgibbs /// flag result. 12939217Sgibbs CMOV, 13018781Sgibbs 13118781Sgibbs /// X86 conditional branches. Operand 0 is the chain operand, operand 1 13218781Sgibbs /// is the block to branch if condition is true, operand 2 is the 13339217Sgibbs /// condition code, and operand 3 is the flag operand produced by a CMP 13439217Sgibbs /// or TEST instruction. 13539217Sgibbs BRCOND, 13618781Sgibbs 13739217Sgibbs /// Return with a flag operand. Operand 0 is the chain operand, operand 13839217Sgibbs /// 1 is the number of bytes of stack to pop. 13918781Sgibbs RET_FLAG, 14039217Sgibbs 14139217Sgibbs /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 14239217Sgibbs REP_STOS, 14339217Sgibbs 14439217Sgibbs /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 14539217Sgibbs REP_MOVS, 14639217Sgibbs 14739217Sgibbs /// GlobalBaseReg - On Darwin, this node represents the result of the popl 14839217Sgibbs /// at function entry, used for PIC code. 14939217Sgibbs GlobalBaseReg, 15039217Sgibbs 15139217Sgibbs /// Wrapper - A wrapper node for TargetConstantPool, 15239217Sgibbs /// TargetExternalSymbol, and TargetGlobalAddress. 15339217Sgibbs Wrapper, 15439217Sgibbs 15539217Sgibbs /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 15618781Sgibbs /// relative displacements. 15718781Sgibbs WrapperRIP, 15818781Sgibbs 15918781Sgibbs /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 16018781Sgibbs /// i32, corresponds to X86::PEXTRB. 16118781Sgibbs PEXTRB, 16218781Sgibbs 16318781Sgibbs /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 16418781Sgibbs /// i32, corresponds to X86::PEXTRW. 16539217Sgibbs PEXTRW, 16639217Sgibbs 16718781Sgibbs /// INSERTPS - Insert any element of a 4 x float vector into any element 16818781Sgibbs /// of a destination 4 x floatvector. 16918781Sgibbs INSERTPS, 17018781Sgibbs 17118781Sgibbs /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 17218781Sgibbs /// corresponds to X86::PINSRB. 17318781Sgibbs PINSRB, 17418781Sgibbs 17518781Sgibbs /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 17618781Sgibbs /// corresponds to X86::PINSRW. 17739217Sgibbs PINSRW, 17839217Sgibbs 17939217Sgibbs /// PSHUFB - Shuffle 16 8-bit values within a vector. 18039217Sgibbs PSHUFB, 18118781Sgibbs 18239217Sgibbs /// FMAX, FMIN - Floating point max and min. 18339217Sgibbs /// 18439217Sgibbs FMAX, FMIN, 18539217Sgibbs 18639217Sgibbs /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 18739217Sgibbs /// approximation. Note that these typically require refinement 18839217Sgibbs /// in order to obtain suitable precision. 18939217Sgibbs FRSQRT, FRCP, 19039217Sgibbs 19139217Sgibbs // TLSADDR - Thread Local Storage. 19239217Sgibbs TLSADDR, 19339217Sgibbs 19439217Sgibbs // SegmentBaseAddress - The address segment:0 19539217Sgibbs SegmentBaseAddress, 19639217Sgibbs 19739217Sgibbs // EH_RETURN - Exception Handling helpers. 19839217Sgibbs EH_RETURN, 19939217Sgibbs 20039217Sgibbs /// TC_RETURN - Tail call return. 20139217Sgibbs /// operand #0 chain 20239217Sgibbs /// operand #1 callee (register or absolute) 20339217Sgibbs /// operand #2 stack adjustment 20439217Sgibbs /// operand #3 optional in flag 20539217Sgibbs TC_RETURN, 20639217Sgibbs 20739217Sgibbs // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 20839217Sgibbs LCMPXCHG_DAG, 20939217Sgibbs LCMPXCHG8_DAG, 21039217Sgibbs 21139217Sgibbs // FNSTCW16m - Store FP control world into i16 memory. 21218781Sgibbs FNSTCW16m, 21318781Sgibbs 21418781Sgibbs // VZEXT_MOVL - Vector move low and zero extend. 21518781Sgibbs VZEXT_MOVL, 21618781Sgibbs 21718781Sgibbs // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 21818781Sgibbs VZEXT_LOAD, 21918781Sgibbs 22018781Sgibbs // VSHL, VSRL - Vector logical left / right shift. 22118781Sgibbs VSHL, VSRL, 22218781Sgibbs 22318781Sgibbs // CMPPD, CMPPS - Vector double/float comparison. 22418781Sgibbs // CMPPD, CMPPS - Vector double/float comparison. 22518781Sgibbs CMPPD, CMPPS, 22618781Sgibbs 22718781Sgibbs // PCMP* - Vector integer comparisons. 22818781Sgibbs PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 22918781Sgibbs PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 23018781Sgibbs 23118781Sgibbs // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 23218781Sgibbs ADD, SUB, SMUL, UMUL, 23318781Sgibbs INC, DEC, OR, XOR, AND, 23418781Sgibbs 23518781Sgibbs // MUL_IMM - X86 specific multiply by immediate. 23618781Sgibbs MUL_IMM, 23718781Sgibbs 23818781Sgibbs // PTEST - Vector bitwise comparisons 23918781Sgibbs PTEST, 24018781Sgibbs 24139217Sgibbs // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 24218781Sgibbs // according to %al. An operator is needed so that this can be expanded 24339217Sgibbs // with control flow. 24439217Sgibbs VASTART_SAVE_XMM_REGS, 24539217Sgibbs 24639217Sgibbs // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 24739217Sgibbs // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 24839217Sgibbs // Atomic 64-bit binary operations. 24939217Sgibbs ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 25039217Sgibbs ATOMSUB64_DAG, 25139217Sgibbs ATOMOR64_DAG, 25218781Sgibbs ATOMXOR64_DAG, 25339217Sgibbs ATOMAND64_DAG, 25439217Sgibbs ATOMNAND64_DAG, 25539217Sgibbs ATOMSWAP64_DAG 25639217Sgibbs }; 25739217Sgibbs } 25839217Sgibbs 25939217Sgibbs /// Define some predicates that are used for node matching. 26018781Sgibbs namespace X86 { 26118781Sgibbs /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 26218781Sgibbs /// specifies a shuffle of elements that is suitable for input to PSHUFD. 26318781Sgibbs bool isPSHUFDMask(ShuffleVectorSDNode *N); 26418781Sgibbs 26518781Sgibbs /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 26618781Sgibbs /// specifies a shuffle of elements that is suitable for input to PSHUFD. 26718781Sgibbs bool isPSHUFHWMask(ShuffleVectorSDNode *N); 26818781Sgibbs 26918781Sgibbs /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 27018781Sgibbs /// specifies a shuffle of elements that is suitable for input to PSHUFD. 27118781Sgibbs bool isPSHUFLWMask(ShuffleVectorSDNode *N); 27218781Sgibbs 27318781Sgibbs /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 27418781Sgibbs /// specifies a shuffle of elements that is suitable for input to SHUFP*. 27518781Sgibbs bool isSHUFPMask(ShuffleVectorSDNode *N); 27618781Sgibbs 27718781Sgibbs /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 27818781Sgibbs /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 27918781Sgibbs bool isMOVHLPSMask(ShuffleVectorSDNode *N); 28018781Sgibbs 28118781Sgibbs /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 28218781Sgibbs /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 28318781Sgibbs /// <2, 3, 2, 3> 28418781Sgibbs bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 28518781Sgibbs 28618781Sgibbs /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 28718781Sgibbs /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 28818781Sgibbs bool isMOVLPMask(ShuffleVectorSDNode *N); 28918781Sgibbs 29018781Sgibbs /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 29118781Sgibbs /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 29218781Sgibbs /// as well as MOVLHPS. 29339217Sgibbs bool isMOVLHPSMask(ShuffleVectorSDNode *N); 29439217Sgibbs 29539217Sgibbs /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 29639217Sgibbs /// specifies a shuffle of elements that is suitable for input to UNPCKL. 29739217Sgibbs bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 29839217Sgibbs 29918781Sgibbs /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 30039217Sgibbs /// specifies a shuffle of elements that is suitable for input to UNPCKH. 30139217Sgibbs bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 30239217Sgibbs 30318781Sgibbs /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 30418781Sgibbs /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 30518781Sgibbs /// <0, 0, 1, 1> 30618781Sgibbs bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 30718781Sgibbs 30818781Sgibbs /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 30918781Sgibbs /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 31018781Sgibbs /// <2, 2, 3, 3> 31139217Sgibbs bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 31239217Sgibbs 31339217Sgibbs /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 31439217Sgibbs /// specifies a shuffle of elements that is suitable for input to MOVSS, 31539217Sgibbs /// MOVSD, and MOVD, i.e. setting the lowest element. 31639217Sgibbs bool isMOVLMask(ShuffleVectorSDNode *N); 31739217Sgibbs 31839217Sgibbs /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 31939217Sgibbs /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 32039217Sgibbs bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 32139217Sgibbs 32239217Sgibbs /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 32339217Sgibbs /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 32439217Sgibbs bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 32539217Sgibbs 32639217Sgibbs /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 32739217Sgibbs /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 32839217Sgibbs bool isMOVDDUPMask(ShuffleVectorSDNode *N); 32939217Sgibbs 33039217Sgibbs /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 33139217Sgibbs /// specifies a shuffle of elements that is suitable for input to PALIGNR. 33218781Sgibbs bool isPALIGNRMask(ShuffleVectorSDNode *N); 33318781Sgibbs 33418781Sgibbs /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 33518781Sgibbs /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 33618781Sgibbs /// instructions. 33718781Sgibbs unsigned getShuffleSHUFImmediate(SDNode *N); 33818781Sgibbs 33918781Sgibbs /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 34018781Sgibbs /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 34118781Sgibbs unsigned getShufflePSHUFHWImmediate(SDNode *N); 34218781Sgibbs 34318781Sgibbs /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 34418781Sgibbs /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 34518781Sgibbs unsigned getShufflePSHUFLWImmediate(SDNode *N); 34618781Sgibbs 34718781Sgibbs /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 34818781Sgibbs /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 34918781Sgibbs unsigned getShufflePALIGNRImmediate(SDNode *N); 35018781Sgibbs 35118781Sgibbs /// isZeroNode - Returns true if Elt is a constant zero or a floating point 35218781Sgibbs /// constant +0.0. 35318781Sgibbs bool isZeroNode(SDValue Elt); 35418781Sgibbs 35518781Sgibbs /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 35618781Sgibbs /// fit into displacement field of the instruction. 35718781Sgibbs bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 35839217Sgibbs bool hasSymbolicDisplacement = true); 35918781Sgibbs } 36018781Sgibbs 36118781Sgibbs //===--------------------------------------------------------------------===// 36218781Sgibbs // X86TargetLowering - X86 Implementation of the TargetLowering interface 36318781Sgibbs class X86TargetLowering : public TargetLowering { 36418781Sgibbs int VarArgsFrameIndex; // FrameIndex for start of varargs area. 36518781Sgibbs int RegSaveFrameIndex; // X86-64 vararg func register save area. 36639217Sgibbs unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. 36739217Sgibbs unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. 36818781Sgibbs int BytesToPopOnReturn; // Number of arg bytes ret should pop. 36918781Sgibbs int BytesCallerReserves; // Number of arg bytes caller makes. 37018781Sgibbs 37118781Sgibbs public: 37218781Sgibbs explicit X86TargetLowering(X86TargetMachine &TM); 37318781Sgibbs 37418781Sgibbs /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 37518781Sgibbs /// jumptable. 37639217Sgibbs SDValue getPICJumpTableRelocBase(SDValue Table, 37718781Sgibbs SelectionDAG &DAG) const; 37818781Sgibbs 37918781Sgibbs // Return the number of bytes that a function should pop when it returns (in 38018781Sgibbs // addition to the space used by the return address). 38118781Sgibbs // 38218781Sgibbs unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } 38339217Sgibbs 38439217Sgibbs // Return the number of bytes that the caller reserves for arguments passed 38539217Sgibbs // to this function. 38639217Sgibbs unsigned getBytesCallerReserves() const { return BytesCallerReserves; } 38739217Sgibbs 38839217Sgibbs /// getStackPtrReg - Return the stack pointer register we are using: either 38955945Sgibbs /// ESP or RSP. 39039217Sgibbs unsigned getStackPtrReg() const { return X86StackPtr; } 39139217Sgibbs 39239217Sgibbs /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 39339217Sgibbs /// function arguments in the caller parameter area. For X86, aggregates 39439217Sgibbs /// that contains are placed at 16-byte boundaries while the rest are at 39539217Sgibbs /// 4-byte boundaries. 39639217Sgibbs virtual unsigned getByValTypeAlignment(const Type *Ty) const; 39739217Sgibbs 39855945Sgibbs /// getOptimalMemOpType - Returns the target specific optimal type for load 39939217Sgibbs /// and store operations as a result of memset, memcpy, and memmove 40039217Sgibbs /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for 40155945Sgibbs /// determining it. 40239217Sgibbs virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 40339217Sgibbs bool isSrcConst, bool isSrcStr, 40418781Sgibbs SelectionDAG &DAG) const; 40518781Sgibbs 40618781Sgibbs /// allowsUnalignedMemoryAccesses - Returns true if the target allows 40718781Sgibbs /// unaligned memory accesses. of the specified type. 40818781Sgibbs virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 40918781Sgibbs return true; 41039217Sgibbs } 41139217Sgibbs 41218781Sgibbs /// LowerOperation - Provide custom lowering hooks for some operations. 41318781Sgibbs /// 41418781Sgibbs virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 41518781Sgibbs 41618781Sgibbs /// ReplaceNodeResults - Replace the results of node with an illegal result 41718781Sgibbs /// type with new values built out of custom code. 41818781Sgibbs /// 41918781Sgibbs virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 42039217Sgibbs SelectionDAG &DAG); 42139217Sgibbs 42239217Sgibbs 42339217Sgibbs virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 42439217Sgibbs 42518781Sgibbs virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 42618781Sgibbs MachineBasicBlock *MBB, 42718781Sgibbs DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 42818781Sgibbs 42918781Sgibbs 43018781Sgibbs /// getTargetNodeName - This method returns the name of a target specific 43118781Sgibbs /// DAG node. 43218781Sgibbs virtual const char *getTargetNodeName(unsigned Opcode) const; 43318781Sgibbs 43418781Sgibbs /// getSetCCResultType - Return the ISD::SETCC ValueType 43539217Sgibbs virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 43639217Sgibbs 43739217Sgibbs /// computeMaskedBitsForTargetNode - Determine which of the bits specified 43839217Sgibbs /// in Mask are known to be either zero or one and return them in the 43939217Sgibbs /// KnownZero/KnownOne bitsets. 44039217Sgibbs virtual void computeMaskedBitsForTargetNode(const SDValue Op, 44155945Sgibbs const APInt &Mask, 44218781Sgibbs APInt &KnownZero, 44318781Sgibbs APInt &KnownOne, 44418781Sgibbs const SelectionDAG &DAG, 44518781Sgibbs unsigned Depth = 0) const; 44618781Sgibbs 44718781Sgibbs virtual bool 44818781Sgibbs isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 44918781Sgibbs 45039217Sgibbs SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); 45118781Sgibbs 45218781Sgibbs virtual bool ExpandInlineAsm(CallInst *CI) const; 45318781Sgibbs 45418781Sgibbs ConstraintType getConstraintType(const std::string &Constraint) const; 45518781Sgibbs 45618781Sgibbs std::vector<unsigned> 45718781Sgibbs getRegClassForInlineAsmConstraint(const std::string &Constraint, 45818781Sgibbs EVT VT) const; 45918781Sgibbs 46018781Sgibbs virtual const char *LowerXConstraint(EVT ConstraintVT) const; 46118781Sgibbs 46218781Sgibbs /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 46318781Sgibbs /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 46418781Sgibbs /// true it means one of the asm constraint of the inline asm instruction 46518781Sgibbs /// being processed is 'm'. 46618781Sgibbs virtual void LowerAsmOperandForConstraint(SDValue Op, 46718781Sgibbs char ConstraintLetter, 46818781Sgibbs bool hasMemory, 46918781Sgibbs std::vector<SDValue> &Ops, 47018781Sgibbs SelectionDAG &DAG) const; 47118781Sgibbs 47218781Sgibbs /// getRegForInlineAsmConstraint - Given a physical register constraint 47318781Sgibbs /// (e.g. {edx}), return the register number and the register class for the 47418781Sgibbs /// register. This should only be used for C_Register constraints. On 47518781Sgibbs /// error, this returns a register number of 0. 47618781Sgibbs std::pair<unsigned, const TargetRegisterClass*> 47718781Sgibbs getRegForInlineAsmConstraint(const std::string &Constraint, 47818781Sgibbs EVT VT) const; 47918781Sgibbs 48018781Sgibbs /// isLegalAddressingMode - Return true if the addressing mode represented 48139217Sgibbs /// by AM is legal for this target, for a load/store of the specified type. 48239217Sgibbs virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 48339217Sgibbs 48439217Sgibbs /// isTruncateFree - Return true if it's free to truncate a value of 48539217Sgibbs /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 48639217Sgibbs /// register EAX to i16 by referencing its sub-register AX. 48739217Sgibbs virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 48839217Sgibbs virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 48939217Sgibbs 49039217Sgibbs /// isZExtFree - Return true if any actual instruction that defines a 49139217Sgibbs /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 49239217Sgibbs /// register. This does not necessarily include registers defined in 49339217Sgibbs /// unknown ways, such as incoming arguments, or copies from unknown 49439217Sgibbs /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 49539217Sgibbs /// does not necessarily apply to truncate instructions. e.g. on x86-64, 49639217Sgibbs /// all instructions that define 32-bit values implicit zero-extend the 49739217Sgibbs /// result out to 64 bits. 49859082Snyan virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 499170872Sscottl virtual bool isZExtFree(EVT VT1, EVT VT2) const; 500241492Sjhb 501241492Sjhb /// isNarrowingProfitable - Return true if it's profitable to narrow 50255945Sgibbs /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 50360938Sjake /// from i32 to i8 but not from i32 to i16. 50455945Sgibbs virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 50560938Sjake 50655945Sgibbs /// isFPImmLegal - Returns true if the target can instruction select the 50755945Sgibbs /// specified FP immediate natively. If false, the legalizer will 50855945Sgibbs /// materialize the FP immediate as a load from a constant pool. 50955945Sgibbs virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 51039217Sgibbs 51155945Sgibbs /// isShuffleMaskLegal - Targets can use this to indicate that they only 51255945Sgibbs /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 51355945Sgibbs /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 51455945Sgibbs /// values are assumed to be legal. 51555945Sgibbs virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 51655945Sgibbs EVT VT) const; 51755945Sgibbs 51855945Sgibbs /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 51955945Sgibbs /// used by Targets can use this to indicate if there is a suitable 52055945Sgibbs /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 52155945Sgibbs /// pool entry. 52218781Sgibbs virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 52318781Sgibbs EVT VT) const; 52418781Sgibbs 52518781Sgibbs /// ShouldShrinkFPConstant - If true, then instruction selection should 52618781Sgibbs /// seek to shrink the FP constant of the specified type to a smaller type 52718781Sgibbs /// in order to save space and / or reduce runtime. 52818781Sgibbs virtual bool ShouldShrinkFPConstant(EVT VT) const { 52918781Sgibbs // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 53018781Sgibbs // expensive than a straight movsd. On the other hand, it's important to 53118781Sgibbs // shrink long double fp constant since fldt is very slow. 53218781Sgibbs return !X86ScalarSSEf64 || VT == MVT::f80; 53318781Sgibbs } 53418781Sgibbs 53539217Sgibbs /// IsEligibleForTailCallOptimization - Check whether the call is eligible 53618781Sgibbs /// for tail call optimization. Targets which want to do tail call 53755945Sgibbs /// optimization should implement this function. 53839217Sgibbs virtual bool 53939217Sgibbs IsEligibleForTailCallOptimization(SDValue Callee, 54018781Sgibbs CallingConv::ID CalleeCC, 54155945Sgibbs bool isVarArg, 54239217Sgibbs const SmallVectorImpl<ISD::InputArg> &Ins, 543241492Sjhb SelectionDAG& DAG) const; 54455945Sgibbs 54555945Sgibbs virtual const X86Subtarget* getSubtarget() { 54655945Sgibbs return Subtarget; 54755945Sgibbs } 54855945Sgibbs 54955945Sgibbs /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 55055945Sgibbs /// computed in an SSE register, not on the X87 floating point stack. 55155945Sgibbs bool isScalarFPTypeInSSEReg(EVT VT) const { 55255945Sgibbs return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 55355945Sgibbs (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 55455945Sgibbs } 55539217Sgibbs 55655945Sgibbs /// getWidenVectorType: given a vector type, returns the type to widen 557241492Sjhb /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 55818781Sgibbs /// If there is no vector type that we want to widen to, returns EVT::Other 55918781Sgibbs /// When and were to widen is target dependent based on the cost of 56018781Sgibbs /// scalarizing vs using the wider vector type. 56118781Sgibbs virtual EVT getWidenVectorType(EVT VT) const; 56218781Sgibbs 56318781Sgibbs /// createFastISel - This method returns a target specific FastISel object, 56418781Sgibbs /// or null if the target does not support "fast" ISel. 56518781Sgibbs virtual FastISel * 56618781Sgibbs createFastISel(MachineFunction &mf, 56718781Sgibbs MachineModuleInfo *mmi, DwarfWriter *dw, 56818781Sgibbs DenseMap<const Value *, unsigned> &, 56918781Sgibbs DenseMap<const BasicBlock *, MachineBasicBlock *> &, 57018781Sgibbs DenseMap<const AllocaInst *, int> & 57118781Sgibbs#ifndef NDEBUG 57218781Sgibbs , SmallSet<Instruction*, 8> & 57318781Sgibbs#endif 57418781Sgibbs ); 57518781Sgibbs 57618781Sgibbs /// getFunctionAlignment - Return the Log2 alignment of this function. 57718781Sgibbs virtual unsigned getFunctionAlignment(const Function *F) const; 57818781Sgibbs 57918781Sgibbs private: 58018781Sgibbs /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 58118781Sgibbs /// make the right decision when generating code for different targets. 58218781Sgibbs const X86Subtarget *Subtarget; 58318781Sgibbs const X86RegisterInfo *RegInfo; 58418781Sgibbs const TargetData *TD; 58518781Sgibbs 58618781Sgibbs /// X86StackPtr - X86 physical register used as stack ptr. 58718781Sgibbs unsigned X86StackPtr; 58818781Sgibbs 58918781Sgibbs /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 59018781Sgibbs /// floating point ops. 59118781Sgibbs /// When SSE is available, use it for f32 operations. 59218781Sgibbs /// When SSE2 is available, use it for f64 operations. 59318781Sgibbs bool X86ScalarSSEf32; 59418781Sgibbs bool X86ScalarSSEf64; 59518781Sgibbs 59618781Sgibbs /// LegalFPImmediates - A list of legal fp immediates. 59718781Sgibbs std::vector<APFloat> LegalFPImmediates; 59818781Sgibbs 59918781Sgibbs /// addLegalFPImmediate - Indicate that this x86 target can instruction 60018781Sgibbs /// select the specified FP immediate natively. 60118781Sgibbs void addLegalFPImmediate(const APFloat& Imm) { 60218781Sgibbs LegalFPImmediates.push_back(Imm); 60318781Sgibbs } 60418781Sgibbs 60518781Sgibbs SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 60618781Sgibbs CallingConv::ID CallConv, bool isVarArg, 60739217Sgibbs const SmallVectorImpl<ISD::InputArg> &Ins, 60818781Sgibbs DebugLoc dl, SelectionDAG &DAG, 60918781Sgibbs SmallVectorImpl<SDValue> &InVals); 61018781Sgibbs SDValue LowerMemArgument(SDValue Chain, 61155945Sgibbs CallingConv::ID CallConv, 61218781Sgibbs const SmallVectorImpl<ISD::InputArg> &ArgInfo, 61318781Sgibbs DebugLoc dl, SelectionDAG &DAG, 61418781Sgibbs const CCValAssign &VA, MachineFrameInfo *MFI, 61518781Sgibbs unsigned i); 61618781Sgibbs SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 61718781Sgibbs DebugLoc dl, SelectionDAG &DAG, 61818781Sgibbs const CCValAssign &VA, 61918781Sgibbs ISD::ArgFlagsTy Flags); 62018781Sgibbs 62118781Sgibbs // Call lowering helpers. 62218781Sgibbs bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); 62339217Sgibbs SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 62439217Sgibbs SDValue Chain, bool IsTailCall, bool Is64Bit, 62539217Sgibbs int FPDiff, DebugLoc dl); 62639217Sgibbs 62718781Sgibbs CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 62818781Sgibbs NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv); 62918781Sgibbs unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); 63018781Sgibbs 63118781Sgibbs std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 63218781Sgibbs bool isSigned); 63318781Sgibbs 63418781Sgibbs SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 63518781Sgibbs SelectionDAG &DAG); 63618781Sgibbs SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 63718781Sgibbs SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 63818781Sgibbs SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 63918781Sgibbs SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 64018781Sgibbs SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 64118781Sgibbs SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 64218781Sgibbs SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 64318781Sgibbs SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 64418781Sgibbs SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 64518781Sgibbs SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 64618781Sgibbs int64_t Offset, SelectionDAG &DAG) const; 64718781Sgibbs SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 64818781Sgibbs SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 64918781Sgibbs SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); 65018781Sgibbs SDValue LowerShift(SDValue Op, SelectionDAG &DAG); 65118781Sgibbs SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 65218781Sgibbs SelectionDAG &DAG); 65318781Sgibbs SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 65418781Sgibbs SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); 65518781Sgibbs SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); 65618781Sgibbs SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); 65718781Sgibbs SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 65818781Sgibbs SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); 65918781Sgibbs SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); 66018781Sgibbs SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); 66118781Sgibbs SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); 66218781Sgibbs SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 66318781Sgibbs SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); 66418781Sgibbs SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); 66539217Sgibbs SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); 66618781Sgibbs SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); 66718781Sgibbs SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 66818781Sgibbs SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 66918781Sgibbs SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); 67018781Sgibbs SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); 67118781Sgibbs SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); 67218781Sgibbs SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 67318781Sgibbs SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 67418781Sgibbs SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 67518781Sgibbs SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); 67618781Sgibbs SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); 67718781Sgibbs SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 67818781Sgibbs SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 67918781Sgibbs SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); 68039217Sgibbs SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); 68118781Sgibbs SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); 68218781Sgibbs SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); 68318781Sgibbs 68418781Sgibbs SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); 68518781Sgibbs SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); 68618781Sgibbs SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); 68718781Sgibbs 68818781Sgibbs virtual SDValue 68918781Sgibbs LowerFormalArguments(SDValue Chain, 69018781Sgibbs CallingConv::ID CallConv, bool isVarArg, 69118781Sgibbs const SmallVectorImpl<ISD::InputArg> &Ins, 69218781Sgibbs DebugLoc dl, SelectionDAG &DAG, 69318781Sgibbs SmallVectorImpl<SDValue> &InVals); 69439217Sgibbs virtual SDValue 69518781Sgibbs LowerCall(SDValue Chain, SDValue Callee, 69618781Sgibbs CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 69718781Sgibbs const SmallVectorImpl<ISD::OutputArg> &Outs, 69818781Sgibbs const SmallVectorImpl<ISD::InputArg> &Ins, 69918781Sgibbs DebugLoc dl, SelectionDAG &DAG, 70018781Sgibbs SmallVectorImpl<SDValue> &InVals); 70118781Sgibbs 70218781Sgibbs virtual SDValue 70318781Sgibbs LowerReturn(SDValue Chain, 70418781Sgibbs CallingConv::ID CallConv, bool isVarArg, 70539217Sgibbs const SmallVectorImpl<ISD::OutputArg> &Outs, 70639217Sgibbs DebugLoc dl, SelectionDAG &DAG); 70739217Sgibbs 70839217Sgibbs virtual bool 70918781Sgibbs CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 71039217Sgibbs const SmallVectorImpl<EVT> &OutTys, 71139217Sgibbs const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 71239217Sgibbs SelectionDAG &DAG); 71339217Sgibbs 71418781Sgibbs void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 71518781Sgibbs SelectionDAG &DAG, unsigned NewOp); 71639217Sgibbs 71739217Sgibbs SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 71839217Sgibbs SDValue Chain, 71918781Sgibbs SDValue Dst, SDValue Src, 72039217Sgibbs SDValue Size, unsigned Align, 72139217Sgibbs const Value *DstSV, uint64_t DstSVOff); 72218781Sgibbs SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 72318781Sgibbs SDValue Chain, 72418781Sgibbs SDValue Dst, SDValue Src, 72518781Sgibbs SDValue Size, unsigned Align, 72618781Sgibbs bool AlwaysInline, 72718781Sgibbs const Value *DstSV, uint64_t DstSVOff, 72818781Sgibbs const Value *SrcSV, uint64_t SrcSVOff); 72918781Sgibbs 73039217Sgibbs /// Utility function to emit string processing sse4.2 instructions 73118781Sgibbs /// that return in xmm0. 73218781Sgibbs /// This takes the instruction to expand, the associated machine basic 73318781Sgibbs /// block, the number of args, and whether or not the second arg is 73418781Sgibbs /// in memory or not. 73518781Sgibbs MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 73618781Sgibbs unsigned argNum, bool inMem) const; 73718781Sgibbs 73818781Sgibbs /// Utility function to emit atomic bitwise operations (and, or, xor). 73918781Sgibbs /// It takes the bitwise instruction to expand, the associated machine basic 74018781Sgibbs /// block, and the associated X86 opcodes for reg/reg and reg/imm. 74118781Sgibbs MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 74218781Sgibbs MachineInstr *BInstr, 74318781Sgibbs MachineBasicBlock *BB, 74418781Sgibbs unsigned regOpc, 74518781Sgibbs unsigned immOpc, 74618781Sgibbs unsigned loadOpc, 74718781Sgibbs unsigned cxchgOpc, 74818781Sgibbs unsigned copyOpc, 74918781Sgibbs unsigned notOpc, 75018781Sgibbs unsigned EAXreg, 75118781Sgibbs TargetRegisterClass *RC, 75218781Sgibbs bool invSrc = false) const; 75318781Sgibbs 75418781Sgibbs MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 75518781Sgibbs MachineInstr *BInstr, 75618781Sgibbs MachineBasicBlock *BB, 75718781Sgibbs unsigned regOpcL, 75818781Sgibbs unsigned regOpcH, 75918781Sgibbs unsigned immOpcL, 76018781Sgibbs unsigned immOpcH, 76118781Sgibbs bool invSrc = false) const; 76218781Sgibbs 76318781Sgibbs /// Utility function to emit atomic min and max. It takes the min/max 76418781Sgibbs /// instruction to expand, the associated basic block, and the associated 76518781Sgibbs /// cmov opcode for moving the min or max value. 76618781Sgibbs MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 76718781Sgibbs MachineBasicBlock *BB, 76818781Sgibbs unsigned cmovOpc) const; 76918781Sgibbs 77018781Sgibbs /// Utility function to emit the xmm reg save portion of va_start. 77118781Sgibbs MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 77218781Sgibbs MachineInstr *BInstr, 77318781Sgibbs MachineBasicBlock *BB) const; 77418781Sgibbs 77518781Sgibbs MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 77618781Sgibbs MachineBasicBlock *BB, 77718781Sgibbs DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 77818781Sgibbs 77918781Sgibbs /// Emit nodes that will be selected as "test Op0,Op0", or something 78018781Sgibbs /// equivalent, for use with the given x86 condition code. 78118781Sgibbs SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); 78239217Sgibbs 78318781Sgibbs /// Emit nodes that will be selected as "cmp Op0,Op1", or something 78418781Sgibbs /// equivalent, for use with the given x86 condition code. 78539217Sgibbs SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 78639217Sgibbs SelectionDAG &DAG); 78718781Sgibbs }; 78818781Sgibbs 78939217Sgibbs namespace X86 { 79039217Sgibbs FastISel *createFastISel(MachineFunction &mf, 79139217Sgibbs MachineModuleInfo *mmi, DwarfWriter *dw, 79239217Sgibbs DenseMap<const Value *, unsigned> &, 79339217Sgibbs DenseMap<const BasicBlock *, MachineBasicBlock *> &, 79439217Sgibbs DenseMap<const AllocaInst *, int> & 79518781Sgibbs#ifndef NDEBUG 79618781Sgibbs , SmallSet<Instruction*, 8> & 797241492Sjhb#endif 79839217Sgibbs ); 79918781Sgibbs } 80039217Sgibbs} 80139217Sgibbs 80239217Sgibbs#endif // X86ISELLOWERING_H 80339217Sgibbs