X86MCTargetDesc.cpp revision 296417
1234353Sdim//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10224133Sdim// This file provides X86 specific target descriptions. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14224133Sdim#include "X86MCTargetDesc.h" 15226633Sdim#include "InstPrinter/X86ATTInstPrinter.h" 16226633Sdim#include "InstPrinter/X86IntelInstPrinter.h" 17249423Sdim#include "X86MCAsmInfo.h" 18249423Sdim#include "llvm/ADT/Triple.h" 19226633Sdim#include "llvm/MC/MCCodeGenInfo.h" 20226633Sdim#include "llvm/MC/MCInstrAnalysis.h" 21224133Sdim#include "llvm/MC/MCInstrInfo.h" 22224133Sdim#include "llvm/MC/MCRegisterInfo.h" 23226633Sdim#include "llvm/MC/MCStreamer.h" 24224133Sdim#include "llvm/MC/MCSubtargetInfo.h" 25249423Sdim#include "llvm/MC/MachineLocation.h" 26249423Sdim#include "llvm/Support/ErrorHandling.h" 27224133Sdim#include "llvm/Support/Host.h" 28226633Sdim#include "llvm/Support/TargetRegistry.h" 29224133Sdim 30276479Sdim#if _MSC_VER 31276479Sdim#include <intrin.h> 32276479Sdim#endif 33276479Sdim 34276479Sdimusing namespace llvm; 35276479Sdim 36224133Sdim#define GET_REGINFO_MC_DESC 37224133Sdim#include "X86GenRegisterInfo.inc" 38224133Sdim 39224133Sdim#define GET_INSTRINFO_MC_DESC 40224133Sdim#include "X86GenInstrInfo.inc" 41224133Sdim 42224133Sdim#define GET_SUBTARGETINFO_MC_DESC 43224133Sdim#include "X86GenSubtargetInfo.inc" 44224133Sdim 45288943Sdimstd::string X86_MC::ParseX86Triple(const Triple &TT) { 46226633Sdim std::string FS; 47288943Sdim if (TT.getArch() == Triple::x86_64) 48276479Sdim FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 49288943Sdim else if (TT.getEnvironment() != Triple::CODE16) 50276479Sdim FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 51226633Sdim else 52276479Sdim FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 53276479Sdim 54226633Sdim return FS; 55224133Sdim} 56224133Sdim 57288943Sdimunsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 58276479Sdim if (TT.getArch() == Triple::x86_64) 59226633Sdim return DWARFFlavour::X86_64; 60226633Sdim 61276479Sdim if (TT.isOSDarwin()) 62226633Sdim return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 63276479Sdim if (TT.isOSCygMing()) 64226633Sdim // Unsupported by now, just quick fallback 65226633Sdim return DWARFFlavour::X86_32_Generic; 66226633Sdim return DWARFFlavour::X86_32_Generic; 67226633Sdim} 68226633Sdim 69226633Sdimvoid X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { 70226633Sdim // FIXME: TableGen these. 71226633Sdim for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 72243830Sdim unsigned SEH = MRI->getEncodingValue(Reg); 73226633Sdim MRI->mapLLVMRegToSEHReg(Reg, SEH); 74226633Sdim } 75226633Sdim} 76226633Sdim 77288943SdimMCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 78288943Sdim StringRef CPU, StringRef FS) { 79224133Sdim std::string ArchFS = X86_MC::ParseX86Triple(TT); 80224133Sdim if (!FS.empty()) { 81224133Sdim if (!ArchFS.empty()) 82288943Sdim ArchFS = (Twine(ArchFS) + "," + FS).str(); 83224133Sdim else 84224133Sdim ArchFS = FS; 85224133Sdim } 86224133Sdim 87224133Sdim std::string CPUName = CPU; 88276479Sdim if (CPUName.empty()) 89224133Sdim CPUName = "generic"; 90224133Sdim 91288943Sdim return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 92224133Sdim} 93224133Sdim 94224133Sdimstatic MCInstrInfo *createX86MCInstrInfo() { 95224133Sdim MCInstrInfo *X = new MCInstrInfo(); 96224133Sdim InitX86MCInstrInfo(X); 97224133Sdim return X; 98224133Sdim} 99224133Sdim 100288943Sdimstatic MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 101288943Sdim unsigned RA = (TT.getArch() == Triple::x86_64) 102288943Sdim ? X86::RIP // Should have dwarf #16. 103288943Sdim : X86::EIP; // Should have dwarf #8. 104224133Sdim 105224133Sdim MCRegisterInfo *X = new MCRegisterInfo(); 106288943Sdim InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 107288943Sdim X86_MC::getDwarfRegFlavour(TT, true), RA); 108226633Sdim X86_MC::InitLLVM2SEHRegisterMapping(X); 109224133Sdim return X; 110224133Sdim} 111224133Sdim 112288943Sdimstatic MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 113288943Sdim const Triple &TheTriple) { 114226633Sdim bool is64Bit = TheTriple.getArch() == Triple::x86_64; 115224133Sdim 116226633Sdim MCAsmInfo *MAI; 117276479Sdim if (TheTriple.isOSBinFormatMachO()) { 118226633Sdim if (is64Bit) 119226633Sdim MAI = new X86_64MCAsmInfoDarwin(TheTriple); 120224133Sdim else 121226633Sdim MAI = new X86MCAsmInfoDarwin(TheTriple); 122276479Sdim } else if (TheTriple.isOSBinFormatELF()) { 123243830Sdim // Force the use of an ELF container. 124243830Sdim MAI = new X86ELFMCAsmInfo(TheTriple); 125296417Sdim } else if (TheTriple.isWindowsMSVCEnvironment() || 126296417Sdim TheTriple.isWindowsCoreCLREnvironment()) { 127234353Sdim MAI = new X86MCAsmInfoMicrosoft(TheTriple); 128276479Sdim } else if (TheTriple.isOSCygMing() || 129276479Sdim TheTriple.isWindowsItaniumEnvironment()) { 130234353Sdim MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 131226633Sdim } else { 132243830Sdim // The default is ELF. 133226633Sdim MAI = new X86ELFMCAsmInfo(TheTriple); 134224133Sdim } 135224133Sdim 136226633Sdim // Initialize initial frame state. 137226633Sdim // Calculate amount of bytes used for return address storing 138226633Sdim int stackGrowth = is64Bit ? -8 : -4; 139226633Sdim 140226633Sdim // Initial state of the frame pointer is esp+stackGrowth. 141261991Sdim unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 142261991Sdim MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 143276479Sdim nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 144261991Sdim MAI->addInitialFrameState(Inst); 145226633Sdim 146226633Sdim // Add return address to move list 147261991Sdim unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 148261991Sdim MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 149276479Sdim nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 150261991Sdim MAI->addInitialFrameState(Inst2); 151226633Sdim 152226633Sdim return MAI; 153226633Sdim} 154226633Sdim 155288943Sdimstatic MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, 156234353Sdim CodeModel::Model CM, 157234353Sdim CodeGenOpt::Level OL) { 158226633Sdim MCCodeGenInfo *X = new MCCodeGenInfo(); 159226633Sdim 160288943Sdim bool is64Bit = TT.getArch() == Triple::x86_64; 161226633Sdim 162226633Sdim if (RM == Reloc::Default) { 163226633Sdim // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 164226633Sdim // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 165226633Sdim // use static relocation model by default. 166288943Sdim if (TT.isOSDarwin()) { 167226633Sdim if (is64Bit) 168226633Sdim RM = Reloc::PIC_; 169226633Sdim else 170226633Sdim RM = Reloc::DynamicNoPIC; 171288943Sdim } else if (TT.isOSWindows() && is64Bit) 172226633Sdim RM = Reloc::PIC_; 173226633Sdim else 174226633Sdim RM = Reloc::Static; 175226633Sdim } 176226633Sdim 177226633Sdim // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 178226633Sdim // is defined as a model for code which may be used in static or dynamic 179226633Sdim // executables but not necessarily a shared library. On X86-32 we just 180226633Sdim // compile in -static mode, in x86-64 we use PIC. 181226633Sdim if (RM == Reloc::DynamicNoPIC) { 182226633Sdim if (is64Bit) 183226633Sdim RM = Reloc::PIC_; 184288943Sdim else if (!TT.isOSDarwin()) 185226633Sdim RM = Reloc::Static; 186226633Sdim } 187226633Sdim 188226633Sdim // If we are on Darwin, disallow static relocation model in X86-64 mode, since 189226633Sdim // the Mach-O file format doesn't support it. 190288943Sdim if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit) 191226633Sdim RM = Reloc::PIC_; 192226633Sdim 193226633Sdim // For static codegen, if we're not already set, use Small codegen. 194226633Sdim if (CM == CodeModel::Default) 195226633Sdim CM = CodeModel::Small; 196226633Sdim else if (CM == CodeModel::JITDefault) 197226633Sdim // 64-bit JIT places everything in the same buffer except external funcs. 198226633Sdim CM = is64Bit ? CodeModel::Large : CodeModel::Small; 199226633Sdim 200288943Sdim X->initMCCodeGenInfo(RM, CM, OL); 201226633Sdim return X; 202226633Sdim} 203226633Sdim 204288943Sdimstatic MCInstPrinter *createX86MCInstPrinter(const Triple &T, 205226633Sdim unsigned SyntaxVariant, 206226633Sdim const MCAsmInfo &MAI, 207234353Sdim const MCInstrInfo &MII, 208288943Sdim const MCRegisterInfo &MRI) { 209226633Sdim if (SyntaxVariant == 0) 210288943Sdim return new X86ATTInstPrinter(MAI, MII, MRI); 211226633Sdim if (SyntaxVariant == 1) 212234353Sdim return new X86IntelInstPrinter(MAI, MII, MRI); 213276479Sdim return nullptr; 214226633Sdim} 215226633Sdim 216288943Sdimstatic MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 217261991Sdim MCContext &Ctx) { 218276479Sdim if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64) 219261991Sdim return createX86_64MachORelocationInfo(Ctx); 220261991Sdim else if (TheTriple.isOSBinFormatELF()) 221261991Sdim return createX86_64ELFRelocationInfo(Ctx); 222261991Sdim // Default to the stock relocation info. 223288943Sdim return llvm::createMCRelocationInfo(TheTriple, Ctx); 224261991Sdim} 225261991Sdim 226226633Sdimstatic MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 227226633Sdim return new MCInstrAnalysis(Info); 228226633Sdim} 229226633Sdim 230226633Sdim// Force static initialization. 231226633Sdimextern "C" void LLVMInitializeX86TargetMC() { 232288943Sdim for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { 233288943Sdim // Register the MC asm info. 234288943Sdim RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 235226633Sdim 236288943Sdim // Register the MC codegen info. 237288943Sdim RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); 238226633Sdim 239288943Sdim // Register the MC instruction info. 240288943Sdim TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 241226633Sdim 242288943Sdim // Register the MC register info. 243288943Sdim TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 244226633Sdim 245288943Sdim // Register the MC subtarget info. 246288943Sdim TargetRegistry::RegisterMCSubtargetInfo(*T, 247288943Sdim X86_MC::createX86MCSubtargetInfo); 248226633Sdim 249288943Sdim // Register the MC instruction analyzer. 250288943Sdim TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 251226633Sdim 252288943Sdim // Register the code emitter. 253288943Sdim TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 254226633Sdim 255288943Sdim // Register the object streamer. 256288943Sdim TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 257288943Sdim 258288943Sdim // Register the MCInstPrinter. 259288943Sdim TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 260288943Sdim 261288943Sdim // Register the MC relocation info. 262288943Sdim TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 263288943Sdim } 264288943Sdim 265226633Sdim // Register the asm backend. 266226633Sdim TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 267226633Sdim createX86_32AsmBackend); 268226633Sdim TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 269226633Sdim createX86_64AsmBackend); 270224133Sdim} 271296417Sdim 272296417Sdimunsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, 273296417Sdim bool High) { 274296417Sdim switch (Size) { 275296417Sdim default: return 0; 276296417Sdim case 8: 277296417Sdim if (High) { 278296417Sdim switch (Reg) { 279296417Sdim default: return getX86SubSuperRegisterOrZero(Reg, 64); 280296417Sdim case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 281296417Sdim return X86::SI; 282296417Sdim case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 283296417Sdim return X86::DI; 284296417Sdim case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 285296417Sdim return X86::BP; 286296417Sdim case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 287296417Sdim return X86::SP; 288296417Sdim case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 289296417Sdim return X86::AH; 290296417Sdim case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 291296417Sdim return X86::DH; 292296417Sdim case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 293296417Sdim return X86::CH; 294296417Sdim case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 295296417Sdim return X86::BH; 296296417Sdim } 297296417Sdim } else { 298296417Sdim switch (Reg) { 299296417Sdim default: return 0; 300296417Sdim case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 301296417Sdim return X86::AL; 302296417Sdim case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 303296417Sdim return X86::DL; 304296417Sdim case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 305296417Sdim return X86::CL; 306296417Sdim case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 307296417Sdim return X86::BL; 308296417Sdim case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 309296417Sdim return X86::SIL; 310296417Sdim case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 311296417Sdim return X86::DIL; 312296417Sdim case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 313296417Sdim return X86::BPL; 314296417Sdim case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 315296417Sdim return X86::SPL; 316296417Sdim case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 317296417Sdim return X86::R8B; 318296417Sdim case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 319296417Sdim return X86::R9B; 320296417Sdim case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 321296417Sdim return X86::R10B; 322296417Sdim case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 323296417Sdim return X86::R11B; 324296417Sdim case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 325296417Sdim return X86::R12B; 326296417Sdim case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 327296417Sdim return X86::R13B; 328296417Sdim case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 329296417Sdim return X86::R14B; 330296417Sdim case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 331296417Sdim return X86::R15B; 332296417Sdim } 333296417Sdim } 334296417Sdim case 16: 335296417Sdim switch (Reg) { 336296417Sdim default: return 0; 337296417Sdim case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 338296417Sdim return X86::AX; 339296417Sdim case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 340296417Sdim return X86::DX; 341296417Sdim case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 342296417Sdim return X86::CX; 343296417Sdim case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 344296417Sdim return X86::BX; 345296417Sdim case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 346296417Sdim return X86::SI; 347296417Sdim case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 348296417Sdim return X86::DI; 349296417Sdim case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 350296417Sdim return X86::BP; 351296417Sdim case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 352296417Sdim return X86::SP; 353296417Sdim case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 354296417Sdim return X86::R8W; 355296417Sdim case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 356296417Sdim return X86::R9W; 357296417Sdim case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 358296417Sdim return X86::R10W; 359296417Sdim case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 360296417Sdim return X86::R11W; 361296417Sdim case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 362296417Sdim return X86::R12W; 363296417Sdim case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 364296417Sdim return X86::R13W; 365296417Sdim case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 366296417Sdim return X86::R14W; 367296417Sdim case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 368296417Sdim return X86::R15W; 369296417Sdim } 370296417Sdim case 32: 371296417Sdim switch (Reg) { 372296417Sdim default: return 0; 373296417Sdim case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 374296417Sdim return X86::EAX; 375296417Sdim case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 376296417Sdim return X86::EDX; 377296417Sdim case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 378296417Sdim return X86::ECX; 379296417Sdim case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 380296417Sdim return X86::EBX; 381296417Sdim case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 382296417Sdim return X86::ESI; 383296417Sdim case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 384296417Sdim return X86::EDI; 385296417Sdim case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 386296417Sdim return X86::EBP; 387296417Sdim case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 388296417Sdim return X86::ESP; 389296417Sdim case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 390296417Sdim return X86::R8D; 391296417Sdim case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 392296417Sdim return X86::R9D; 393296417Sdim case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 394296417Sdim return X86::R10D; 395296417Sdim case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 396296417Sdim return X86::R11D; 397296417Sdim case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 398296417Sdim return X86::R12D; 399296417Sdim case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 400296417Sdim return X86::R13D; 401296417Sdim case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 402296417Sdim return X86::R14D; 403296417Sdim case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 404296417Sdim return X86::R15D; 405296417Sdim } 406296417Sdim case 64: 407296417Sdim switch (Reg) { 408296417Sdim default: return 0; 409296417Sdim case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 410296417Sdim return X86::RAX; 411296417Sdim case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 412296417Sdim return X86::RDX; 413296417Sdim case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 414296417Sdim return X86::RCX; 415296417Sdim case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 416296417Sdim return X86::RBX; 417296417Sdim case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 418296417Sdim return X86::RSI; 419296417Sdim case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 420296417Sdim return X86::RDI; 421296417Sdim case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 422296417Sdim return X86::RBP; 423296417Sdim case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 424296417Sdim return X86::RSP; 425296417Sdim case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 426296417Sdim return X86::R8; 427296417Sdim case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 428296417Sdim return X86::R9; 429296417Sdim case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 430296417Sdim return X86::R10; 431296417Sdim case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 432296417Sdim return X86::R11; 433296417Sdim case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 434296417Sdim return X86::R12; 435296417Sdim case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 436296417Sdim return X86::R13; 437296417Sdim case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 438296417Sdim return X86::R14; 439296417Sdim case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 440296417Sdim return X86::R15; 441296417Sdim } 442296417Sdim } 443296417Sdim} 444296417Sdim 445296417Sdimunsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { 446296417Sdim unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 447296417Sdim assert(Res != 0 && "Unexpected register or VT"); 448296417Sdim return Res; 449296417Sdim} 450296417Sdim 451296417Sdim 452