X86MCTargetDesc.cpp revision 288943 
1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides X86 specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86MCTargetDesc.h"
15#include "InstPrinter/X86ATTInstPrinter.h"
16#include "InstPrinter/X86IntelInstPrinter.h"
17#include "X86MCAsmInfo.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/MC/MCCodeGenInfo.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCStreamer.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/MachineLocation.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/Host.h"
28#include "llvm/Support/TargetRegistry.h"
29
30#if _MSC_VER
31#include <intrin.h>
32#endif
33
34using namespace llvm;
35
36#define GET_REGINFO_MC_DESC
37#include "X86GenRegisterInfo.inc"
38
39#define GET_INSTRINFO_MC_DESC
40#include "X86GenInstrInfo.inc"
41
42#define GET_SUBTARGETINFO_MC_DESC
43#include "X86GenSubtargetInfo.inc"
44
45std::string X86_MC::ParseX86Triple(const Triple &TT) {
46  std::string FS;
47  if (TT.getArch() == Triple::x86_64)
48    FS = "+64bit-mode,-32bit-mode,-16bit-mode";
49  else if (TT.getEnvironment() != Triple::CODE16)
50    FS = "-64bit-mode,+32bit-mode,-16bit-mode";
51  else
52    FS = "-64bit-mode,-32bit-mode,+16bit-mode";
53
54  return FS;
55}
56
57unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
58  if (TT.getArch() == Triple::x86_64)
59    return DWARFFlavour::X86_64;
60
61  if (TT.isOSDarwin())
62    return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
63  if (TT.isOSCygMing())
64    // Unsupported by now, just quick fallback
65    return DWARFFlavour::X86_32_Generic;
66  return DWARFFlavour::X86_32_Generic;
67}
68
69void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
70  // FIXME: TableGen these.
71  for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
72    unsigned SEH = MRI->getEncodingValue(Reg);
73    MRI->mapLLVMRegToSEHReg(Reg, SEH);
74  }
75}
76
77MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
78                                                  StringRef CPU, StringRef FS) {
79  std::string ArchFS = X86_MC::ParseX86Triple(TT);
80  if (!FS.empty()) {
81    if (!ArchFS.empty())
82      ArchFS = (Twine(ArchFS) + "," + FS).str();
83    else
84      ArchFS = FS;
85  }
86
87  std::string CPUName = CPU;
88  if (CPUName.empty())
89    CPUName = "generic";
90
91  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
92}
93
94static MCInstrInfo *createX86MCInstrInfo() {
95  MCInstrInfo *X = new MCInstrInfo();
96  InitX86MCInstrInfo(X);
97  return X;
98}
99
100static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
101  unsigned RA = (TT.getArch() == Triple::x86_64)
102                    ? X86::RIP  // Should have dwarf #16.
103                    : X86::EIP; // Should have dwarf #8.
104
105  MCRegisterInfo *X = new MCRegisterInfo();
106  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
107                        X86_MC::getDwarfRegFlavour(TT, true), RA);
108  X86_MC::InitLLVM2SEHRegisterMapping(X);
109  return X;
110}
111
112static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
113                                     const Triple &TheTriple) {
114  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
115
116  MCAsmInfo *MAI;
117  if (TheTriple.isOSBinFormatMachO()) {
118    if (is64Bit)
119      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
120    else
121      MAI = new X86MCAsmInfoDarwin(TheTriple);
122  } else if (TheTriple.isOSBinFormatELF()) {
123    // Force the use of an ELF container.
124    MAI = new X86ELFMCAsmInfo(TheTriple);
125  } else if (TheTriple.isWindowsMSVCEnvironment()) {
126    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
127  } else if (TheTriple.isOSCygMing() ||
128             TheTriple.isWindowsItaniumEnvironment()) {
129    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
130  } else {
131    // The default is ELF.
132    MAI = new X86ELFMCAsmInfo(TheTriple);
133  }
134
135  // Initialize initial frame state.
136  // Calculate amount of bytes used for return address storing
137  int stackGrowth = is64Bit ? -8 : -4;
138
139  // Initial state of the frame pointer is esp+stackGrowth.
140  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
141  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
142      nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
143  MAI->addInitialFrameState(Inst);
144
145  // Add return address to move list
146  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
147  MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
148      nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
149  MAI->addInitialFrameState(Inst2);
150
151  return MAI;
152}
153
154static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
155                                             CodeModel::Model CM,
156                                             CodeGenOpt::Level OL) {
157  MCCodeGenInfo *X = new MCCodeGenInfo();
158
159  bool is64Bit = TT.getArch() == Triple::x86_64;
160
161  if (RM == Reloc::Default) {
162    // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
163    // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
164    // use static relocation model by default.
165    if (TT.isOSDarwin()) {
166      if (is64Bit)
167        RM = Reloc::PIC_;
168      else
169        RM = Reloc::DynamicNoPIC;
170    } else if (TT.isOSWindows() && is64Bit)
171      RM = Reloc::PIC_;
172    else
173      RM = Reloc::Static;
174  }
175
176  // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
177  // is defined as a model for code which may be used in static or dynamic
178  // executables but not necessarily a shared library. On X86-32 we just
179  // compile in -static mode, in x86-64 we use PIC.
180  if (RM == Reloc::DynamicNoPIC) {
181    if (is64Bit)
182      RM = Reloc::PIC_;
183    else if (!TT.isOSDarwin())
184      RM = Reloc::Static;
185  }
186
187  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
188  // the Mach-O file format doesn't support it.
189  if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
190    RM = Reloc::PIC_;
191
192  // For static codegen, if we're not already set, use Small codegen.
193  if (CM == CodeModel::Default)
194    CM = CodeModel::Small;
195  else if (CM == CodeModel::JITDefault)
196    // 64-bit JIT places everything in the same buffer except external funcs.
197    CM = is64Bit ? CodeModel::Large : CodeModel::Small;
198
199  X->initMCCodeGenInfo(RM, CM, OL);
200  return X;
201}
202
203static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
204                                             unsigned SyntaxVariant,
205                                             const MCAsmInfo &MAI,
206                                             const MCInstrInfo &MII,
207                                             const MCRegisterInfo &MRI) {
208  if (SyntaxVariant == 0)
209    return new X86ATTInstPrinter(MAI, MII, MRI);
210  if (SyntaxVariant == 1)
211    return new X86IntelInstPrinter(MAI, MII, MRI);
212  return nullptr;
213}
214
215static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
216                                                   MCContext &Ctx) {
217  if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
218    return createX86_64MachORelocationInfo(Ctx);
219  else if (TheTriple.isOSBinFormatELF())
220    return createX86_64ELFRelocationInfo(Ctx);
221  // Default to the stock relocation info.
222  return llvm::createMCRelocationInfo(TheTriple, Ctx);
223}
224
225static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
226  return new MCInstrAnalysis(Info);
227}
228
229// Force static initialization.
230extern "C" void LLVMInitializeX86TargetMC() {
231  for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
232    // Register the MC asm info.
233    RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
234
235    // Register the MC codegen info.
236    RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
237
238    // Register the MC instruction info.
239    TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
240
241    // Register the MC register info.
242    TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
243
244    // Register the MC subtarget info.
245    TargetRegistry::RegisterMCSubtargetInfo(*T,
246                                            X86_MC::createX86MCSubtargetInfo);
247
248    // Register the MC instruction analyzer.
249    TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
250
251    // Register the code emitter.
252    TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
253
254    // Register the object streamer.
255    TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
256
257    // Register the MCInstPrinter.
258    TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
259
260    // Register the MC relocation info.
261    TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
262  }
263
264  // Register the asm backend.
265  TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
266                                       createX86_32AsmBackend);
267  TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
268                                       createX86_64AsmBackend);
269}
270