SystemZInstrInfo.cpp revision 288943
1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the SystemZ implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SystemZInstrInfo.h" 15#include "SystemZInstrBuilder.h" 16#include "SystemZTargetMachine.h" 17#include "llvm/CodeGen/LiveVariables.h" 18#include "llvm/CodeGen/MachineRegisterInfo.h" 19 20using namespace llvm; 21 22#define GET_INSTRINFO_CTOR_DTOR 23#define GET_INSTRMAP_INFO 24#include "SystemZGenInstrInfo.inc" 25 26// Return a mask with Count low bits set. 27static uint64_t allOnes(unsigned int Count) { 28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1; 29} 30 31// Reg should be a 32-bit GPR. Return true if it is a high register rather 32// than a low register. 33static bool isHighReg(unsigned int Reg) { 34 if (SystemZ::GRH32BitRegClass.contains(Reg)) 35 return true; 36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32"); 37 return false; 38} 39 40// Pin the vtable to this file. 41void SystemZInstrInfo::anchor() {} 42 43SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti) 44 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP), 45 RI(), STI(sti) { 46} 47 48// MI is a 128-bit load or store. Split it into two 64-bit loads or stores, 49// each having the opcode given by NewOpcode. 50void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, 51 unsigned NewOpcode) const { 52 MachineBasicBlock *MBB = MI->getParent(); 53 MachineFunction &MF = *MBB->getParent(); 54 55 // Get two load or store instructions. Use the original instruction for one 56 // of them (arbitrarily the second here) and create a clone for the other. 57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); 58 MBB->insert(MI, EarlierMI); 59 60 // Set up the two 64-bit registers. 61 MachineOperand &HighRegOp = EarlierMI->getOperand(0); 62 MachineOperand &LowRegOp = MI->getOperand(0); 63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64)); 64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64)); 65 66 // The address in the first (high) instruction is already correct. 67 // Adjust the offset in the second (low) instruction. 68 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2); 69 MachineOperand &LowOffsetOp = MI->getOperand(2); 70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); 71 72 // Set the opcodes. 73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 75 assert(HighOpcode && LowOpcode && "Both offsets should be in range"); 76 77 EarlierMI->setDesc(get(HighOpcode)); 78 MI->setDesc(get(LowOpcode)); 79} 80 81// Split ADJDYNALLOC instruction MI. 82void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const { 83 MachineBasicBlock *MBB = MI->getParent(); 84 MachineFunction &MF = *MBB->getParent(); 85 MachineFrameInfo *MFFrame = MF.getFrameInfo(); 86 MachineOperand &OffsetMO = MI->getOperand(2); 87 88 uint64_t Offset = (MFFrame->getMaxCallFrameSize() + 89 SystemZMC::CallFrameSize + 90 OffsetMO.getImm()); 91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); 92 assert(NewOpcode && "No support for huge argument lists yet"); 93 MI->setDesc(get(NewOpcode)); 94 OffsetMO.setImm(Offset); 95} 96 97// MI is an RI-style pseudo instruction. Replace it with LowOpcode 98// if the first operand is a low GR32 and HighOpcode if the first operand 99// is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand 100// and HighOpcode takes an unsigned 32-bit operand. In those cases, 101// MI has the same kind of operand as LowOpcode, so needs to be converted 102// if HighOpcode is used. 103void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode, 104 unsigned HighOpcode, 105 bool ConvertHigh) const { 106 unsigned Reg = MI->getOperand(0).getReg(); 107 bool IsHigh = isHighReg(Reg); 108 MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode)); 109 if (IsHigh && ConvertHigh) 110 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm())); 111} 112 113// MI is a three-operand RIE-style pseudo instruction. Replace it with 114// LowOpcode3 if the registers are both low GR32s, otherwise use a move 115// followed by HighOpcode or LowOpcode, depending on whether the target 116// is a high or low GR32. 117void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode, 118 unsigned LowOpcodeK, 119 unsigned HighOpcode) const { 120 unsigned DestReg = MI->getOperand(0).getReg(); 121 unsigned SrcReg = MI->getOperand(1).getReg(); 122 bool DestIsHigh = isHighReg(DestReg); 123 bool SrcIsHigh = isHighReg(SrcReg); 124 if (!DestIsHigh && !SrcIsHigh) 125 MI->setDesc(get(LowOpcodeK)); 126 else { 127 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(), 128 DestReg, SrcReg, SystemZ::LR, 32, 129 MI->getOperand(1).isKill()); 130 MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); 131 MI->getOperand(1).setReg(DestReg); 132 } 133} 134 135// MI is an RXY-style pseudo instruction. Replace it with LowOpcode 136// if the first operand is a low GR32 and HighOpcode if the first operand 137// is a high GR32. 138void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, 139 unsigned HighOpcode) const { 140 unsigned Reg = MI->getOperand(0).getReg(); 141 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode, 142 MI->getOperand(2).getImm()); 143 MI->setDesc(get(Opcode)); 144} 145 146// MI is an RR-style pseudo instruction that zero-extends the low Size bits 147// of one GRX32 into another. Replace it with LowOpcode if both operands 148// are low registers, otherwise use RISB[LH]G. 149void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, 150 unsigned Size) const { 151 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(), 152 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(), 153 LowOpcode, Size, MI->getOperand(1).isKill()); 154 MI->eraseFromParent(); 155} 156 157// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR 158// DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg 159// are low registers, otherwise use RISB[LH]G. Size is the number of bits 160// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR). 161// KillSrc is true if this move is the last use of SrcReg. 162void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB, 163 MachineBasicBlock::iterator MBBI, 164 DebugLoc DL, unsigned DestReg, 165 unsigned SrcReg, unsigned LowLowOpcode, 166 unsigned Size, bool KillSrc) const { 167 unsigned Opcode; 168 bool DestIsHigh = isHighReg(DestReg); 169 bool SrcIsHigh = isHighReg(SrcReg); 170 if (DestIsHigh && SrcIsHigh) 171 Opcode = SystemZ::RISBHH; 172 else if (DestIsHigh && !SrcIsHigh) 173 Opcode = SystemZ::RISBHL; 174 else if (!DestIsHigh && SrcIsHigh) 175 Opcode = SystemZ::RISBLH; 176 else { 177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) 178 .addReg(SrcReg, getKillRegState(KillSrc)); 179 return; 180 } 181 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0); 182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) 183 .addReg(DestReg, RegState::Undef) 184 .addReg(SrcReg, getKillRegState(KillSrc)) 185 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate); 186} 187 188// If MI is a simple load or store for a frame object, return the register 189// it loads or stores and set FrameIndex to the index of the frame object. 190// Return 0 otherwise. 191// 192// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores. 193static int isSimpleMove(const MachineInstr *MI, int &FrameIndex, 194 unsigned Flag) { 195 const MCInstrDesc &MCID = MI->getDesc(); 196 if ((MCID.TSFlags & Flag) && 197 MI->getOperand(1).isFI() && 198 MI->getOperand(2).getImm() == 0 && 199 MI->getOperand(3).getReg() == 0) { 200 FrameIndex = MI->getOperand(1).getIndex(); 201 return MI->getOperand(0).getReg(); 202 } 203 return 0; 204} 205 206unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 207 int &FrameIndex) const { 208 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad); 209} 210 211unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 212 int &FrameIndex) const { 213 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore); 214} 215 216bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI, 217 int &DestFrameIndex, 218 int &SrcFrameIndex) const { 219 // Check for MVC 0(Length,FI1),0(FI2) 220 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo(); 221 if (MI->getOpcode() != SystemZ::MVC || 222 !MI->getOperand(0).isFI() || 223 MI->getOperand(1).getImm() != 0 || 224 !MI->getOperand(3).isFI() || 225 MI->getOperand(4).getImm() != 0) 226 return false; 227 228 // Check that Length covers the full slots. 229 int64_t Length = MI->getOperand(2).getImm(); 230 unsigned FI1 = MI->getOperand(0).getIndex(); 231 unsigned FI2 = MI->getOperand(3).getIndex(); 232 if (MFI->getObjectSize(FI1) != Length || 233 MFI->getObjectSize(FI2) != Length) 234 return false; 235 236 DestFrameIndex = FI1; 237 SrcFrameIndex = FI2; 238 return true; 239} 240 241bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 242 MachineBasicBlock *&TBB, 243 MachineBasicBlock *&FBB, 244 SmallVectorImpl<MachineOperand> &Cond, 245 bool AllowModify) const { 246 // Most of the code and comments here are boilerplate. 247 248 // Start from the bottom of the block and work up, examining the 249 // terminator instructions. 250 MachineBasicBlock::iterator I = MBB.end(); 251 while (I != MBB.begin()) { 252 --I; 253 if (I->isDebugValue()) 254 continue; 255 256 // Working from the bottom, when we see a non-terminator instruction, we're 257 // done. 258 if (!isUnpredicatedTerminator(I)) 259 break; 260 261 // A terminator that isn't a branch can't easily be handled by this 262 // analysis. 263 if (!I->isBranch()) 264 return true; 265 266 // Can't handle indirect branches. 267 SystemZII::Branch Branch(getBranchInfo(I)); 268 if (!Branch.Target->isMBB()) 269 return true; 270 271 // Punt on compound branches. 272 if (Branch.Type != SystemZII::BranchNormal) 273 return true; 274 275 if (Branch.CCMask == SystemZ::CCMASK_ANY) { 276 // Handle unconditional branches. 277 if (!AllowModify) { 278 TBB = Branch.Target->getMBB(); 279 continue; 280 } 281 282 // If the block has any instructions after a JMP, delete them. 283 while (std::next(I) != MBB.end()) 284 std::next(I)->eraseFromParent(); 285 286 Cond.clear(); 287 FBB = nullptr; 288 289 // Delete the JMP if it's equivalent to a fall-through. 290 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) { 291 TBB = nullptr; 292 I->eraseFromParent(); 293 I = MBB.end(); 294 continue; 295 } 296 297 // TBB is used to indicate the unconditinal destination. 298 TBB = Branch.Target->getMBB(); 299 continue; 300 } 301 302 // Working from the bottom, handle the first conditional branch. 303 if (Cond.empty()) { 304 // FIXME: add X86-style branch swap 305 FBB = TBB; 306 TBB = Branch.Target->getMBB(); 307 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid)); 308 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask)); 309 continue; 310 } 311 312 // Handle subsequent conditional branches. 313 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch"); 314 315 // Only handle the case where all conditional branches branch to the same 316 // destination. 317 if (TBB != Branch.Target->getMBB()) 318 return true; 319 320 // If the conditions are the same, we can leave them alone. 321 unsigned OldCCValid = Cond[0].getImm(); 322 unsigned OldCCMask = Cond[1].getImm(); 323 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask) 324 continue; 325 326 // FIXME: Try combining conditions like X86 does. Should be easy on Z! 327 return false; 328 } 329 330 return false; 331} 332 333unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 334 // Most of the code and comments here are boilerplate. 335 MachineBasicBlock::iterator I = MBB.end(); 336 unsigned Count = 0; 337 338 while (I != MBB.begin()) { 339 --I; 340 if (I->isDebugValue()) 341 continue; 342 if (!I->isBranch()) 343 break; 344 if (!getBranchInfo(I).Target->isMBB()) 345 break; 346 // Remove the branch. 347 I->eraseFromParent(); 348 I = MBB.end(); 349 ++Count; 350 } 351 352 return Count; 353} 354 355bool SystemZInstrInfo:: 356ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 357 assert(Cond.size() == 2 && "Invalid condition"); 358 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm()); 359 return false; 360} 361 362unsigned 363SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 364 MachineBasicBlock *FBB, 365 ArrayRef<MachineOperand> Cond, 366 DebugLoc DL) const { 367 // In this function we output 32-bit branches, which should always 368 // have enough range. They can be shortened and relaxed by later code 369 // in the pipeline, if desired. 370 371 // Shouldn't be a fall through. 372 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 373 assert((Cond.size() == 2 || Cond.size() == 0) && 374 "SystemZ branch conditions have one component!"); 375 376 if (Cond.empty()) { 377 // Unconditional branch? 378 assert(!FBB && "Unconditional branch with multiple successors!"); 379 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB); 380 return 1; 381 } 382 383 // Conditional branch. 384 unsigned Count = 0; 385 unsigned CCValid = Cond[0].getImm(); 386 unsigned CCMask = Cond[1].getImm(); 387 BuildMI(&MBB, DL, get(SystemZ::BRC)) 388 .addImm(CCValid).addImm(CCMask).addMBB(TBB); 389 ++Count; 390 391 if (FBB) { 392 // Two-way Conditional branch. Insert the second branch. 393 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB); 394 ++Count; 395 } 396 return Count; 397} 398 399bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI, 400 unsigned &SrcReg, unsigned &SrcReg2, 401 int &Mask, int &Value) const { 402 assert(MI->isCompare() && "Caller should have checked for a comparison"); 403 404 if (MI->getNumExplicitOperands() == 2 && 405 MI->getOperand(0).isReg() && 406 MI->getOperand(1).isImm()) { 407 SrcReg = MI->getOperand(0).getReg(); 408 SrcReg2 = 0; 409 Value = MI->getOperand(1).getImm(); 410 Mask = ~0; 411 return true; 412 } 413 414 return false; 415} 416 417// If Reg is a virtual register, return its definition, otherwise return null. 418static MachineInstr *getDef(unsigned Reg, 419 const MachineRegisterInfo *MRI) { 420 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 421 return nullptr; 422 return MRI->getUniqueVRegDef(Reg); 423} 424 425// Return true if MI is a shift of type Opcode by Imm bits. 426static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) { 427 return (MI->getOpcode() == Opcode && 428 !MI->getOperand(2).getReg() && 429 MI->getOperand(3).getImm() == Imm); 430} 431 432// If the destination of MI has no uses, delete it as dead. 433static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) { 434 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg())) 435 MI->eraseFromParent(); 436} 437 438// Compare compares SrcReg against zero. Check whether SrcReg contains 439// the result of an IPM sequence whose input CC survives until Compare, 440// and whether Compare is therefore redundant. Delete it and return 441// true if so. 442static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, 443 const MachineRegisterInfo *MRI, 444 const TargetRegisterInfo *TRI) { 445 MachineInstr *LGFR = nullptr; 446 MachineInstr *RLL = getDef(SrcReg, MRI); 447 if (RLL && RLL->getOpcode() == SystemZ::LGFR) { 448 LGFR = RLL; 449 RLL = getDef(LGFR->getOperand(1).getReg(), MRI); 450 } 451 if (!RLL || !isShift(RLL, SystemZ::RLL, 31)) 452 return false; 453 454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); 455 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC)) 456 return false; 457 458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); 459 if (!IPM || IPM->getOpcode() != SystemZ::IPM) 460 return false; 461 462 // Check that there are no assignments to CC between the IPM and Compare, 463 if (IPM->getParent() != Compare->getParent()) 464 return false; 465 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare; 466 for (++MBBI; MBBI != MBBE; ++MBBI) { 467 MachineInstr *MI = MBBI; 468 if (MI->modifiesRegister(SystemZ::CC, TRI)) 469 return false; 470 } 471 472 Compare->eraseFromParent(); 473 if (LGFR) 474 eraseIfDead(LGFR, MRI); 475 eraseIfDead(RLL, MRI); 476 eraseIfDead(SRL, MRI); 477 eraseIfDead(IPM, MRI); 478 479 return true; 480} 481 482bool 483SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare, 484 unsigned SrcReg, unsigned SrcReg2, 485 int Mask, int Value, 486 const MachineRegisterInfo *MRI) const { 487 assert(!SrcReg2 && "Only optimizing constant comparisons so far"); 488 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0; 489 if (Value == 0 && 490 !IsLogical && 491 removeIPMBasedCompare(Compare, SrcReg, MRI, &RI)) 492 return true; 493 return false; 494} 495 496// If Opcode is a move that has a conditional variant, return that variant, 497// otherwise return 0. 498static unsigned getConditionalMove(unsigned Opcode) { 499 switch (Opcode) { 500 case SystemZ::LR: return SystemZ::LOCR; 501 case SystemZ::LGR: return SystemZ::LOCGR; 502 default: return 0; 503 } 504} 505 506bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const { 507 unsigned Opcode = MI->getOpcode(); 508 if (STI.hasLoadStoreOnCond() && 509 getConditionalMove(Opcode)) 510 return true; 511 return false; 512} 513 514bool SystemZInstrInfo:: 515isProfitableToIfCvt(MachineBasicBlock &MBB, 516 unsigned NumCycles, unsigned ExtraPredCycles, 517 const BranchProbability &Probability) const { 518 // For now only convert single instructions. 519 return NumCycles == 1; 520} 521 522bool SystemZInstrInfo:: 523isProfitableToIfCvt(MachineBasicBlock &TMBB, 524 unsigned NumCyclesT, unsigned ExtraPredCyclesT, 525 MachineBasicBlock &FMBB, 526 unsigned NumCyclesF, unsigned ExtraPredCyclesF, 527 const BranchProbability &Probability) const { 528 // For now avoid converting mutually-exclusive cases. 529 return false; 530} 531 532bool SystemZInstrInfo:: 533PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const { 534 assert(Pred.size() == 2 && "Invalid condition"); 535 unsigned CCValid = Pred[0].getImm(); 536 unsigned CCMask = Pred[1].getImm(); 537 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate"); 538 unsigned Opcode = MI->getOpcode(); 539 if (STI.hasLoadStoreOnCond()) { 540 if (unsigned CondOpcode = getConditionalMove(Opcode)) { 541 MI->setDesc(get(CondOpcode)); 542 MachineInstrBuilder(*MI->getParent()->getParent(), MI) 543 .addImm(CCValid).addImm(CCMask) 544 .addReg(SystemZ::CC, RegState::Implicit); 545 return true; 546 } 547 } 548 return false; 549} 550 551void 552SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 553 MachineBasicBlock::iterator MBBI, DebugLoc DL, 554 unsigned DestReg, unsigned SrcReg, 555 bool KillSrc) const { 556 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too. 557 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) { 558 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64), 559 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc); 560 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64), 561 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc); 562 return; 563 } 564 565 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) { 566 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc); 567 return; 568 } 569 570 // Everything else needs only one instruction. 571 unsigned Opcode; 572 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg)) 573 Opcode = SystemZ::LGR; 574 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg)) 575 Opcode = SystemZ::LER; 576 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg)) 577 Opcode = SystemZ::LDR; 578 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg)) 579 Opcode = SystemZ::LXR; 580 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg)) 581 Opcode = SystemZ::VLR32; 582 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg)) 583 Opcode = SystemZ::VLR64; 584 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg)) 585 Opcode = SystemZ::VLR; 586 else 587 llvm_unreachable("Impossible reg-to-reg copy"); 588 589 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) 590 .addReg(SrcReg, getKillRegState(KillSrc)); 591} 592 593void 594SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 595 MachineBasicBlock::iterator MBBI, 596 unsigned SrcReg, bool isKill, 597 int FrameIdx, 598 const TargetRegisterClass *RC, 599 const TargetRegisterInfo *TRI) const { 600 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 601 602 // Callers may expect a single instruction, so keep 128-bit moves 603 // together for now and lower them after register allocation. 604 unsigned LoadOpcode, StoreOpcode; 605 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode); 606 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode)) 607 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx); 608} 609 610void 611SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 612 MachineBasicBlock::iterator MBBI, 613 unsigned DestReg, int FrameIdx, 614 const TargetRegisterClass *RC, 615 const TargetRegisterInfo *TRI) const { 616 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 617 618 // Callers may expect a single instruction, so keep 128-bit moves 619 // together for now and lower them after register allocation. 620 unsigned LoadOpcode, StoreOpcode; 621 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode); 622 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg), 623 FrameIdx); 624} 625 626// Return true if MI is a simple load or store with a 12-bit displacement 627// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores. 628static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) { 629 const MCInstrDesc &MCID = MI->getDesc(); 630 return ((MCID.TSFlags & Flag) && 631 isUInt<12>(MI->getOperand(2).getImm()) && 632 MI->getOperand(3).getReg() == 0); 633} 634 635namespace { 636struct LogicOp { 637 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} 638 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) 639 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} 640 641 explicit operator bool() const { return RegSize; } 642 643 unsigned RegSize, ImmLSB, ImmSize; 644}; 645} // end anonymous namespace 646 647static LogicOp interpretAndImmediate(unsigned Opcode) { 648 switch (Opcode) { 649 case SystemZ::NILMux: return LogicOp(32, 0, 16); 650 case SystemZ::NIHMux: return LogicOp(32, 16, 16); 651 case SystemZ::NILL64: return LogicOp(64, 0, 16); 652 case SystemZ::NILH64: return LogicOp(64, 16, 16); 653 case SystemZ::NIHL64: return LogicOp(64, 32, 16); 654 case SystemZ::NIHH64: return LogicOp(64, 48, 16); 655 case SystemZ::NIFMux: return LogicOp(32, 0, 32); 656 case SystemZ::NILF64: return LogicOp(64, 0, 32); 657 case SystemZ::NIHF64: return LogicOp(64, 32, 32); 658 default: return LogicOp(); 659 } 660} 661 662// Used to return from convertToThreeAddress after replacing two-address 663// instruction OldMI with three-address instruction NewMI. 664static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI, 665 MachineInstr *NewMI, 666 LiveVariables *LV) { 667 if (LV) { 668 unsigned NumOps = OldMI->getNumOperands(); 669 for (unsigned I = 1; I < NumOps; ++I) { 670 MachineOperand &Op = OldMI->getOperand(I); 671 if (Op.isReg() && Op.isKill()) 672 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI); 673 } 674 } 675 return NewMI; 676} 677 678MachineInstr * 679SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 680 MachineBasicBlock::iterator &MBBI, 681 LiveVariables *LV) const { 682 MachineInstr *MI = MBBI; 683 MachineBasicBlock *MBB = MI->getParent(); 684 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 685 686 unsigned Opcode = MI->getOpcode(); 687 unsigned NumOps = MI->getNumOperands(); 688 689 // Try to convert something like SLL into SLLK, if supported. 690 // We prefer to keep the two-operand form where possible both 691 // because it tends to be shorter and because some instructions 692 // have memory forms that can be used during spilling. 693 if (STI.hasDistinctOps()) { 694 MachineOperand &Dest = MI->getOperand(0); 695 MachineOperand &Src = MI->getOperand(1); 696 unsigned DestReg = Dest.getReg(); 697 unsigned SrcReg = Src.getReg(); 698 // AHIMux is only really a three-operand instruction when both operands 699 // are low registers. Try to constrain both operands to be low if 700 // possible. 701 if (Opcode == SystemZ::AHIMux && 702 TargetRegisterInfo::isVirtualRegister(DestReg) && 703 TargetRegisterInfo::isVirtualRegister(SrcReg) && 704 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) && 705 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) { 706 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass); 707 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass); 708 } 709 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode); 710 if (ThreeOperandOpcode >= 0) { 711 MachineInstrBuilder MIB = 712 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode)) 713 .addOperand(Dest); 714 // Keep the kill state, but drop the tied flag. 715 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()); 716 // Keep the remaining operands as-is. 717 for (unsigned I = 2; I < NumOps; ++I) 718 MIB.addOperand(MI->getOperand(I)); 719 return finishConvertToThreeAddress(MI, MIB, LV); 720 } 721 } 722 723 // Try to convert an AND into an RISBG-type instruction. 724 if (LogicOp And = interpretAndImmediate(Opcode)) { 725 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB; 726 // AND IMMEDIATE leaves the other bits of the register unchanged. 727 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); 728 unsigned Start, End; 729 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { 730 unsigned NewOpcode; 731 if (And.RegSize == 64) { 732 NewOpcode = SystemZ::RISBG; 733 // Prefer RISBGN if available, since it does not clobber CC. 734 if (STI.hasMiscellaneousExtensions()) 735 NewOpcode = SystemZ::RISBGN; 736 } else { 737 NewOpcode = SystemZ::RISBMux; 738 Start &= 31; 739 End &= 31; 740 } 741 MachineOperand &Dest = MI->getOperand(0); 742 MachineOperand &Src = MI->getOperand(1); 743 MachineInstrBuilder MIB = 744 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode)) 745 .addOperand(Dest).addReg(0) 746 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()) 747 .addImm(Start).addImm(End + 128).addImm(0); 748 return finishConvertToThreeAddress(MI, MIB, LV); 749 } 750 } 751 return nullptr; 752} 753 754MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl( 755 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, 756 MachineBasicBlock::iterator InsertPt, int FrameIndex) const { 757 const MachineFrameInfo *MFI = MF.getFrameInfo(); 758 unsigned Size = MFI->getObjectSize(FrameIndex); 759 unsigned Opcode = MI->getOpcode(); 760 761 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 762 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) && 763 isInt<8>(MI->getOperand(2).getImm()) && 764 !MI->getOperand(3).getReg()) { 765 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST 766 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(), 767 get(SystemZ::AGSI)) 768 .addFrameIndex(FrameIndex) 769 .addImm(0) 770 .addImm(MI->getOperand(2).getImm()); 771 } 772 return nullptr; 773 } 774 775 // All other cases require a single operand. 776 if (Ops.size() != 1) 777 return nullptr; 778 779 unsigned OpNum = Ops[0]; 780 assert(Size == MF.getRegInfo() 781 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() && 782 "Invalid size combination"); 783 784 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && 785 OpNum == 0 && 786 isInt<8>(MI->getOperand(2).getImm())) { 787 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST 788 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI); 789 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(), 790 get(Opcode)) 791 .addFrameIndex(FrameIndex) 792 .addImm(0) 793 .addImm(MI->getOperand(2).getImm()); 794 } 795 796 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) { 797 bool Op0IsGPR = (Opcode == SystemZ::LGDR); 798 bool Op1IsGPR = (Opcode == SystemZ::LDGR); 799 // If we're spilling the destination of an LDGR or LGDR, store the 800 // source register instead. 801 if (OpNum == 0) { 802 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD; 803 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(), 804 get(StoreOpcode)) 805 .addOperand(MI->getOperand(1)) 806 .addFrameIndex(FrameIndex) 807 .addImm(0) 808 .addReg(0); 809 } 810 // If we're spilling the source of an LDGR or LGDR, load the 811 // destination register instead. 812 if (OpNum == 1) { 813 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD; 814 unsigned Dest = MI->getOperand(0).getReg(); 815 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(), 816 get(LoadOpcode), Dest) 817 .addFrameIndex(FrameIndex) 818 .addImm(0) 819 .addReg(0); 820 } 821 } 822 823 // Look for cases where the source of a simple store or the destination 824 // of a simple load is being spilled. Try to use MVC instead. 825 // 826 // Although MVC is in practice a fast choice in these cases, it is still 827 // logically a bytewise copy. This means that we cannot use it if the 828 // load or store is volatile. We also wouldn't be able to use MVC if 829 // the two memories partially overlap, but that case cannot occur here, 830 // because we know that one of the memories is a full frame index. 831 // 832 // For performance reasons, we also want to avoid using MVC if the addresses 833 // might be equal. We don't worry about that case here, because spill slot 834 // coloring happens later, and because we have special code to remove 835 // MVCs that turn out to be redundant. 836 if (OpNum == 0 && MI->hasOneMemOperand()) { 837 MachineMemOperand *MMO = *MI->memoperands_begin(); 838 if (MMO->getSize() == Size && !MMO->isVolatile()) { 839 // Handle conversion of loads. 840 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) { 841 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(), 842 get(SystemZ::MVC)) 843 .addFrameIndex(FrameIndex) 844 .addImm(0) 845 .addImm(Size) 846 .addOperand(MI->getOperand(1)) 847 .addImm(MI->getOperand(2).getImm()) 848 .addMemOperand(MMO); 849 } 850 // Handle conversion of stores. 851 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) { 852 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(), 853 get(SystemZ::MVC)) 854 .addOperand(MI->getOperand(1)) 855 .addImm(MI->getOperand(2).getImm()) 856 .addImm(Size) 857 .addFrameIndex(FrameIndex) 858 .addImm(0) 859 .addMemOperand(MMO); 860 } 861 } 862 } 863 864 // If the spilled operand is the final one, try to change <INSN>R 865 // into <INSN>. 866 int MemOpcode = SystemZ::getMemOpcode(Opcode); 867 if (MemOpcode >= 0) { 868 unsigned NumOps = MI->getNumExplicitOperands(); 869 if (OpNum == NumOps - 1) { 870 const MCInstrDesc &MemDesc = get(MemOpcode); 871 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags); 872 assert(AccessBytes != 0 && "Size of access should be known"); 873 assert(AccessBytes <= Size && "Access outside the frame index"); 874 uint64_t Offset = Size - AccessBytes; 875 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt, 876 MI->getDebugLoc(), get(MemOpcode)); 877 for (unsigned I = 0; I < OpNum; ++I) 878 MIB.addOperand(MI->getOperand(I)); 879 MIB.addFrameIndex(FrameIndex).addImm(Offset); 880 if (MemDesc.TSFlags & SystemZII::HasIndex) 881 MIB.addReg(0); 882 return MIB; 883 } 884 } 885 886 return nullptr; 887} 888 889MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl( 890 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, 891 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const { 892 return nullptr; 893} 894 895bool 896SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 897 switch (MI->getOpcode()) { 898 case SystemZ::L128: 899 splitMove(MI, SystemZ::LG); 900 return true; 901 902 case SystemZ::ST128: 903 splitMove(MI, SystemZ::STG); 904 return true; 905 906 case SystemZ::LX: 907 splitMove(MI, SystemZ::LD); 908 return true; 909 910 case SystemZ::STX: 911 splitMove(MI, SystemZ::STD); 912 return true; 913 914 case SystemZ::LBMux: 915 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH); 916 return true; 917 918 case SystemZ::LHMux: 919 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH); 920 return true; 921 922 case SystemZ::LLCRMux: 923 expandZExtPseudo(MI, SystemZ::LLCR, 8); 924 return true; 925 926 case SystemZ::LLHRMux: 927 expandZExtPseudo(MI, SystemZ::LLHR, 16); 928 return true; 929 930 case SystemZ::LLCMux: 931 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH); 932 return true; 933 934 case SystemZ::LLHMux: 935 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH); 936 return true; 937 938 case SystemZ::LMux: 939 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH); 940 return true; 941 942 case SystemZ::STCMux: 943 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH); 944 return true; 945 946 case SystemZ::STHMux: 947 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH); 948 return true; 949 950 case SystemZ::STMux: 951 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH); 952 return true; 953 954 case SystemZ::LHIMux: 955 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true); 956 return true; 957 958 case SystemZ::IIFMux: 959 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false); 960 return true; 961 962 case SystemZ::IILMux: 963 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false); 964 return true; 965 966 case SystemZ::IIHMux: 967 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false); 968 return true; 969 970 case SystemZ::NIFMux: 971 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false); 972 return true; 973 974 case SystemZ::NILMux: 975 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false); 976 return true; 977 978 case SystemZ::NIHMux: 979 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false); 980 return true; 981 982 case SystemZ::OIFMux: 983 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false); 984 return true; 985 986 case SystemZ::OILMux: 987 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false); 988 return true; 989 990 case SystemZ::OIHMux: 991 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false); 992 return true; 993 994 case SystemZ::XIFMux: 995 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false); 996 return true; 997 998 case SystemZ::TMLMux: 999 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false); 1000 return true; 1001 1002 case SystemZ::TMHMux: 1003 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false); 1004 return true; 1005 1006 case SystemZ::AHIMux: 1007 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false); 1008 return true; 1009 1010 case SystemZ::AHIMuxK: 1011 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH); 1012 return true; 1013 1014 case SystemZ::AFIMux: 1015 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false); 1016 return true; 1017 1018 case SystemZ::CFIMux: 1019 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false); 1020 return true; 1021 1022 case SystemZ::CLFIMux: 1023 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false); 1024 return true; 1025 1026 case SystemZ::CMux: 1027 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF); 1028 return true; 1029 1030 case SystemZ::CLMux: 1031 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF); 1032 return true; 1033 1034 case SystemZ::RISBMux: { 1035 bool DestIsHigh = isHighReg(MI->getOperand(0).getReg()); 1036 bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg()); 1037 if (SrcIsHigh == DestIsHigh) 1038 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL)); 1039 else { 1040 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH)); 1041 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32); 1042 } 1043 return true; 1044 } 1045 1046 case SystemZ::ADJDYNALLOC: 1047 splitAdjDynAlloc(MI); 1048 return true; 1049 1050 default: 1051 return false; 1052 } 1053} 1054 1055uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const { 1056 if (MI->getOpcode() == TargetOpcode::INLINEASM) { 1057 const MachineFunction *MF = MI->getParent()->getParent(); 1058 const char *AsmStr = MI->getOperand(0).getSymbolName(); 1059 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 1060 } 1061 return MI->getDesc().getSize(); 1062} 1063 1064SystemZII::Branch 1065SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const { 1066 switch (MI->getOpcode()) { 1067 case SystemZ::BR: 1068 case SystemZ::J: 1069 case SystemZ::JG: 1070 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY, 1071 SystemZ::CCMASK_ANY, &MI->getOperand(0)); 1072 1073 case SystemZ::BRC: 1074 case SystemZ::BRCL: 1075 return SystemZII::Branch(SystemZII::BranchNormal, 1076 MI->getOperand(0).getImm(), 1077 MI->getOperand(1).getImm(), &MI->getOperand(2)); 1078 1079 case SystemZ::BRCT: 1080 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP, 1081 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2)); 1082 1083 case SystemZ::BRCTG: 1084 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP, 1085 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2)); 1086 1087 case SystemZ::CIJ: 1088 case SystemZ::CRJ: 1089 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP, 1090 MI->getOperand(2).getImm(), &MI->getOperand(3)); 1091 1092 case SystemZ::CLIJ: 1093 case SystemZ::CLRJ: 1094 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP, 1095 MI->getOperand(2).getImm(), &MI->getOperand(3)); 1096 1097 case SystemZ::CGIJ: 1098 case SystemZ::CGRJ: 1099 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP, 1100 MI->getOperand(2).getImm(), &MI->getOperand(3)); 1101 1102 case SystemZ::CLGIJ: 1103 case SystemZ::CLGRJ: 1104 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP, 1105 MI->getOperand(2).getImm(), &MI->getOperand(3)); 1106 1107 default: 1108 llvm_unreachable("Unrecognized branch opcode"); 1109 } 1110} 1111 1112void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, 1113 unsigned &LoadOpcode, 1114 unsigned &StoreOpcode) const { 1115 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) { 1116 LoadOpcode = SystemZ::L; 1117 StoreOpcode = SystemZ::ST; 1118 } else if (RC == &SystemZ::GRH32BitRegClass) { 1119 LoadOpcode = SystemZ::LFH; 1120 StoreOpcode = SystemZ::STFH; 1121 } else if (RC == &SystemZ::GRX32BitRegClass) { 1122 LoadOpcode = SystemZ::LMux; 1123 StoreOpcode = SystemZ::STMux; 1124 } else if (RC == &SystemZ::GR64BitRegClass || 1125 RC == &SystemZ::ADDR64BitRegClass) { 1126 LoadOpcode = SystemZ::LG; 1127 StoreOpcode = SystemZ::STG; 1128 } else if (RC == &SystemZ::GR128BitRegClass || 1129 RC == &SystemZ::ADDR128BitRegClass) { 1130 LoadOpcode = SystemZ::L128; 1131 StoreOpcode = SystemZ::ST128; 1132 } else if (RC == &SystemZ::FP32BitRegClass) { 1133 LoadOpcode = SystemZ::LE; 1134 StoreOpcode = SystemZ::STE; 1135 } else if (RC == &SystemZ::FP64BitRegClass) { 1136 LoadOpcode = SystemZ::LD; 1137 StoreOpcode = SystemZ::STD; 1138 } else if (RC == &SystemZ::FP128BitRegClass) { 1139 LoadOpcode = SystemZ::LX; 1140 StoreOpcode = SystemZ::STX; 1141 } else if (RC == &SystemZ::VR32BitRegClass) { 1142 LoadOpcode = SystemZ::VL32; 1143 StoreOpcode = SystemZ::VST32; 1144 } else if (RC == &SystemZ::VR64BitRegClass) { 1145 LoadOpcode = SystemZ::VL64; 1146 StoreOpcode = SystemZ::VST64; 1147 } else if (RC == &SystemZ::VF128BitRegClass || 1148 RC == &SystemZ::VR128BitRegClass) { 1149 LoadOpcode = SystemZ::VL; 1150 StoreOpcode = SystemZ::VST; 1151 } else 1152 llvm_unreachable("Unsupported regclass to load or store"); 1153} 1154 1155unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode, 1156 int64_t Offset) const { 1157 const MCInstrDesc &MCID = get(Opcode); 1158 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); 1159 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) { 1160 // Get the instruction to use for unsigned 12-bit displacements. 1161 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode); 1162 if (Disp12Opcode >= 0) 1163 return Disp12Opcode; 1164 1165 // All address-related instructions can use unsigned 12-bit 1166 // displacements. 1167 return Opcode; 1168 } 1169 if (isInt<20>(Offset) && isInt<20>(Offset2)) { 1170 // Get the instruction to use for signed 20-bit displacements. 1171 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode); 1172 if (Disp20Opcode >= 0) 1173 return Disp20Opcode; 1174 1175 // Check whether Opcode allows signed 20-bit displacements. 1176 if (MCID.TSFlags & SystemZII::Has20BitOffset) 1177 return Opcode; 1178 } 1179 return 0; 1180} 1181 1182unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const { 1183 switch (Opcode) { 1184 case SystemZ::L: return SystemZ::LT; 1185 case SystemZ::LY: return SystemZ::LT; 1186 case SystemZ::LG: return SystemZ::LTG; 1187 case SystemZ::LGF: return SystemZ::LTGF; 1188 case SystemZ::LR: return SystemZ::LTR; 1189 case SystemZ::LGFR: return SystemZ::LTGFR; 1190 case SystemZ::LGR: return SystemZ::LTGR; 1191 case SystemZ::LER: return SystemZ::LTEBR; 1192 case SystemZ::LDR: return SystemZ::LTDBR; 1193 case SystemZ::LXR: return SystemZ::LTXBR; 1194 // On zEC12 we prefer to use RISBGN. But if there is a chance to 1195 // actually use the condition code, we may turn it back into RISGB. 1196 // Note that RISBG is not really a "load-and-test" instruction, 1197 // but sets the same condition code values, so is OK to use here. 1198 case SystemZ::RISBGN: return SystemZ::RISBG; 1199 default: return 0; 1200 } 1201} 1202 1203// Return true if Mask matches the regexp 0*1+0*, given that zero masks 1204// have already been filtered out. Store the first set bit in LSB and 1205// the number of set bits in Length if so. 1206static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) { 1207 unsigned First = findFirstSet(Mask); 1208 uint64_t Top = (Mask >> First) + 1; 1209 if ((Top & -Top) == Top) { 1210 LSB = First; 1211 Length = findFirstSet(Top); 1212 return true; 1213 } 1214 return false; 1215} 1216 1217bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize, 1218 unsigned &Start, unsigned &End) const { 1219 // Reject trivial all-zero masks. 1220 Mask &= allOnes(BitSize); 1221 if (Mask == 0) 1222 return false; 1223 1224 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of 1225 // the msb and End specifies the index of the lsb. 1226 unsigned LSB, Length; 1227 if (isStringOfOnes(Mask, LSB, Length)) { 1228 Start = 63 - (LSB + Length - 1); 1229 End = 63 - LSB; 1230 return true; 1231 } 1232 1233 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb 1234 // of the low 1s and End specifies the lsb of the high 1s. 1235 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) { 1236 assert(LSB > 0 && "Bottom bit must be set"); 1237 assert(LSB + Length < BitSize && "Top bit must be set"); 1238 Start = 63 - (LSB - 1); 1239 End = 63 - (LSB + Length); 1240 return true; 1241 } 1242 1243 return false; 1244} 1245 1246unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode, 1247 const MachineInstr *MI) const { 1248 switch (Opcode) { 1249 case SystemZ::CR: 1250 return SystemZ::CRJ; 1251 case SystemZ::CGR: 1252 return SystemZ::CGRJ; 1253 case SystemZ::CHI: 1254 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0; 1255 case SystemZ::CGHI: 1256 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0; 1257 case SystemZ::CLR: 1258 return SystemZ::CLRJ; 1259 case SystemZ::CLGR: 1260 return SystemZ::CLGRJ; 1261 case SystemZ::CLFI: 1262 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0; 1263 case SystemZ::CLGFI: 1264 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0; 1265 default: 1266 return 0; 1267 } 1268} 1269 1270void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB, 1271 MachineBasicBlock::iterator MBBI, 1272 unsigned Reg, uint64_t Value) const { 1273 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 1274 unsigned Opcode; 1275 if (isInt<16>(Value)) 1276 Opcode = SystemZ::LGHI; 1277 else if (SystemZ::isImmLL(Value)) 1278 Opcode = SystemZ::LLILL; 1279 else if (SystemZ::isImmLH(Value)) { 1280 Opcode = SystemZ::LLILH; 1281 Value >>= 16; 1282 } else { 1283 assert(isInt<32>(Value) && "Huge values not handled yet"); 1284 Opcode = SystemZ::LGFI; 1285 } 1286 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value); 1287} 1288