1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZInstrInfo.h"
15#include "SystemZInstrBuilder.h"
16#include "SystemZTargetMachine.h"
17#include "llvm/CodeGen/LiveVariables.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19
20using namespace llvm;
21
22#define GET_INSTRINFO_CTOR_DTOR
23#define GET_INSTRMAP_INFO
24#include "SystemZGenInstrInfo.inc"
25
26// Return a mask with Count low bits set.
27static uint64_t allOnes(unsigned int Count) {
28  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
29}
30
31// Reg should be a 32-bit GPR.  Return true if it is a high register rather
32// than a low register.
33static bool isHighReg(unsigned int Reg) {
34  if (SystemZ::GRH32BitRegClass.contains(Reg))
35    return true;
36  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
37  return false;
38}
39
40// Pin the vtable to this file.
41void SystemZInstrInfo::anchor() {}
42
43SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
44  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
45    RI(), STI(sti) {
46}
47
48// MI is a 128-bit load or store.  Split it into two 64-bit loads or stores,
49// each having the opcode given by NewOpcode.
50void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
51                                 unsigned NewOpcode) const {
52  MachineBasicBlock *MBB = MI->getParent();
53  MachineFunction &MF = *MBB->getParent();
54
55  // Get two load or store instructions.  Use the original instruction for one
56  // of them (arbitrarily the second here) and create a clone for the other.
57  MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
58  MBB->insert(MI, EarlierMI);
59
60  // Set up the two 64-bit registers.
61  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
62  MachineOperand &LowRegOp = MI->getOperand(0);
63  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
65
66  // The address in the first (high) instruction is already correct.
67  // Adjust the offset in the second (low) instruction.
68  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
69  MachineOperand &LowOffsetOp = MI->getOperand(2);
70  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
71
72 // Clear the kill flags for the base and index registers in the first
73 // instruction.
74  EarlierMI->getOperand(1).setIsKill(false);
75  EarlierMI->getOperand(3).setIsKill(false);
76
77  // Set the opcodes.
78  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
79  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
80  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
81
82  EarlierMI->setDesc(get(HighOpcode));
83  MI->setDesc(get(LowOpcode));
84}
85
86// Split ADJDYNALLOC instruction MI.
87void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
88  MachineBasicBlock *MBB = MI->getParent();
89  MachineFunction &MF = *MBB->getParent();
90  MachineFrameInfo *MFFrame = MF.getFrameInfo();
91  MachineOperand &OffsetMO = MI->getOperand(2);
92
93  uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
94                     SystemZMC::CallFrameSize +
95                     OffsetMO.getImm());
96  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
97  assert(NewOpcode && "No support for huge argument lists yet");
98  MI->setDesc(get(NewOpcode));
99  OffsetMO.setImm(Offset);
100}
101
102// MI is an RI-style pseudo instruction.  Replace it with LowOpcode
103// if the first operand is a low GR32 and HighOpcode if the first operand
104// is a high GR32.  ConvertHigh is true if LowOpcode takes a signed operand
105// and HighOpcode takes an unsigned 32-bit operand.  In those cases,
106// MI has the same kind of operand as LowOpcode, so needs to be converted
107// if HighOpcode is used.
108void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
109                                      unsigned HighOpcode,
110                                      bool ConvertHigh) const {
111  unsigned Reg = MI->getOperand(0).getReg();
112  bool IsHigh = isHighReg(Reg);
113  MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
114  if (IsHigh && ConvertHigh)
115    MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
116}
117
118// MI is a three-operand RIE-style pseudo instruction.  Replace it with
119// LowOpcodeK if the registers are both low GR32s, otherwise use a move
120// followed by HighOpcode or LowOpcode, depending on whether the target
121// is a high or low GR32.
122void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
123                                       unsigned LowOpcodeK,
124                                       unsigned HighOpcode) const {
125  unsigned DestReg = MI->getOperand(0).getReg();
126  unsigned SrcReg = MI->getOperand(1).getReg();
127  bool DestIsHigh = isHighReg(DestReg);
128  bool SrcIsHigh = isHighReg(SrcReg);
129  if (!DestIsHigh && !SrcIsHigh)
130    MI->setDesc(get(LowOpcodeK));
131  else {
132    emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
133                  DestReg, SrcReg, SystemZ::LR, 32,
134                  MI->getOperand(1).isKill());
135    MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
136    MI->getOperand(1).setReg(DestReg);
137    MI->tieOperands(0, 1);
138  }
139}
140
141// MI is an RXY-style pseudo instruction.  Replace it with LowOpcode
142// if the first operand is a low GR32 and HighOpcode if the first operand
143// is a high GR32.
144void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
145                                       unsigned HighOpcode) const {
146  unsigned Reg = MI->getOperand(0).getReg();
147  unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
148                                       MI->getOperand(2).getImm());
149  MI->setDesc(get(Opcode));
150}
151
152// MI is an RR-style pseudo instruction that zero-extends the low Size bits
153// of one GRX32 into another.  Replace it with LowOpcode if both operands
154// are low registers, otherwise use RISB[LH]G.
155void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
156                                        unsigned Size) const {
157  emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
158                MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
159                LowOpcode, Size, MI->getOperand(1).isKill());
160  MI->eraseFromParent();
161}
162
163// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
164// DestReg before MBBI in MBB.  Use LowLowOpcode when both DestReg and SrcReg
165// are low registers, otherwise use RISB[LH]G.  Size is the number of bits
166// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
167// KillSrc is true if this move is the last use of SrcReg.
168void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
169                                     MachineBasicBlock::iterator MBBI,
170                                     DebugLoc DL, unsigned DestReg,
171                                     unsigned SrcReg, unsigned LowLowOpcode,
172                                     unsigned Size, bool KillSrc) const {
173  unsigned Opcode;
174  bool DestIsHigh = isHighReg(DestReg);
175  bool SrcIsHigh = isHighReg(SrcReg);
176  if (DestIsHigh && SrcIsHigh)
177    Opcode = SystemZ::RISBHH;
178  else if (DestIsHigh && !SrcIsHigh)
179    Opcode = SystemZ::RISBHL;
180  else if (!DestIsHigh && SrcIsHigh)
181    Opcode = SystemZ::RISBLH;
182  else {
183    BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
184      .addReg(SrcReg, getKillRegState(KillSrc));
185    return;
186  }
187  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
188  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
189    .addReg(DestReg, RegState::Undef)
190    .addReg(SrcReg, getKillRegState(KillSrc))
191    .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
192}
193
194// If MI is a simple load or store for a frame object, return the register
195// it loads or stores and set FrameIndex to the index of the frame object.
196// Return 0 otherwise.
197//
198// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
199static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
200                        unsigned Flag) {
201  const MCInstrDesc &MCID = MI->getDesc();
202  if ((MCID.TSFlags & Flag) &&
203      MI->getOperand(1).isFI() &&
204      MI->getOperand(2).getImm() == 0 &&
205      MI->getOperand(3).getReg() == 0) {
206    FrameIndex = MI->getOperand(1).getIndex();
207    return MI->getOperand(0).getReg();
208  }
209  return 0;
210}
211
212unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
213                                               int &FrameIndex) const {
214  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
215}
216
217unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
218                                              int &FrameIndex) const {
219  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
220}
221
222bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
223                                       int &DestFrameIndex,
224                                       int &SrcFrameIndex) const {
225  // Check for MVC 0(Length,FI1),0(FI2)
226  const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
227  if (MI->getOpcode() != SystemZ::MVC ||
228      !MI->getOperand(0).isFI() ||
229      MI->getOperand(1).getImm() != 0 ||
230      !MI->getOperand(3).isFI() ||
231      MI->getOperand(4).getImm() != 0)
232    return false;
233
234  // Check that Length covers the full slots.
235  int64_t Length = MI->getOperand(2).getImm();
236  unsigned FI1 = MI->getOperand(0).getIndex();
237  unsigned FI2 = MI->getOperand(3).getIndex();
238  if (MFI->getObjectSize(FI1) != Length ||
239      MFI->getObjectSize(FI2) != Length)
240    return false;
241
242  DestFrameIndex = FI1;
243  SrcFrameIndex = FI2;
244  return true;
245}
246
247bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
248                                     MachineBasicBlock *&TBB,
249                                     MachineBasicBlock *&FBB,
250                                     SmallVectorImpl<MachineOperand> &Cond,
251                                     bool AllowModify) const {
252  // Most of the code and comments here are boilerplate.
253
254  // Start from the bottom of the block and work up, examining the
255  // terminator instructions.
256  MachineBasicBlock::iterator I = MBB.end();
257  while (I != MBB.begin()) {
258    --I;
259    if (I->isDebugValue())
260      continue;
261
262    // Working from the bottom, when we see a non-terminator instruction, we're
263    // done.
264    if (!isUnpredicatedTerminator(I))
265      break;
266
267    // A terminator that isn't a branch can't easily be handled by this
268    // analysis.
269    if (!I->isBranch())
270      return true;
271
272    // Can't handle indirect branches.
273    SystemZII::Branch Branch(getBranchInfo(I));
274    if (!Branch.Target->isMBB())
275      return true;
276
277    // Punt on compound branches.
278    if (Branch.Type != SystemZII::BranchNormal)
279      return true;
280
281    if (Branch.CCMask == SystemZ::CCMASK_ANY) {
282      // Handle unconditional branches.
283      if (!AllowModify) {
284        TBB = Branch.Target->getMBB();
285        continue;
286      }
287
288      // If the block has any instructions after a JMP, delete them.
289      while (std::next(I) != MBB.end())
290        std::next(I)->eraseFromParent();
291
292      Cond.clear();
293      FBB = nullptr;
294
295      // Delete the JMP if it's equivalent to a fall-through.
296      if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
297        TBB = nullptr;
298        I->eraseFromParent();
299        I = MBB.end();
300        continue;
301      }
302
303      // TBB is used to indicate the unconditinal destination.
304      TBB = Branch.Target->getMBB();
305      continue;
306    }
307
308    // Working from the bottom, handle the first conditional branch.
309    if (Cond.empty()) {
310      // FIXME: add X86-style branch swap
311      FBB = TBB;
312      TBB = Branch.Target->getMBB();
313      Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
314      Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
315      continue;
316    }
317
318    // Handle subsequent conditional branches.
319    assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
320
321    // Only handle the case where all conditional branches branch to the same
322    // destination.
323    if (TBB != Branch.Target->getMBB())
324      return true;
325
326    // If the conditions are the same, we can leave them alone.
327    unsigned OldCCValid = Cond[0].getImm();
328    unsigned OldCCMask = Cond[1].getImm();
329    if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
330      continue;
331
332    // FIXME: Try combining conditions like X86 does.  Should be easy on Z!
333    return false;
334  }
335
336  return false;
337}
338
339unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
340  // Most of the code and comments here are boilerplate.
341  MachineBasicBlock::iterator I = MBB.end();
342  unsigned Count = 0;
343
344  while (I != MBB.begin()) {
345    --I;
346    if (I->isDebugValue())
347      continue;
348    if (!I->isBranch())
349      break;
350    if (!getBranchInfo(I).Target->isMBB())
351      break;
352    // Remove the branch.
353    I->eraseFromParent();
354    I = MBB.end();
355    ++Count;
356  }
357
358  return Count;
359}
360
361bool SystemZInstrInfo::
362ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
363  assert(Cond.size() == 2 && "Invalid condition");
364  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
365  return false;
366}
367
368unsigned
369SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
370                               MachineBasicBlock *FBB,
371                               ArrayRef<MachineOperand> Cond,
372                               DebugLoc DL) const {
373  // In this function we output 32-bit branches, which should always
374  // have enough range.  They can be shortened and relaxed by later code
375  // in the pipeline, if desired.
376
377  // Shouldn't be a fall through.
378  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
379  assert((Cond.size() == 2 || Cond.size() == 0) &&
380         "SystemZ branch conditions have one component!");
381
382  if (Cond.empty()) {
383    // Unconditional branch?
384    assert(!FBB && "Unconditional branch with multiple successors!");
385    BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
386    return 1;
387  }
388
389  // Conditional branch.
390  unsigned Count = 0;
391  unsigned CCValid = Cond[0].getImm();
392  unsigned CCMask = Cond[1].getImm();
393  BuildMI(&MBB, DL, get(SystemZ::BRC))
394    .addImm(CCValid).addImm(CCMask).addMBB(TBB);
395  ++Count;
396
397  if (FBB) {
398    // Two-way Conditional branch. Insert the second branch.
399    BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
400    ++Count;
401  }
402  return Count;
403}
404
405bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
406                                      unsigned &SrcReg, unsigned &SrcReg2,
407                                      int &Mask, int &Value) const {
408  assert(MI->isCompare() && "Caller should have checked for a comparison");
409
410  if (MI->getNumExplicitOperands() == 2 &&
411      MI->getOperand(0).isReg() &&
412      MI->getOperand(1).isImm()) {
413    SrcReg = MI->getOperand(0).getReg();
414    SrcReg2 = 0;
415    Value = MI->getOperand(1).getImm();
416    Mask = ~0;
417    return true;
418  }
419
420  return false;
421}
422
423// If Reg is a virtual register, return its definition, otherwise return null.
424static MachineInstr *getDef(unsigned Reg,
425                            const MachineRegisterInfo *MRI) {
426  if (TargetRegisterInfo::isPhysicalRegister(Reg))
427    return nullptr;
428  return MRI->getUniqueVRegDef(Reg);
429}
430
431// Return true if MI is a shift of type Opcode by Imm bits.
432static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
433  return (MI->getOpcode() == Opcode &&
434          !MI->getOperand(2).getReg() &&
435          MI->getOperand(3).getImm() == Imm);
436}
437
438// If the destination of MI has no uses, delete it as dead.
439static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
440  if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
441    MI->eraseFromParent();
442}
443
444// Compare compares SrcReg against zero.  Check whether SrcReg contains
445// the result of an IPM sequence whose input CC survives until Compare,
446// and whether Compare is therefore redundant.  Delete it and return
447// true if so.
448static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
449                                  const MachineRegisterInfo *MRI,
450                                  const TargetRegisterInfo *TRI) {
451  MachineInstr *LGFR = nullptr;
452  MachineInstr *RLL = getDef(SrcReg, MRI);
453  if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
454    LGFR = RLL;
455    RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
456  }
457  if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
458    return false;
459
460  MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
461  if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
462    return false;
463
464  MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
465  if (!IPM || IPM->getOpcode() != SystemZ::IPM)
466    return false;
467
468  // Check that there are no assignments to CC between the IPM and Compare,
469  if (IPM->getParent() != Compare->getParent())
470    return false;
471  MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
472  for (++MBBI; MBBI != MBBE; ++MBBI) {
473    MachineInstr *MI = MBBI;
474    if (MI->modifiesRegister(SystemZ::CC, TRI))
475      return false;
476  }
477
478  Compare->eraseFromParent();
479  if (LGFR)
480    eraseIfDead(LGFR, MRI);
481  eraseIfDead(RLL, MRI);
482  eraseIfDead(SRL, MRI);
483  eraseIfDead(IPM, MRI);
484
485  return true;
486}
487
488bool
489SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
490                                       unsigned SrcReg, unsigned SrcReg2,
491                                       int Mask, int Value,
492                                       const MachineRegisterInfo *MRI) const {
493  assert(!SrcReg2 && "Only optimizing constant comparisons so far");
494  bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
495  return Value == 0 && !IsLogical &&
496         removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
497}
498
499// If Opcode is a move that has a conditional variant, return that variant,
500// otherwise return 0.
501static unsigned getConditionalMove(unsigned Opcode) {
502  switch (Opcode) {
503  case SystemZ::LR:  return SystemZ::LOCR;
504  case SystemZ::LGR: return SystemZ::LOCGR;
505  default:           return 0;
506  }
507}
508
509bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
510  unsigned Opcode = MI->getOpcode();
511  return STI.hasLoadStoreOnCond() && getConditionalMove(Opcode);
512}
513
514bool SystemZInstrInfo::
515isProfitableToIfCvt(MachineBasicBlock &MBB,
516                    unsigned NumCycles, unsigned ExtraPredCycles,
517                    BranchProbability Probability) const {
518  // For now only convert single instructions.
519  return NumCycles == 1;
520}
521
522bool SystemZInstrInfo::
523isProfitableToIfCvt(MachineBasicBlock &TMBB,
524                    unsigned NumCyclesT, unsigned ExtraPredCyclesT,
525                    MachineBasicBlock &FMBB,
526                    unsigned NumCyclesF, unsigned ExtraPredCyclesF,
527                    BranchProbability Probability) const {
528  // For now avoid converting mutually-exclusive cases.
529  return false;
530}
531
532bool SystemZInstrInfo::
533PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
534  assert(Pred.size() == 2 && "Invalid condition");
535  unsigned CCValid = Pred[0].getImm();
536  unsigned CCMask = Pred[1].getImm();
537  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
538  unsigned Opcode = MI->getOpcode();
539  if (STI.hasLoadStoreOnCond()) {
540    if (unsigned CondOpcode = getConditionalMove(Opcode)) {
541      MI->setDesc(get(CondOpcode));
542      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
543        .addImm(CCValid).addImm(CCMask)
544        .addReg(SystemZ::CC, RegState::Implicit);
545      return true;
546    }
547  }
548  return false;
549}
550
551void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
552                                   MachineBasicBlock::iterator MBBI,
553                                   DebugLoc DL, unsigned DestReg,
554                                   unsigned SrcReg, bool KillSrc) const {
555  // Split 128-bit GPR moves into two 64-bit moves.  This handles ADDR128 too.
556  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
557    copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
558                RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
559    copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
560                RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
561    return;
562  }
563
564  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
565    emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
566    return;
567  }
568
569  // Everything else needs only one instruction.
570  unsigned Opcode;
571  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
572    Opcode = SystemZ::LGR;
573  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
574    Opcode = SystemZ::LER;
575  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
576    Opcode = SystemZ::LDR;
577  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
578    Opcode = SystemZ::LXR;
579  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
580    Opcode = SystemZ::VLR32;
581  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
582    Opcode = SystemZ::VLR64;
583  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
584    Opcode = SystemZ::VLR;
585  else
586    llvm_unreachable("Impossible reg-to-reg copy");
587
588  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
589    .addReg(SrcReg, getKillRegState(KillSrc));
590}
591
592void SystemZInstrInfo::storeRegToStackSlot(
593    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
594    bool isKill, int FrameIdx, const TargetRegisterClass *RC,
595    const TargetRegisterInfo *TRI) const {
596  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
597
598  // Callers may expect a single instruction, so keep 128-bit moves
599  // together for now and lower them after register allocation.
600  unsigned LoadOpcode, StoreOpcode;
601  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
602  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
603                        .addReg(SrcReg, getKillRegState(isKill)),
604                    FrameIdx);
605}
606
607void SystemZInstrInfo::loadRegFromStackSlot(
608    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
609    int FrameIdx, const TargetRegisterClass *RC,
610    const TargetRegisterInfo *TRI) const {
611  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
612
613  // Callers may expect a single instruction, so keep 128-bit moves
614  // together for now and lower them after register allocation.
615  unsigned LoadOpcode, StoreOpcode;
616  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
617  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
618                    FrameIdx);
619}
620
621// Return true if MI is a simple load or store with a 12-bit displacement
622// and no index.  Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
623static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
624  const MCInstrDesc &MCID = MI->getDesc();
625  return ((MCID.TSFlags & Flag) &&
626          isUInt<12>(MI->getOperand(2).getImm()) &&
627          MI->getOperand(3).getReg() == 0);
628}
629
630namespace {
631struct LogicOp {
632  LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
633  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
634    : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
635
636  explicit operator bool() const { return RegSize; }
637
638  unsigned RegSize, ImmLSB, ImmSize;
639};
640} // end anonymous namespace
641
642static LogicOp interpretAndImmediate(unsigned Opcode) {
643  switch (Opcode) {
644  case SystemZ::NILMux: return LogicOp(32,  0, 16);
645  case SystemZ::NIHMux: return LogicOp(32, 16, 16);
646  case SystemZ::NILL64: return LogicOp(64,  0, 16);
647  case SystemZ::NILH64: return LogicOp(64, 16, 16);
648  case SystemZ::NIHL64: return LogicOp(64, 32, 16);
649  case SystemZ::NIHH64: return LogicOp(64, 48, 16);
650  case SystemZ::NIFMux: return LogicOp(32,  0, 32);
651  case SystemZ::NILF64: return LogicOp(64,  0, 32);
652  case SystemZ::NIHF64: return LogicOp(64, 32, 32);
653  default:              return LogicOp();
654  }
655}
656
657// Used to return from convertToThreeAddress after replacing two-address
658// instruction OldMI with three-address instruction NewMI.
659static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
660                                                 MachineInstr *NewMI,
661                                                 LiveVariables *LV) {
662  if (LV) {
663    unsigned NumOps = OldMI->getNumOperands();
664    for (unsigned I = 1; I < NumOps; ++I) {
665      MachineOperand &Op = OldMI->getOperand(I);
666      if (Op.isReg() && Op.isKill())
667        LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
668    }
669  }
670  return NewMI;
671}
672
673MachineInstr *
674SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
675                                        MachineBasicBlock::iterator &MBBI,
676                                        LiveVariables *LV) const {
677  MachineInstr *MI = MBBI;
678  MachineBasicBlock *MBB = MI->getParent();
679  MachineFunction *MF = MBB->getParent();
680  MachineRegisterInfo &MRI = MF->getRegInfo();
681
682  unsigned Opcode = MI->getOpcode();
683  unsigned NumOps = MI->getNumOperands();
684
685  // Try to convert something like SLL into SLLK, if supported.
686  // We prefer to keep the two-operand form where possible both
687  // because it tends to be shorter and because some instructions
688  // have memory forms that can be used during spilling.
689  if (STI.hasDistinctOps()) {
690    MachineOperand &Dest = MI->getOperand(0);
691    MachineOperand &Src = MI->getOperand(1);
692    unsigned DestReg = Dest.getReg();
693    unsigned SrcReg = Src.getReg();
694    // AHIMux is only really a three-operand instruction when both operands
695    // are low registers.  Try to constrain both operands to be low if
696    // possible.
697    if (Opcode == SystemZ::AHIMux &&
698        TargetRegisterInfo::isVirtualRegister(DestReg) &&
699        TargetRegisterInfo::isVirtualRegister(SrcReg) &&
700        MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
701        MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
702      MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
703      MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
704    }
705    int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
706    if (ThreeOperandOpcode >= 0) {
707      // Create three address instruction without adding the implicit
708      // operands. Those will instead be copied over from the original
709      // instruction by the loop below.
710      MachineInstrBuilder MIB(*MF,
711                              MF->CreateMachineInstr(get(ThreeOperandOpcode),
712                                    MI->getDebugLoc(), /*NoImplicit=*/true));
713      MIB.addOperand(Dest);
714      // Keep the kill state, but drop the tied flag.
715      MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
716      // Keep the remaining operands as-is.
717      for (unsigned I = 2; I < NumOps; ++I)
718        MIB.addOperand(MI->getOperand(I));
719      MBB->insert(MI, MIB);
720      return finishConvertToThreeAddress(MI, MIB, LV);
721    }
722  }
723
724  // Try to convert an AND into an RISBG-type instruction.
725  if (LogicOp And = interpretAndImmediate(Opcode)) {
726    uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
727    // AND IMMEDIATE leaves the other bits of the register unchanged.
728    Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
729    unsigned Start, End;
730    if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
731      unsigned NewOpcode;
732      if (And.RegSize == 64) {
733        NewOpcode = SystemZ::RISBG;
734        // Prefer RISBGN if available, since it does not clobber CC.
735        if (STI.hasMiscellaneousExtensions())
736          NewOpcode = SystemZ::RISBGN;
737      } else {
738        NewOpcode = SystemZ::RISBMux;
739        Start &= 31;
740        End &= 31;
741      }
742      MachineOperand &Dest = MI->getOperand(0);
743      MachineOperand &Src = MI->getOperand(1);
744      MachineInstrBuilder MIB =
745        BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
746        .addOperand(Dest).addReg(0)
747        .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
748        .addImm(Start).addImm(End + 128).addImm(0);
749      return finishConvertToThreeAddress(MI, MIB, LV);
750    }
751  }
752  return nullptr;
753}
754
755MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
756    MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
757    MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
758  const MachineFrameInfo *MFI = MF.getFrameInfo();
759  unsigned Size = MFI->getObjectSize(FrameIndex);
760  unsigned Opcode = MI->getOpcode();
761
762  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
763    if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
764        isInt<8>(MI->getOperand(2).getImm()) &&
765        !MI->getOperand(3).getReg()) {
766      // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
767      return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
768                     get(SystemZ::AGSI))
769          .addFrameIndex(FrameIndex)
770          .addImm(0)
771          .addImm(MI->getOperand(2).getImm());
772    }
773    return nullptr;
774  }
775
776  // All other cases require a single operand.
777  if (Ops.size() != 1)
778    return nullptr;
779
780  unsigned OpNum = Ops[0];
781  assert(Size == MF.getRegInfo()
782         .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
783         "Invalid size combination");
784
785  if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
786      OpNum == 0 &&
787      isInt<8>(MI->getOperand(2).getImm())) {
788    // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
789    Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
790    return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
791                   get(Opcode))
792        .addFrameIndex(FrameIndex)
793        .addImm(0)
794        .addImm(MI->getOperand(2).getImm());
795  }
796
797  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
798    bool Op0IsGPR = (Opcode == SystemZ::LGDR);
799    bool Op1IsGPR = (Opcode == SystemZ::LDGR);
800    // If we're spilling the destination of an LDGR or LGDR, store the
801    // source register instead.
802    if (OpNum == 0) {
803      unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
804      return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
805                     get(StoreOpcode))
806          .addOperand(MI->getOperand(1))
807          .addFrameIndex(FrameIndex)
808          .addImm(0)
809          .addReg(0);
810    }
811    // If we're spilling the source of an LDGR or LGDR, load the
812    // destination register instead.
813    if (OpNum == 1) {
814      unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
815      unsigned Dest = MI->getOperand(0).getReg();
816      return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
817                     get(LoadOpcode), Dest)
818          .addFrameIndex(FrameIndex)
819          .addImm(0)
820          .addReg(0);
821    }
822  }
823
824  // Look for cases where the source of a simple store or the destination
825  // of a simple load is being spilled.  Try to use MVC instead.
826  //
827  // Although MVC is in practice a fast choice in these cases, it is still
828  // logically a bytewise copy.  This means that we cannot use it if the
829  // load or store is volatile.  We also wouldn't be able to use MVC if
830  // the two memories partially overlap, but that case cannot occur here,
831  // because we know that one of the memories is a full frame index.
832  //
833  // For performance reasons, we also want to avoid using MVC if the addresses
834  // might be equal.  We don't worry about that case here, because spill slot
835  // coloring happens later, and because we have special code to remove
836  // MVCs that turn out to be redundant.
837  if (OpNum == 0 && MI->hasOneMemOperand()) {
838    MachineMemOperand *MMO = *MI->memoperands_begin();
839    if (MMO->getSize() == Size && !MMO->isVolatile()) {
840      // Handle conversion of loads.
841      if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
842        return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
843                       get(SystemZ::MVC))
844            .addFrameIndex(FrameIndex)
845            .addImm(0)
846            .addImm(Size)
847            .addOperand(MI->getOperand(1))
848            .addImm(MI->getOperand(2).getImm())
849            .addMemOperand(MMO);
850      }
851      // Handle conversion of stores.
852      if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
853        return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
854                       get(SystemZ::MVC))
855            .addOperand(MI->getOperand(1))
856            .addImm(MI->getOperand(2).getImm())
857            .addImm(Size)
858            .addFrameIndex(FrameIndex)
859            .addImm(0)
860            .addMemOperand(MMO);
861      }
862    }
863  }
864
865  // If the spilled operand is the final one, try to change <INSN>R
866  // into <INSN>.
867  int MemOpcode = SystemZ::getMemOpcode(Opcode);
868  if (MemOpcode >= 0) {
869    unsigned NumOps = MI->getNumExplicitOperands();
870    if (OpNum == NumOps - 1) {
871      const MCInstrDesc &MemDesc = get(MemOpcode);
872      uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
873      assert(AccessBytes != 0 && "Size of access should be known");
874      assert(AccessBytes <= Size && "Access outside the frame index");
875      uint64_t Offset = Size - AccessBytes;
876      MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
877                                        MI->getDebugLoc(), get(MemOpcode));
878      for (unsigned I = 0; I < OpNum; ++I)
879        MIB.addOperand(MI->getOperand(I));
880      MIB.addFrameIndex(FrameIndex).addImm(Offset);
881      if (MemDesc.TSFlags & SystemZII::HasIndex)
882        MIB.addReg(0);
883      return MIB;
884    }
885  }
886
887  return nullptr;
888}
889
890MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
891    MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
892    MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
893  return nullptr;
894}
895
896bool
897SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
898  switch (MI->getOpcode()) {
899  case SystemZ::L128:
900    splitMove(MI, SystemZ::LG);
901    return true;
902
903  case SystemZ::ST128:
904    splitMove(MI, SystemZ::STG);
905    return true;
906
907  case SystemZ::LX:
908    splitMove(MI, SystemZ::LD);
909    return true;
910
911  case SystemZ::STX:
912    splitMove(MI, SystemZ::STD);
913    return true;
914
915  case SystemZ::LBMux:
916    expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
917    return true;
918
919  case SystemZ::LHMux:
920    expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
921    return true;
922
923  case SystemZ::LLCRMux:
924    expandZExtPseudo(MI, SystemZ::LLCR, 8);
925    return true;
926
927  case SystemZ::LLHRMux:
928    expandZExtPseudo(MI, SystemZ::LLHR, 16);
929    return true;
930
931  case SystemZ::LLCMux:
932    expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
933    return true;
934
935  case SystemZ::LLHMux:
936    expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
937    return true;
938
939  case SystemZ::LMux:
940    expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
941    return true;
942
943  case SystemZ::STCMux:
944    expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
945    return true;
946
947  case SystemZ::STHMux:
948    expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
949    return true;
950
951  case SystemZ::STMux:
952    expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
953    return true;
954
955  case SystemZ::LHIMux:
956    expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
957    return true;
958
959  case SystemZ::IIFMux:
960    expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
961    return true;
962
963  case SystemZ::IILMux:
964    expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
965    return true;
966
967  case SystemZ::IIHMux:
968    expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
969    return true;
970
971  case SystemZ::NIFMux:
972    expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
973    return true;
974
975  case SystemZ::NILMux:
976    expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
977    return true;
978
979  case SystemZ::NIHMux:
980    expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
981    return true;
982
983  case SystemZ::OIFMux:
984    expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
985    return true;
986
987  case SystemZ::OILMux:
988    expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
989    return true;
990
991  case SystemZ::OIHMux:
992    expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
993    return true;
994
995  case SystemZ::XIFMux:
996    expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
997    return true;
998
999  case SystemZ::TMLMux:
1000    expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1001    return true;
1002
1003  case SystemZ::TMHMux:
1004    expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1005    return true;
1006
1007  case SystemZ::AHIMux:
1008    expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1009    return true;
1010
1011  case SystemZ::AHIMuxK:
1012    expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1013    return true;
1014
1015  case SystemZ::AFIMux:
1016    expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1017    return true;
1018
1019  case SystemZ::CFIMux:
1020    expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1021    return true;
1022
1023  case SystemZ::CLFIMux:
1024    expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1025    return true;
1026
1027  case SystemZ::CMux:
1028    expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1029    return true;
1030
1031  case SystemZ::CLMux:
1032    expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1033    return true;
1034
1035  case SystemZ::RISBMux: {
1036    bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
1037    bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
1038    if (SrcIsHigh == DestIsHigh)
1039      MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1040    else {
1041      MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1042      MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
1043    }
1044    return true;
1045  }
1046
1047  case SystemZ::ADJDYNALLOC:
1048    splitAdjDynAlloc(MI);
1049    return true;
1050
1051  default:
1052    return false;
1053  }
1054}
1055
1056uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
1057  if (MI->getOpcode() == TargetOpcode::INLINEASM) {
1058    const MachineFunction *MF = MI->getParent()->getParent();
1059    const char *AsmStr = MI->getOperand(0).getSymbolName();
1060    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1061  }
1062  return MI->getDesc().getSize();
1063}
1064
1065SystemZII::Branch
1066SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
1067  switch (MI->getOpcode()) {
1068  case SystemZ::BR:
1069  case SystemZ::J:
1070  case SystemZ::JG:
1071    return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1072                             SystemZ::CCMASK_ANY, &MI->getOperand(0));
1073
1074  case SystemZ::BRC:
1075  case SystemZ::BRCL:
1076    return SystemZII::Branch(SystemZII::BranchNormal,
1077                             MI->getOperand(0).getImm(),
1078                             MI->getOperand(1).getImm(), &MI->getOperand(2));
1079
1080  case SystemZ::BRCT:
1081    return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1082                             SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1083
1084  case SystemZ::BRCTG:
1085    return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1086                             SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1087
1088  case SystemZ::CIJ:
1089  case SystemZ::CRJ:
1090    return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1091                             MI->getOperand(2).getImm(), &MI->getOperand(3));
1092
1093  case SystemZ::CLIJ:
1094  case SystemZ::CLRJ:
1095    return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1096                             MI->getOperand(2).getImm(), &MI->getOperand(3));
1097
1098  case SystemZ::CGIJ:
1099  case SystemZ::CGRJ:
1100    return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1101                             MI->getOperand(2).getImm(), &MI->getOperand(3));
1102
1103  case SystemZ::CLGIJ:
1104  case SystemZ::CLGRJ:
1105    return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1106                             MI->getOperand(2).getImm(), &MI->getOperand(3));
1107
1108  default:
1109    llvm_unreachable("Unrecognized branch opcode");
1110  }
1111}
1112
1113void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1114                                           unsigned &LoadOpcode,
1115                                           unsigned &StoreOpcode) const {
1116  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1117    LoadOpcode = SystemZ::L;
1118    StoreOpcode = SystemZ::ST;
1119  } else if (RC == &SystemZ::GRH32BitRegClass) {
1120    LoadOpcode = SystemZ::LFH;
1121    StoreOpcode = SystemZ::STFH;
1122  } else if (RC == &SystemZ::GRX32BitRegClass) {
1123    LoadOpcode = SystemZ::LMux;
1124    StoreOpcode = SystemZ::STMux;
1125  } else if (RC == &SystemZ::GR64BitRegClass ||
1126             RC == &SystemZ::ADDR64BitRegClass) {
1127    LoadOpcode = SystemZ::LG;
1128    StoreOpcode = SystemZ::STG;
1129  } else if (RC == &SystemZ::GR128BitRegClass ||
1130             RC == &SystemZ::ADDR128BitRegClass) {
1131    LoadOpcode = SystemZ::L128;
1132    StoreOpcode = SystemZ::ST128;
1133  } else if (RC == &SystemZ::FP32BitRegClass) {
1134    LoadOpcode = SystemZ::LE;
1135    StoreOpcode = SystemZ::STE;
1136  } else if (RC == &SystemZ::FP64BitRegClass) {
1137    LoadOpcode = SystemZ::LD;
1138    StoreOpcode = SystemZ::STD;
1139  } else if (RC == &SystemZ::FP128BitRegClass) {
1140    LoadOpcode = SystemZ::LX;
1141    StoreOpcode = SystemZ::STX;
1142  } else if (RC == &SystemZ::VR32BitRegClass) {
1143    LoadOpcode = SystemZ::VL32;
1144    StoreOpcode = SystemZ::VST32;
1145  } else if (RC == &SystemZ::VR64BitRegClass) {
1146    LoadOpcode = SystemZ::VL64;
1147    StoreOpcode = SystemZ::VST64;
1148  } else if (RC == &SystemZ::VF128BitRegClass ||
1149             RC == &SystemZ::VR128BitRegClass) {
1150    LoadOpcode = SystemZ::VL;
1151    StoreOpcode = SystemZ::VST;
1152  } else
1153    llvm_unreachable("Unsupported regclass to load or store");
1154}
1155
1156unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1157                                              int64_t Offset) const {
1158  const MCInstrDesc &MCID = get(Opcode);
1159  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1160  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1161    // Get the instruction to use for unsigned 12-bit displacements.
1162    int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1163    if (Disp12Opcode >= 0)
1164      return Disp12Opcode;
1165
1166    // All address-related instructions can use unsigned 12-bit
1167    // displacements.
1168    return Opcode;
1169  }
1170  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1171    // Get the instruction to use for signed 20-bit displacements.
1172    int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1173    if (Disp20Opcode >= 0)
1174      return Disp20Opcode;
1175
1176    // Check whether Opcode allows signed 20-bit displacements.
1177    if (MCID.TSFlags & SystemZII::Has20BitOffset)
1178      return Opcode;
1179  }
1180  return 0;
1181}
1182
1183unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1184  switch (Opcode) {
1185  case SystemZ::L:      return SystemZ::LT;
1186  case SystemZ::LY:     return SystemZ::LT;
1187  case SystemZ::LG:     return SystemZ::LTG;
1188  case SystemZ::LGF:    return SystemZ::LTGF;
1189  case SystemZ::LR:     return SystemZ::LTR;
1190  case SystemZ::LGFR:   return SystemZ::LTGFR;
1191  case SystemZ::LGR:    return SystemZ::LTGR;
1192  case SystemZ::LER:    return SystemZ::LTEBR;
1193  case SystemZ::LDR:    return SystemZ::LTDBR;
1194  case SystemZ::LXR:    return SystemZ::LTXBR;
1195  case SystemZ::LCDFR:  return SystemZ::LCDBR;
1196  case SystemZ::LPDFR:  return SystemZ::LPDBR;
1197  case SystemZ::LNDFR:  return SystemZ::LNDBR;
1198  case SystemZ::LCDFR_32:  return SystemZ::LCEBR;
1199  case SystemZ::LPDFR_32:  return SystemZ::LPEBR;
1200  case SystemZ::LNDFR_32:  return SystemZ::LNEBR;
1201  // On zEC12 we prefer to use RISBGN.  But if there is a chance to
1202  // actually use the condition code, we may turn it back into RISGB.
1203  // Note that RISBG is not really a "load-and-test" instruction,
1204  // but sets the same condition code values, so is OK to use here.
1205  case SystemZ::RISBGN: return SystemZ::RISBG;
1206  default:              return 0;
1207  }
1208}
1209
1210// Return true if Mask matches the regexp 0*1+0*, given that zero masks
1211// have already been filtered out.  Store the first set bit in LSB and
1212// the number of set bits in Length if so.
1213static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1214  unsigned First = findFirstSet(Mask);
1215  uint64_t Top = (Mask >> First) + 1;
1216  if ((Top & -Top) == Top) {
1217    LSB = First;
1218    Length = findFirstSet(Top);
1219    return true;
1220  }
1221  return false;
1222}
1223
1224bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1225                                   unsigned &Start, unsigned &End) const {
1226  // Reject trivial all-zero masks.
1227  Mask &= allOnes(BitSize);
1228  if (Mask == 0)
1229    return false;
1230
1231  // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
1232  // the msb and End specifies the index of the lsb.
1233  unsigned LSB, Length;
1234  if (isStringOfOnes(Mask, LSB, Length)) {
1235    Start = 63 - (LSB + Length - 1);
1236    End = 63 - LSB;
1237    return true;
1238  }
1239
1240  // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
1241  // of the low 1s and End specifies the lsb of the high 1s.
1242  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1243    assert(LSB > 0 && "Bottom bit must be set");
1244    assert(LSB + Length < BitSize && "Top bit must be set");
1245    Start = 63 - (LSB - 1);
1246    End = 63 - (LSB + Length);
1247    return true;
1248  }
1249
1250  return false;
1251}
1252
1253unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1254                                               const MachineInstr *MI) const {
1255  switch (Opcode) {
1256  case SystemZ::CR:
1257    return SystemZ::CRJ;
1258  case SystemZ::CGR:
1259    return SystemZ::CGRJ;
1260  case SystemZ::CHI:
1261    return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1262  case SystemZ::CGHI:
1263    return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1264  case SystemZ::CLR:
1265    return SystemZ::CLRJ;
1266  case SystemZ::CLGR:
1267    return SystemZ::CLGRJ;
1268  case SystemZ::CLFI:
1269    return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1270  case SystemZ::CLGFI:
1271    return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1272  default:
1273    return 0;
1274  }
1275}
1276
1277void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1278                                     MachineBasicBlock::iterator MBBI,
1279                                     unsigned Reg, uint64_t Value) const {
1280  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1281  unsigned Opcode;
1282  if (isInt<16>(Value))
1283    Opcode = SystemZ::LGHI;
1284  else if (SystemZ::isImmLL(Value))
1285    Opcode = SystemZ::LLILL;
1286  else if (SystemZ::isImmLH(Value)) {
1287    Opcode = SystemZ::LLILH;
1288    Value >>= 16;
1289  } else {
1290    assert(isInt<32>(Value) && "Huge values not handled yet");
1291    Opcode = SystemZ::LGFI;
1292  }
1293  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1294}
1295