SparcInstrAliases.td revision 262261
1262261Sdim//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===// 2262261Sdim// 3262261Sdim// The LLVM Compiler Infrastructure 4262261Sdim// 5262261Sdim// This file is distributed under the University of Illinois Open Source 6262261Sdim// License. See LICENSE.TXT for details. 7262261Sdim// 8262261Sdim//===----------------------------------------------------------------------===// 9262261Sdim// 10262261Sdim// This file contains instruction aliases for Sparc. 11262261Sdim//===----------------------------------------------------------------------===// 12262261Sdim 13262261Sdim// Instruction aliases for conditional moves. 14262261Sdim 15262261Sdim// mov<cond> <ccreg> rs2, rd 16262261Sdimmulticlass cond_mov_alias<string cond, int condVal, string ccreg, 17262261Sdim Instruction movrr, Instruction movri, 18262261Sdim Instruction fmovs, Instruction fmovd> { 19262261Sdim 20262261Sdim // mov<cond> (%icc|%xcc|%fcc0), rs2, rd 21262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 22262261Sdim ", $rs2, $rd"), 23262261Sdim (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; 24262261Sdim 25262261Sdim // mov<cond> (%icc|%xcc|%fcc0), simm11, rd 26262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 27262261Sdim ", $simm11, $rd"), 28262261Sdim (movri IntRegs:$rd, i32imm:$simm11, condVal)>; 29262261Sdim 30262261Sdim // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd 31262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg), 32262261Sdim ", $rs2, $rd"), 33262261Sdim (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; 34262261Sdim 35262261Sdim // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd 36262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg), 37262261Sdim ", $rs2, $rd"), 38262261Sdim (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>; 39262261Sdim} 40262261Sdim 41262261Sdim 42262261Sdim// Instruction aliases for integer conditional branches and moves. 43262261Sdimmulticlass int_cond_alias<string cond, int condVal> { 44262261Sdim 45262261Sdim // b<cond> $imm 46262261Sdim def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"), 47262261Sdim (BCOND brtarget:$imm, condVal)>; 48262261Sdim 49262261Sdim // b<cond> %xcc, $imm 50262261Sdim def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"), 51262261Sdim (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 52262261Sdim 53262261Sdim defm : cond_mov_alias<cond, condVal, " %icc", 54262261Sdim MOVICCrr, MOVICCri, 55262261Sdim FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>; 56262261Sdim 57262261Sdim defm : cond_mov_alias<cond, condVal, " %xcc", 58262261Sdim MOVXCCrr, MOVXCCri, 59262261Sdim FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>; 60262261Sdim 61262261Sdim // fmovq<cond> (%icc|%xcc), $rs2, $rd 62262261Sdim def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"), 63262261Sdim (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 64262261Sdim Requires<[HasV9, HasHardQuad]>; 65262261Sdim def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"), 66262261Sdim (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 67262261Sdim Requires<[Is64Bit, HasHardQuad]>; 68262261Sdim 69262261Sdim} 70262261Sdim 71262261Sdim 72262261Sdim// Instruction aliases for floating point conditional branches and moves. 73262261Sdimmulticlass fp_cond_alias<string cond, int condVal> { 74262261Sdim 75262261Sdim // fb<cond> $imm 76262261Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"), 77262261Sdim (FBCOND brtarget:$imm, condVal), 0>; 78262261Sdim 79262261Sdim defm : cond_mov_alias<cond, condVal, " %fcc0", 80262261Sdim MOVFCCrr, MOVFCCri, 81262261Sdim FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>; 82262261Sdim 83262261Sdim // fmovq<cond> %fcc0, $rs2, $rd 84262261Sdim def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"), 85262261Sdim (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 86262261Sdim Requires<[HasV9, HasHardQuad]>; 87262261Sdim} 88262261Sdim 89262261Sdimdefm : int_cond_alias<"a", 0b1000>; 90262261Sdimdefm : int_cond_alias<"n", 0b0000>; 91262261Sdimdefm : int_cond_alias<"ne", 0b1001>; 92262261Sdimdefm : int_cond_alias<"e", 0b0001>; 93262261Sdimdefm : int_cond_alias<"g", 0b1010>; 94262261Sdimdefm : int_cond_alias<"le", 0b0010>; 95262261Sdimdefm : int_cond_alias<"ge", 0b1011>; 96262261Sdimdefm : int_cond_alias<"l", 0b0011>; 97262261Sdimdefm : int_cond_alias<"gu", 0b1100>; 98262261Sdimdefm : int_cond_alias<"leu", 0b0100>; 99262261Sdimdefm : int_cond_alias<"cc", 0b1101>; 100262261Sdimdefm : int_cond_alias<"cs", 0b0101>; 101262261Sdimdefm : int_cond_alias<"pos", 0b1110>; 102262261Sdimdefm : int_cond_alias<"neg", 0b0110>; 103262261Sdimdefm : int_cond_alias<"vc", 0b1111>; 104262261Sdimdefm : int_cond_alias<"vs", 0b0111>; 105262261Sdim 106262261Sdimdefm : fp_cond_alias<"u", 0b0111>; 107262261Sdimdefm : fp_cond_alias<"g", 0b0110>; 108262261Sdimdefm : fp_cond_alias<"ug", 0b0101>; 109262261Sdimdefm : fp_cond_alias<"l", 0b0100>; 110262261Sdimdefm : fp_cond_alias<"ul", 0b0011>; 111262261Sdimdefm : fp_cond_alias<"lg", 0b0010>; 112262261Sdimdefm : fp_cond_alias<"ne", 0b0001>; 113262261Sdimdefm : fp_cond_alias<"e", 0b1001>; 114262261Sdimdefm : fp_cond_alias<"ue", 0b1010>; 115262261Sdimdefm : fp_cond_alias<"ge", 0b1011>; 116262261Sdimdefm : fp_cond_alias<"uge", 0b1100>; 117262261Sdimdefm : fp_cond_alias<"le", 0b1101>; 118262261Sdimdefm : fp_cond_alias<"ule", 0b1110>; 119262261Sdimdefm : fp_cond_alias<"o", 0b1111>; 120262261Sdim 121262261Sdim 122262261Sdim// Instruction aliases for JMPL. 123262261Sdim 124262261Sdim// jmp addr -> jmpl addr, %g0 125262261Sdimdef : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>; 126262261Sdimdef : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>; 127262261Sdim 128262261Sdim// call addr -> jmpl addr, %o7 129262261Sdimdef : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>; 130262261Sdimdef : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>; 131262261Sdim 132262261Sdim// retl -> RETL 8 133262261Sdimdef : InstAlias<"retl", (RETL 8)>; 134262261Sdim 135262261Sdim// ret -> RET 8 136262261Sdimdef : InstAlias<"ret", (RET 8)>; 137262261Sdim 138262261Sdim// mov reg, rd -> or %g0, reg, rd 139262261Sdimdef : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; 140262261Sdim 141262261Sdim// mov simm13, rd -> or %g0, simm13, rd 142262261Sdimdef : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; 143