SparcInstrAliases.td revision 262261
1246149Ssjg//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===// 2246149Ssjg// 3246149Ssjg// The LLVM Compiler Infrastructure 4246149Ssjg// 5246149Ssjg// This file is distributed under the University of Illinois Open Source 6246149Ssjg// License. See LICENSE.TXT for details. 7246149Ssjg// 8246149Ssjg//===----------------------------------------------------------------------===// 9246149Ssjg// 10246149Ssjg// This file contains instruction aliases for Sparc. 11246149Ssjg//===----------------------------------------------------------------------===// 12246149Ssjg 13246149Ssjg// Instruction aliases for conditional moves. 14246149Ssjg 15246149Ssjg// mov<cond> <ccreg> rs2, rd 16246149Ssjgmulticlass cond_mov_alias<string cond, int condVal, string ccreg, 17246149Ssjg Instruction movrr, Instruction movri, 18246149Ssjg Instruction fmovs, Instruction fmovd> { 19246149Ssjg 20246149Ssjg // mov<cond> (%icc|%xcc|%fcc0), rs2, rd 21246149Ssjg def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 22246149Ssjg ", $rs2, $rd"), 23246149Ssjg (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; 24246149Ssjg 25246149Ssjg // mov<cond> (%icc|%xcc|%fcc0), simm11, rd 26246149Ssjg def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 27246149Ssjg ", $simm11, $rd"), 28246149Ssjg (movri IntRegs:$rd, i32imm:$simm11, condVal)>; 29246149Ssjg 30246149Ssjg // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd 31246149Ssjg def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg), 32246149Ssjg ", $rs2, $rd"), 33246149Ssjg (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; 34246149Ssjg 35246149Ssjg // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd 36246149Ssjg def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg), 37246149Ssjg ", $rs2, $rd"), 38246149Ssjg (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>; 39246149Ssjg} 40246149Ssjg 41246149Ssjg 42246149Ssjg// Instruction aliases for integer conditional branches and moves. 43246149Ssjgmulticlass int_cond_alias<string cond, int condVal> { 44246149Ssjg 45246149Ssjg // b<cond> $imm 46246149Ssjg def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"), 47246149Ssjg (BCOND brtarget:$imm, condVal)>; 48246149Ssjg 49246149Ssjg // b<cond> %xcc, $imm 50246149Ssjg def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"), 51246149Ssjg (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 52246149Ssjg 53246149Ssjg defm : cond_mov_alias<cond, condVal, " %icc", 54246149Ssjg MOVICCrr, MOVICCri, 55246149Ssjg FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>; 56246149Ssjg 57246149Ssjg defm : cond_mov_alias<cond, condVal, " %xcc", 58246149Ssjg MOVXCCrr, MOVXCCri, 59246149Ssjg FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>; 60246149Ssjg 61246149Ssjg // fmovq<cond> (%icc|%xcc), $rs2, $rd 62246149Ssjg def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"), 63246149Ssjg (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 64246149Ssjg Requires<[HasV9, HasHardQuad]>; 65246149Ssjg def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"), 66246149Ssjg (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 67246149Ssjg Requires<[Is64Bit, HasHardQuad]>; 68246149Ssjg 69246149Ssjg} 70246149Ssjg 71246149Ssjg 72246149Ssjg// Instruction aliases for floating point conditional branches and moves. 73246149Ssjgmulticlass fp_cond_alias<string cond, int condVal> { 74246149Ssjg 75246149Ssjg // fb<cond> $imm 76246149Ssjg def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"), 77246149Ssjg (FBCOND brtarget:$imm, condVal), 0>; 78246149Ssjg 79246149Ssjg defm : cond_mov_alias<cond, condVal, " %fcc0", 80246149Ssjg MOVFCCrr, MOVFCCri, 81246149Ssjg FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>; 82246149Ssjg 83246149Ssjg // fmovq<cond> %fcc0, $rs2, $rd 84246149Ssjg def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"), 85246149Ssjg (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 86246149Ssjg Requires<[HasV9, HasHardQuad]>; 87246149Ssjg} 88246149Ssjg 89246149Ssjgdefm : int_cond_alias<"a", 0b1000>; 90246149Ssjgdefm : int_cond_alias<"n", 0b0000>; 91246149Ssjgdefm : int_cond_alias<"ne", 0b1001>; 92246149Ssjgdefm : int_cond_alias<"e", 0b0001>; 93246149Ssjgdefm : int_cond_alias<"g", 0b1010>; 94246149Ssjgdefm : int_cond_alias<"le", 0b0010>; 95246149Ssjgdefm : int_cond_alias<"ge", 0b1011>; 96246149Ssjgdefm : int_cond_alias<"l", 0b0011>; 97246149Ssjgdefm : int_cond_alias<"gu", 0b1100>; 98246149Ssjgdefm : int_cond_alias<"leu", 0b0100>; 99246149Ssjgdefm : int_cond_alias<"cc", 0b1101>; 100246149Ssjgdefm : int_cond_alias<"cs", 0b0101>; 101246149Ssjgdefm : int_cond_alias<"pos", 0b1110>; 102246149Ssjgdefm : int_cond_alias<"neg", 0b0110>; 103246149Ssjgdefm : int_cond_alias<"vc", 0b1111>; 104246149Ssjgdefm : int_cond_alias<"vs", 0b0111>; 105246149Ssjg 106246149Ssjgdefm : fp_cond_alias<"u", 0b0111>; 107246149Ssjgdefm : fp_cond_alias<"g", 0b0110>; 108246149Ssjgdefm : fp_cond_alias<"ug", 0b0101>; 109246149Ssjgdefm : fp_cond_alias<"l", 0b0100>; 110246149Ssjgdefm : fp_cond_alias<"ul", 0b0011>; 111246149Ssjgdefm : fp_cond_alias<"lg", 0b0010>; 112246149Ssjgdefm : fp_cond_alias<"ne", 0b0001>; 113246149Ssjgdefm : fp_cond_alias<"e", 0b1001>; 114246149Ssjgdefm : fp_cond_alias<"ue", 0b1010>; 115246149Ssjgdefm : fp_cond_alias<"ge", 0b1011>; 116246149Ssjgdefm : fp_cond_alias<"uge", 0b1100>; 117246149Ssjgdefm : fp_cond_alias<"le", 0b1101>; 118246149Ssjgdefm : fp_cond_alias<"ule", 0b1110>; 119246149Ssjgdefm : fp_cond_alias<"o", 0b1111>; 120246149Ssjg 121246149Ssjg 122246149Ssjg// Instruction aliases for JMPL. 123246149Ssjg 124246149Ssjg// jmp addr -> jmpl addr, %g0 125246149Ssjgdef : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>; 126246149Ssjgdef : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>; 127246149Ssjg 128246149Ssjg// call addr -> jmpl addr, %o7 129246149Ssjgdef : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>; 130246149Ssjgdef : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>; 131246149Ssjg 132246149Ssjg// retl -> RETL 8 133246149Ssjgdef : InstAlias<"retl", (RETL 8)>; 134246149Ssjg 135246149Ssjg// ret -> RET 8 136246149Ssjgdef : InstAlias<"ret", (RET 8)>; 137246149Ssjg 138246149Ssjg// mov reg, rd -> or %g0, reg, rd 139246149Ssjgdef : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; 140246149Ssjg 141246149Ssjg// mov simm13, rd -> or %g0, simm13, rd 142246149Ssjgdef : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; 143246149Ssjg